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| Hitachi Single-Chip Microcomputer H8S/2138 Series H8S/2134 Series H8S/2138F-ZTATTM H8S/2134F-ZTATTM H8S/2138 HD6432138W, HD6432138, HD64F2138, HD64F2138V H8S/2137 HD6432137W, HD6432137 H8S/2134 HD6432134, HD64F2134, HD64F2134V H8S/2133 HD6432133 H8S/2132 HD6432132, HD64F2132R, HD64F2132V H8S/2130 HD6432130 Hardware Manual ADE-602-144A Rev. 2.0 3/12/99 (c) Hitachi, Ltd. 1997 Notice When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Contents Contents ..... .....................................................................................................i Preface ....... .....................................................................................................1 Section 1 Overview ........................................................................................3 1.1 Overview ......................................................................................................................... 3 1.2 Internal Block Diagram.................................................................................................... 8 1.3 Pin Arrangement and Functions ....................................................................................... 10 1.3.1 Pin Arrangement................................................................................................. 10 1.3.2 Pin Functions in Each Operating Mode ............................................................... 12 1.3.3 Pin Functions ...................................................................................................... 19 Section 2 CPU................................................................................................25 2.1 Overview ......................................................................................................................... 25 2.1.1 Features .............................................................................................................. 25 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ................................... 26 2.1.3 Differences from H8/300 CPU ............................................................................ 27 2.1.4 Differences from H8/300H CPU ......................................................................... 27 2.2 CPU Operating Modes ..................................................................................................... 28 2.3 Address Space.................................................................................................................. 33 2.4 Register Configuration ..................................................................................................... 34 2.4.1 Overview ............................................................................................................ 34 2.4.2 General Registers................................................................................................ 35 2.4.3 Control Registers ................................................................................................ 36 2.4.4 Initial Register Values ........................................................................................ 37 2.5 Data Formats.................................................................................................................... 38 2.5.1 General Register Data Formats ........................................................................... 38 2.5.2 Memory Data Formats ........................................................................................ 40 2.6 Instruction Set.................................................................................................................. 41 2.6.1 Overview ............................................................................................................ 41 2.6.2 Instructions and Addressing Modes..................................................................... 42 2.6.3 Table of Instructions Classified by Function ....................................................... 44 2.6.4 Basic Instruction Formats ................................................................................... 54 2.6.5 Notes on Use of Bit-Manipulation Instructions.................................................... 55 2.7 Addressing Modes and Effective Address Calculation...................................................... 55 2.7.1 Addressing Mode................................................................................................ 55 2.7.2 Effective Address Calculation............................................................................. 59 i 2.8 Processing States.............................................................................................................. 62 2.8.1 Overview ............................................................................................................ 62 2.8.2 Reset State.......................................................................................................... 64 2.8.3 Exception-Handling State ................................................................................... 64 2.8.4 Program Execution State..................................................................................... 65 2.8.5 Bus-Released State ............................................................................................. 66 2.8.6 Power-Down State .............................................................................................. 66 2.9 Basic Timing ................................................................................................................... 67 2.9.1 Overview ............................................................................................................ 67 2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 67 2.9.3 On-Chip Supporting Module Access Timing....................................................... 69 2.9.4 External Address Space Access Timing .............................................................. 70 Section 3 MCU Operating Modes .................................................................. 71 3.1 Overview ......................................................................................................................... 71 3.1.1 Operating Mode Selection .................................................................................. 71 3.1.2 Register Configuration........................................................................................ 72 3.2 Register Descriptions ....................................................................................................... 72 3.2.1 Mode Control Register (MDCR)......................................................................... 72 3.2.2 System Control Register (SYSCR)...................................................................... 73 3.2.3 Bus Control Register (BCR) ............................................................................... 75 3.2.4 Serial Timer Control Register (STCR) ................................................................ 76 3.3 Operating Mode Descriptions........................................................................................... 77 3.3.1 Mode 1 ............................................................................................................... 77 3.3.2 Mode 2 ............................................................................................................... 77 3.3.3 Mode 3 ............................................................................................................... 78 3.4 Pin Functions in Each Operating Mode ............................................................................ 78 3.5 Memory Map in Each Operating Mode ............................................................................ 79 Section 4 Exception Handling ........................................................................ 89 4.1 Overview ......................................................................................................................... 89 4.1.1 Exception Handling Types and Priority............................................................... 89 4.1.2 Exception Handling Operation............................................................................ 90 4.1.3 Exception Sources and Vector Table................................................................... 90 4.2 Reset................................................................................................................................ 92 4.2.1 Overview ............................................................................................................ 92 4.2.2 Reset Sequence................................................................................................... 92 4.2.3 Interrupts after Reset........................................................................................... 94 4.3 Interrupts ......................................................................................................................... 95 4.4 Trap Instruction ............................................................................................................... 96 4.5 Stack Status after Exception Handling ............................................................................. 97 4.6 Notes on Use of the Stack ................................................................................................ 98 ii Section 5 Interrupt Controller.........................................................................99 5.1 Overview ......................................................................................................................... 99 5.1.1 Features .............................................................................................................. 99 5.1.2 Block Diagram.................................................................................................... 100 5.1.3 Pin Configuration................................................................................................ 101 5.1.4 Register Configuration........................................................................................ 101 5.2 Register Descriptions ....................................................................................................... 102 5.2.1 System Control Register (SYSCR)...................................................................... 102 5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 103 5.2.3 IRQ Enable Register (IER) ................................................................................. 104 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 105 5.2.5 IRQ Status Register (ISR) ................................................................................... 106 5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR) .......................................... 107 5.2.7 Address Break Control Register (ABRKCR)....................................................... 108 5.2.8 Break Address Registers A, B, C (BARA, BARB, BARC).................................. 109 5.3 Interrupt Sources.............................................................................................................. 110 5.3.1 External Interrupts .............................................................................................. 110 5.3.2 Internal Interrupts ............................................................................................... 112 5.3.3 Interrupt Exception Vector Table........................................................................ 112 5.4 Address Breaks ................................................................................................................ 115 5.4.1 Features .............................................................................................................. 115 5.4.2 Block Diagram.................................................................................................... 115 5.4.3 Operation............................................................................................................ 116 5.4.4 Usage Notes........................................................................................................ 116 5.5 Interrupt Operation........................................................................................................... 118 5.5.1 Interrupt Control Modes and Interrupt Operation ................................................ 118 5.5.2 Interrupt Control Mode 0 .................................................................................... 121 5.5.3 Interrupt Control Mode 1 .................................................................................... 123 5.5.4 Interrupt Exception Handling Sequence .............................................................. 126 5.5.5 Interrupt Response Times ................................................................................... 127 5.6 Usage Notes..................................................................................................................... 128 5.6.1 Contention between Interrupt Generation and Disabling ..................................... 128 5.6.2 Instructions that Disable Interrupts...................................................................... 129 5.6.3 Interrupts during Execution of EEPMOV Instruction .......................................... 129 5.7 DTC Activation by Interrupt ............................................................................................ 130 5.7.1 Overview ............................................................................................................ 130 5.7.2 Block Diagram.................................................................................................... 130 5.7.3 Operation............................................................................................................ 131 iii Section 6 Bus Controller ................................................................................ 133 6.1 Overview ......................................................................................................................... 133 6.1.1 Features .............................................................................................................. 133 6.1.2 Block Diagram ................................................................................................... 134 6.1.3 Pin Configuration ............................................................................................... 135 6.1.4 Register Configuration........................................................................................ 135 6.2 Register Descriptions ....................................................................................................... 136 6.2.1 Bus Control Register (BCR) ............................................................................... 136 6.2.2 Wait State Control Register (WSCR).................................................................. 137 6.3 Overview of Bus Control ................................................................................................. 139 6.3.1 Bus Specifications .............................................................................................. 139 6.3.2 Advanced Mode.................................................................................................. 140 6.3.3 Normal Mode ..................................................................................................... 141 6.3.4 I/O Select Signal................................................................................................. 141 6.4 Basic Bus Interface .......................................................................................................... 142 6.4.1 Overview ............................................................................................................ 142 6.4.2 Data Size and Data Alignment............................................................................ 142 6.4.3 Valid Strobes ...................................................................................................... 144 6.4.4 Basic Timing ...................................................................................................... 145 6.4.5 Wait Control....................................................................................................... 147 6.5 Burst ROM Interface........................................................................................................ 149 6.5.1 Overview ............................................................................................................ 149 6.5.2 Basic Timing ...................................................................................................... 149 6.5.3 Wait Control....................................................................................................... 151 6.6 Idle Cycle ........................................................................................................................ 151 6.6.1 Operation............................................................................................................ 151 6.6.2 Pin States in Idle Cycle....................................................................................... 152 6.7 Bus Arbitration ................................................................................................................ 152 6.7.1 Overview ............................................................................................................ 152 6.7.2 Operation............................................................................................................ 152 6.7.3 Bus Transfer Timing........................................................................................... 153 Section 7 Data Transfer Controller [H8S/2138 Series] ................................... 155 7.1 Overview ......................................................................................................................... 155 7.1.1 Features .............................................................................................................. 155 7.1.2 Block Diagram ................................................................................................... 156 7.1.3 Register Configuration........................................................................................ 157 7.2 Register Descriptions ....................................................................................................... 158 7.2.1 DTC Mode Register A (MRA)............................................................................ 158 7.2.2 DTC Mode Register B (MRB) ............................................................................ 160 7.2.3 DTC Source Address Register (SAR).................................................................. 161 7.2.4 DTC Destination Address Register (DAR).......................................................... 161 iv 7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 161 7.2.6 DTC Transfer Count Register B (CRB)............................................................... 162 7.2.7 DTC Enable Registers (DTCER) ........................................................................ 162 7.2.8 DTC Vector Register (DTVECR) ....................................................................... 163 7.2.9 Module Stop Control Register (MSTPCR) .......................................................... 164 7.3 Operation ......................................................................................................................... 165 7.3.1 Overview ............................................................................................................ 165 7.3.2 Activation Sources.............................................................................................. 167 7.3.3 DTC Vector Table .............................................................................................. 169 7.3.4 Location of Register Information in Address Space ............................................ 171 7.3.5 Normal Mode...................................................................................................... 172 7.3.6 Repeat Mode....................................................................................................... 173 7.3.7 Block Transfer Mode .......................................................................................... 174 7.3.8 Chain Transfer .................................................................................................... 176 7.3.9 Operation Timing ............................................................................................... 177 7.3.10 Number of DTC Execution States ..................................................................... 178 7.3.11 Procedures for Using the DTC .......................................................................... 179 7.3.12 Examples of Use of the DTC ............................................................................ 180 7.4 Interrupts ......................................................................................................................... 181 7.5 Usage Notes..................................................................................................................... 182 Section 8 I/O Ports .........................................................................................183 8.1 Overview ......................................................................................................................... 183 8.2 Port 1 ............................................................................................................................... 190 8.2.1 Overview ............................................................................................................ 190 8.2.2 Register Configuration........................................................................................ 191 8.2.3 Pin Functions in Each Mode ............................................................................... 193 8.2.4 MOS Input Pull-Up Function .............................................................................. 195 8.3 Port 2 ............................................................................................................................... 195 8.3.1 Overview ............................................................................................................ 195 8.3.2 Register Configuration........................................................................................ 197 8.3.3 Pin Functions in Each Mode ............................................................................... 199 8.3.4 MOS Input Pull-Up Function .............................................................................. 201 8.4 Port 3 ............................................................................................................................... 202 8.4.1 Overview ............................................................................................................ 202 8.4.2 Register Configuration........................................................................................ 203 8.4.3 Pin Functions in Each Mode ............................................................................... 205 8.4.4 MOS Input Pull-Up Function .............................................................................. 206 8.5 Port 4 ............................................................................................................................... 207 8.5.1 Overview ............................................................................................................ 207 8.5.2 Register Configuration........................................................................................ 207 8.5.3 Pin Functions ...................................................................................................... 209 v 8.6 Port 5 ............................................................................................................................... 212 8.6.1 Overview ............................................................................................................ 212 8.6.2 Register Configuration........................................................................................ 212 8.6.3 Pin Functions...................................................................................................... 214 8.7 Port 6 ............................................................................................................................... 215 8.7.1 Overview ............................................................................................................ 215 8.7.2 Register Configuration........................................................................................ 216 8.7.3 Pin Functions...................................................................................................... 219 8.7.4 MOS Input Pull-Up Function .............................................................................. 221 8.8 Port 7 ............................................................................................................................... 222 8.8.1 Overview ............................................................................................................ 222 8.8.2 Register Configuration........................................................................................ 222 8.8.3 Pin Functions...................................................................................................... 223 8.9 Port 8 ............................................................................................................................... 223 8.9.1 Overview ............................................................................................................ 223 8.9.2 Register Configuration........................................................................................ 224 8.9.3 Pin Functions...................................................................................................... 225 8.10 Port 9 ............................................................................................................................. 228 8.10.1 Overview .......................................................................................................... 228 8.10.2 Register Configuration...................................................................................... 229 8.10.3 Pin Functions .................................................................................................... 231 Section 9 8-Bit PWM Timers [H8S/2138 Series] ........................................... 235 9.1 Overview ......................................................................................................................... 235 9.1.1 Features .............................................................................................................. 235 9.1.2 Block Diagram ................................................................................................... 236 9.1.3 Pin Configuration ............................................................................................... 237 9.1.4 Register Configuration........................................................................................ 237 9.2 Register Descriptions ....................................................................................................... 238 9.2.1 PWM Register Select (PWSL) ............................................................................ 238 9.2.2 PWM Data Registers (PWDR0 to PWDR15) ...................................................... 240 9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)..................... 241 9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) .................. 242 9.2.5 Peripheral Clock Select Register (PCSR) ............................................................ 243 9.2.6 Port 1 Data Direction Register (P1DDR)............................................................. 244 9.2.7 Port 2 Data Direction Register (P2DDR)............................................................. 245 9.2.8 Port 1 Data Register (P1DR)............................................................................... 246 9.2.9 Port 2 Data Register (P2DR)............................................................................... 247 9.2.10 Module Stop Control Register (MSTPCR) ........................................................ 248 9.3 Operation......................................................................................................................... 249 9.3.1 Correspondence between PWM Data Register Contents and Output Waveform.. 249 vi Section 10 14-Bit PWM D/A..........................................................................251 10.1 Overview ....................................................................................................................... 251 10.1.1 Features ............................................................................................................ 251 10.1.2 Block Diagram.................................................................................................. 252 10.1.3 Pin Configuration.............................................................................................. 252 10.1.4 Register Configuration...................................................................................... 253 10.2 Register Descriptions ..................................................................................................... 254 10.2.1 PWM D/A Counter (DACNT)........................................................................... 254 10.2.2 D/A Data Registers A and B (DADRA and DADRB)........................................ 255 10.2.3 PWM D/A Control Register (DACR) ................................................................ 257 10.2.4 Module Stop Control Register (MSTPCR) ........................................................ 259 10.3 Bus Master Interface ...................................................................................................... 260 10.4 Operation ....................................................................................................................... 263 Section 11 16-Bit Free-Running Timer...........................................................267 11.1 Overview ....................................................................................................................... 267 11.1.1 Features ............................................................................................................ 267 11.1.2 Block Diagram.................................................................................................. 268 11.1.3 Input and Output Pins ....................................................................................... 269 11.1.4 Register Configuration...................................................................................... 270 11.2 Register Descriptions ..................................................................................................... 271 11.2.1 Free-Running Counter (FRC)............................................................................ 271 11.2.2 Output Compare Registers A and B (OCRA, OCRB) ........................................ 272 11.2.3 Input Capture Registers A to D (ICRA to ICRD)............................................... 273 11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) .............................. 274 11.2.5 Output Compare Register DM (OCRDM) ......................................................... 275 11.2.6 Timer Interrupt Enable Register (TIER)............................................................ 275 11.2.7 Timer Control/Status Register (TCSR).............................................................. 278 11.2.8 Timer Control Register (TCR) .......................................................................... 282 11.2.9 Timer Output Compare Control Register (TOCR)............................................. 284 11.2.10 Module Stop Control Register (MSTPCR) ...................................................... 286 11.3 Operation ....................................................................................................................... 287 11.3.1 FRC Increment Timing ..................................................................................... 287 11.3.2 Output Compare Output Timing........................................................................ 288 11.3.3 FRC Clear Timing ............................................................................................ 289 11.3.4 Input Capture Input Timing............................................................................... 289 11.3.5 Timing of Input Capture Flag (ICF) Setting ...................................................... 291 11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)............................... 292 11.3.7 Setting of FRC Overflow Flag (OVF) ............................................................... 293 11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF ........................................ 294 11.3.9 ICRD and OCRDM Mask Signal Generation .................................................... 295 11.4 Interrupts........................................................................................................................ 296 vii 11.5 Sample Application........................................................................................................ 296 11.6 Usage Notes................................................................................................................... 297 Section 12 8-Bit Timers ................................................................................. 303 12.1 Overview ....................................................................................................................... 303 12.1.1 Features ............................................................................................................ 303 12.1.2 Block Diagram.................................................................................................. 304 12.1.3 Pin Configuration.............................................................................................. 305 12.1.4 Register Configuration...................................................................................... 306 12.2 Register Descriptions ..................................................................................................... 307 12.2.1 Timer Counter (TCNT)..................................................................................... 307 12.2.2 Time Constant Register A (TCORA) ................................................................ 308 12.2.3 Time Constant Register B (TCORB)................................................................. 309 12.2.4 Timer Control Register (TCR) .......................................................................... 310 12.2.5 Timer Control/Status Register (TCSR).............................................................. 314 12.2.6 Serial/Timer Control Register (STCR) .............................................................. 318 12.2.7 System Control Register (SYSCR).................................................................... 319 12.2.8 Timer Connection Register S (TCONRS).......................................................... 320 12.2.9 Input Capture Register (TICR) [TMRX Additional Function] ........................... 321 12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function] ................ 321 12.2.11 Input Capture Registers R and F (TICRR, TICRF).......................................... 321 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function] .................. 322 12.2.13 Module Stop Control Register (MSTPCR) ...................................................... 323 12.3 Operation ....................................................................................................................... 324 12.3.1 TCNT Incrementation Timing .......................................................................... 324 12.3.2 Compare-Match Timing.................................................................................... 325 12.3.3 TCNT External Reset Timing ........................................................................... 326 12.3.4 Timing of Overflow Flag (OVF) Setting ........................................................... 327 12.3.5 Operation with Cascaded Connection................................................................ 327 12.4 Interrupt Sources............................................................................................................ 328 12.5 8-Bit Timer Application Example .................................................................................. 329 12.6 Usage Notes................................................................................................................... 330 12.6.1 Contention between TCNT Write and Clear...................................................... 330 12.6.2 Contention between TCNT Write and Increment .............................................. 331 12.6.3 Contention between TCOR Write and Compare-Match..................................... 332 12.6.4 Contention between Compare-Matches A and B ............................................... 333 12.6.5 Switching of Internal Clocks and TCNT Operation........................................... 333 Section 13 Timer Connection [H8S/2138 Series] ........................................... 337 13.1 Overview ....................................................................................................................... 337 13.1.1 Features ............................................................................................................ 337 13.1.2 Block Diagram.................................................................................................. 338 13.1.3 Input and Output Pins ....................................................................................... 339 viii 13.1.4 Register Configuration...................................................................................... 340 13.2 Register Descriptions ..................................................................................................... 340 13.2.1 Timer Connection Register I (TCONRI) ........................................................... 340 13.2.2 Timer Connection Register O (TCONRO) ........................................................ 343 13.2.3 Timer Connection Register S (TCONRS).......................................................... 345 13.2.4 Edge Sense Register (SEDGR).......................................................................... 347 13.2.5 Module Stop Control Register (MSTPCR) ........................................................ 350 13.3 Operation ....................................................................................................................... 351 13.3.1 PWM Decoding (PDC Signal Generation) ........................................................ 351 13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) .................... 352 13.3.3 Measurement of 8-Bit Timer Divided Waveform Period ................................... 354 13.3.4 IHI Signal and 2fH Modification....................................................................... 356 13.3.5 IVI Signal Fall Modification and IHI Synchronization ...................................... 358 13.3.6 Internal Synchronization Signal Generation ...................................................... 359 13.3.7 HSYNCO Output .............................................................................................. 362 13.3.8 VSYNCO Output .............................................................................................. 363 13.3.9 CBLANK Output .............................................................................................. 364 Section 14 Watchdog Timer (WDT)...............................................................365 14.1 Overview ....................................................................................................................... 365 14.1.1 Features ............................................................................................................ 365 14.1.2 Block Diagram.................................................................................................. 366 14.1.3 Pin Configuration.............................................................................................. 367 14.1.4 Register Configuration...................................................................................... 368 14.2 Register Descriptions ..................................................................................................... 368 14.2.1 Timer Counter (TCNT)..................................................................................... 368 14.2.2 Timer Control/Status Register (TCSR).............................................................. 369 14.2.3 System Control Register (SYSCR).................................................................... 373 14.2.4 Notes on Register Access.................................................................................. 374 14.3 Operation ....................................................................................................................... 375 14.3.1 Watchdog Timer Operation............................................................................... 375 14.3.2 Interval Timer Operation .................................................................................. 376 14.3.3 Timing of Setting of Overflow Flag (OVF) ....................................................... 376 14.4 Interrupts........................................................................................................................ 377 14.5 Usage Notes ................................................................................................................... 377 14.5.1 Contention between Timer Counter (TCNT) Write and Increment .................... 377 14.5.2 Changing Value of CKS2 to CKS0 ................................................................... 378 14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode............... 378 14.5.4 Counter Value in Transitions between High-Speed Mode, ................................ 378 ix Section 15 Serial Communication Interface (SCI, IrDA)................................ 379 15.1 Overview ....................................................................................................................... 379 15.1.1 Features ............................................................................................................ 379 15.1.2 Block Diagram.................................................................................................. 381 15.1.3 Pin Configuration.............................................................................................. 382 15.1.4 Register Configuration...................................................................................... 383 15.2 Register Descriptions ..................................................................................................... 384 15.2.1 Receive Shift Register (RSR)............................................................................ 384 15.2.2 Receive Data Register (RDR) ........................................................................... 384 15.2.3 Transmit Shift Register (TSR) .......................................................................... 385 15.2.4 Transmit Data Register (TDR) .......................................................................... 385 15.2.5 Serial Mode Register (SMR)............................................................................. 386 15.2.6 Serial Control Register (SCR)........................................................................... 389 15.2.7 Serial Status Register (SSR).............................................................................. 393 15.2.8 Bit Rate Register (BRR) ................................................................................... 397 15.2.9 Serial Interface Mode Register (SCMR)............................................................ 405 15.2.10 Module Stop Control Register (MSTPCR) ...................................................... 406 15.2.11 Keyboard Comparator Control Register (KBCOMP)....................................... 408 15.3 Operation ....................................................................................................................... 409 15.3.1 Overview .......................................................................................................... 409 15.3.2 Operation in Asynchronous Mode..................................................................... 411 15.3.3 Multiprocessor Communication Function.......................................................... 422 15.3.4 Operation in Synchronous Mode ....................................................................... 430 15.3.5 IrDA Operation................................................................................................. 439 15.4 SCI Interrupts................................................................................................................. 442 15.5 Usage Notes................................................................................................................... 443 Section 16 I2C Bus Interface [H8S/2138 Series Option] ................................. 447 16.1 Overview ....................................................................................................................... 447 16.1.1 Features ............................................................................................................ 447 16.1.2 Block Diagram.................................................................................................. 449 16.1.3 Input/Output Pins.............................................................................................. 450 16.1.4 Register Configuration...................................................................................... 451 16.2 Register Descriptions ..................................................................................................... 452 2 16.2.1 I C Bus Data Register (ICDR)........................................................................... 452 16.2.2 Slave Address Register (SAR) .......................................................................... 455 16.2.3 Second Slave Address Register (SARX) ........................................................... 457 2 16.2.4 I C Bus Mode Register (ICMR) ........................................................................ 458 2 16.2.5 I C Bus Control Register (ICCR) ...................................................................... 462 2 16.2.6 I C Bus Status Register (ICSR) ......................................................................... 469 16.2.7 Serial/Timer Control Register (STCR) .............................................................. 474 16.2.8 DDC Switch Register (DDCSWR).................................................................... 475 x 16.2.9 Module Stop Control Register (MSTPCR) ........................................................ 478 16.3 Operation ....................................................................................................................... 479 2 16.3.1 I C Bus Data Format ......................................................................................... 479 16.3.2 Master Transmit Operation ............................................................................... 481 16.3.3 Master Receive Operation................................................................................. 483 16.3.4 Slave Receive Operation................................................................................... 485 16.3.5 Slave Transmit Operation ................................................................................. 487 16.3.6 IRIC Setting Timing and SCL Control .............................................................. 489 2 16.3.7 Automatic Switching from Formatless Mode to I C Bus Format ....................... 490 16.3.8 Operation Using the DTC ................................................................................. 491 16.3.9 Noise Canceler.................................................................................................. 492 16.3.10 Sample Flowcharts.......................................................................................... 493 16.3.11 Initialization of Internal State.......................................................................... 497 16.4 Usage Notes ................................................................................................................... 498 Section 17 Host Interface ...............................................................................505 17.1 Overview ....................................................................................................................... 505 17.1.1 Features ............................................................................................................ 505 17.1.2 Block Diagram.................................................................................................. 506 17.1.3 Input and Output Pins ....................................................................................... 507 17.1.4 Register Configuration...................................................................................... 508 17.2 Register Descriptions ..................................................................................................... 509 17.2.1 System Control Register (SYSCR).................................................................... 509 17.2.2 System Control Register 2 (SYSCR2) ............................................................... 510 17.2.3 Host Interface Control Register (HICR) ............................................................ 511 17.2.4 Input Data Register 1 (IDR1) ............................................................................ 512 17.2.5 Output Data Register 1 (ODR1) ........................................................................ 512 17.2.6 Status Register 1 (STR1)................................................................................... 513 17.2.7 Input Data Register 2 (IDR2) ............................................................................ 514 17.2.8 Output Data Register 2 (ODR2) ........................................................................ 515 17.2.9 Status Register 2 (STR2)................................................................................... 515 17.2.10 Module Stop Control Register (MSTPCR) ...................................................... 517 17.3 Operation ....................................................................................................................... 518 17.3.1 Host Interface Operation ................................................................................... 518 17.3.2 Control States ................................................................................................... 519 17.3.3 A20 Gate .......................................................................................................... 520 17.3.4 Host Interface Pin Shutdown Function .............................................................. 523 17.4 Interrupts........................................................................................................................ 524 17.4.1 IBF1, IBF2........................................................................................................ 524 17.4.2 HIRQ11, HIRQ1, and HIRQ12 ......................................................................... 524 17.5 Usage Note .................................................................................................................... 525 xi Section 18 D/A Converter .............................................................................. 527 18.1 Overview ....................................................................................................................... 527 18.1.1 Features ............................................................................................................ 527 18.1.2 Block Diagram.................................................................................................. 528 18.1.3 Input and Output Pins ....................................................................................... 529 18.1.4 Register Configuration...................................................................................... 529 18.2 Register Descriptions ..................................................................................................... 530 18.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1)................................................ 530 18.2.2 D/A Control Register (DACR) .......................................................................... 530 18.2.3 Module Stop Control Register (MSTPCR) ........................................................ 532 18.3 Operation ....................................................................................................................... 533 Section 19 A/D Converter .............................................................................. 535 19.1 Overview ....................................................................................................................... 535 19.1.1 Features ............................................................................................................ 535 19.1.2 Block Diagram.................................................................................................. 536 19.1.3 Pin Configuration.............................................................................................. 537 19.1.4 Register Configuration...................................................................................... 538 19.2 Register Descriptions ..................................................................................................... 539 19.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................ 539 19.2.2 A/D Control/Status Register (ADCSR) ............................................................. 540 19.2.3 A/D Control Register (ADCR) .......................................................................... 543 19.2.4 Keyboard Comparator Control Register (KBCOMP)......................................... 544 19.2.5 Module Stop Control Register (MSTPCR) ........................................................ 545 19.3 Interface to Bus Master .................................................................................................. 546 19.4 Operation ....................................................................................................................... 547 19.4.1 Single Mode (SCAN = 0).................................................................................. 547 19.4.2 Scan Mode (SCAN = 1) .................................................................................... 549 19.4.3 Input Sampling and A/D Conversion Time ....................................................... 551 19.4.4 External Trigger Input Timing .......................................................................... 552 19.5 Interrupts ....................................................................................................................... 553 19.6 Usage Notes................................................................................................................... 553 Section 20 RAM ............................................................................................ 559 20.1 Overview ....................................................................................................................... 559 20.1.1 Block Diagram.................................................................................................. 559 20.1.2 Register Configuration...................................................................................... 560 20.2 System Control Register (SYSCR) ................................................................................. 560 20.3 Operation ....................................................................................................................... 561 20.3.1 Expanded Mode (Modes 1, 2, and 3 (EXPE = 1)).............................................. 561 20.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0)) ............................................... 561 xii Section 21 ROM.............................................................................................563 21.1 Overview ....................................................................................................................... 563 21.1.1 Block Diagram.................................................................................................. 563 21.1.2 Register Configuration...................................................................................... 564 21.2 Register Descriptions ..................................................................................................... 564 21.2.1 Mode Control Register (MDCR) ....................................................................... 564 21.3 Operation ....................................................................................................................... 565 21.4 Overview of Flash Memory............................................................................................ 566 21.4.1 Features ............................................................................................................ 566 21.4.2 Block Diagram.................................................................................................. 567 21.4.3 Flash Memory Operating Modes ....................................................................... 568 21.4.4 Pin Configuration.............................................................................................. 572 21.4.5 Register Configuration...................................................................................... 572 21.5 Register Descriptions ..................................................................................................... 573 21.5.1 Flash Memory Control Register 1 (FLMCR1) ................................................... 573 21.5.2 Flash Memory Control Register 2 (FLMCR2) ................................................... 575 21.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)................................................... 577 21.5.4 Serial/Timer Control Register (STCR) .............................................................. 578 21.6 On-Board Programming Modes...................................................................................... 579 21.6.1 Boot Mode........................................................................................................ 580 21.6.2 User Program Mode .......................................................................................... 585 21.7 Programming/Erasing Flash Memory ............................................................................. 586 21.7.1 Program Mode .................................................................................................. 586 21.7.2 Program-Verify Mode....................................................................................... 587 21.7.3 Erase Mode....................................................................................................... 589 21.7.4 Erase-Verify Mode............................................................................................ 589 21.8 Flash Memory Protection ............................................................................................... 591 21.8.1 Hardware Protection ......................................................................................... 591 21.8.2 Software Protection........................................................................................... 592 21.8.3 Error Protection ................................................................................................ 592 21.9 Interrupt Handling when Programming/Erasing Flash Memory ...................................... 594 21.10 Flash Memory Writer Mode ......................................................................................... 595 21.10.1 Writer Mode Setting ....................................................................................... 595 21.10.2 Socket Adapters and Memory Map ................................................................. 596 21.10.3 Writer Mode Operation ................................................................................... 596 21.10.4 Memory Read Mode ....................................................................................... 598 21.10.5 Auto-Program Mode ....................................................................................... 601 21.10.6 Auto-Erase Mode ............................................................................................ 603 21.10.7 Status Read Mode ........................................................................................... 604 21.10.8 Status Polling.................................................................................................. 606 21.10.9 Writer Mode Transition Time ......................................................................... 606 21.10.10 Notes On Memory Programming................................................................... 607 21.11 Flash Memory Programming and Erasing Precautions.................................................. 607 xiii Section 22 Clock Pulse Generator .................................................................. 609 22.1 Overview ....................................................................................................................... 609 22.1.1 Block Diagram.................................................................................................. 609 22.1.2 Register Configuration...................................................................................... 610 22.2 Register Descriptions ..................................................................................................... 610 22.2.1 Standby Control Register (SBYCR) .................................................................. 610 22.2.2 Low-Power Control Register (LPWRCR) ......................................................... 611 22.3 Oscillator ....................................................................................................................... 612 22.3.1 Connecting a Crystal Resonator ........................................................................ 612 22.3.2 External Clock Input......................................................................................... 614 22.4 Duty Adjustment Circuit ................................................................................................ 617 22.5 Medium-Speed Clock Divider........................................................................................ 617 22.6 Bus Master Clock Selection Circuit................................................................................ 617 22.7 Subclock Input Circuit ................................................................................................... 618 22.8 Subclock Waveform Shaping Circuit ............................................................................. 618 Section 23 Power-Down State........................................................................ 619 23.1 Overview ....................................................................................................................... 619 23.1.1 Register Configuration...................................................................................... 623 23.2 Register Descriptions ..................................................................................................... 623 23.2.1 Standby Control Register (SBYCR) .................................................................. 623 23.2.2 Low-Power Control Register (LPWRCR) ......................................................... 625 23.2.3 Timer Control/Status Register (TCSR).............................................................. 627 23.2.4 Module Stop Control Register (MSTPCR) ........................................................ 628 23.3 Medium-Speed Mode..................................................................................................... 629 23.4 Sleep Mode.................................................................................................................... 630 23.4.1 Sleep Mode....................................................................................................... 630 23.4.2 Clearing Sleep Mode ........................................................................................ 630 23.5 Module Stop Mode......................................................................................................... 631 23.5.1 Module Stop Mode ........................................................................................... 631 23.5.2 Usage Note ....................................................................................................... 632 23.6 Software Standby Mode ................................................................................................. 632 23.6.1 Software Standby Mode.................................................................................... 632 23.6.2 Clearing Software Standby Mode...................................................................... 632 23.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode.......... 633 23.6.4 Software Standby Mode Application Example .................................................. 634 23.6.5 Usage Note ....................................................................................................... 635 23.7 Hardware Standby Mode................................................................................................ 635 23.7.1 Hardware Standby Mode................................................................................... 635 23.7.2 Hardware Standby Mode Timing ...................................................................... 636 23.8 Watch Mode .................................................................................................................. 637 23.8.1 Watch Mode ..................................................................................................... 637 23.8.2 Clearing Watch Mode ....................................................................................... 637 xiv 23.9 Subsleep Mode............................................................................................................... 638 23.9.1 Subsleep Mode.................................................................................................. 638 23.9.2 Clearing Subsleep Mode ................................................................................... 638 23.10 Subactive Mode ........................................................................................................... 639 23.10.1 Subactive Mode .............................................................................................. 639 23.10.2 Clearing Subactive Mode ................................................................................ 639 23.11 Direct Transition .......................................................................................................... 640 23.11.1 Overview of Direct Transition......................................................................... 640 Section 24 Electrical Characteristics...............................................................641 24.1 Absolute Maximum Ratings........................................................................................... 641 24.2 DC Characteristics ......................................................................................................... 642 24.3 AC Characteristics ......................................................................................................... 653 24.3.1 Clock Timing.................................................................................................... 654 24.3.2 Control Signal Timing ...................................................................................... 656 24.3.3 Bus Timing ....................................................................................................... 658 24.3.4 Timing of On-Chip Supporting Modules ........................................................... 665 24.4 A/D Conversion Characteristics ..................................................................................... 675 24.5 D/A Conversion Characteristics ..................................................................................... 677 24.6 Flash Memory Characteristics ........................................................................................ 678 24.7 Usage Note .................................................................................................................... 680 Appendix A Instruction Set ............................................................................681 A.1 Instruction....................................................................................................................... 681 A.2 Instruction Codes ............................................................................................................ 699 A.3 Operation Code Map ....................................................................................................... 713 A.4 Number of States Required for Execution ....................................................................... 717 A.5 Bus States During Instruction Execution ......................................................................... 730 Appendix B Internal I/O Registers..................................................................747 B.1 Addresses ........................................................................................................................ 747 B.2 Register Selection Conditions.......................................................................................... 753 B.3 Functions......................................................................................................................... 759 Appendix C I/O Port Block Diagrams...........................................................835 C.1 Port 1 Block Diagram...................................................................................................... 835 C.2 Port 2 Block Diagrams .................................................................................................... 836 C.3 Port 3 Block Diagram...................................................................................................... 839 C.4 Port 4 Block Diagrams .................................................................................................... 840 C.5 Port 5 Block Diagrams .................................................................................................... 847 C.6 Port 6 Block Diagrams .................................................................................................... 850 C.7 Port 7 Block Diagrams .................................................................................................... 855 xv C.8 Port 8 Block Diagrams .................................................................................................... 856 C.9 Port 9 Block Diagrams .................................................................................................... 862 Appendix D Pin States ................................................................................... 868 D.1 Port States in Each Processing State................................................................................ 868 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode ...............................................................................................................870 E.1 Timing of Transition to Hardware Standby Mode............................................................ 870 E.2 Timing of Recovery from Hardware Standby Mode......................................................... 870 Appendix F Product Code Lineup .................................................................. 872 Appendix G Package Dimensions .................................................................. 874 xvi Preface The H8S/2138 Series and H8S/2134 Series comprise high-performance microcomputers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen internal 16-bit general registers with a 32-bit configuration, and a concise and optimized instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. Single-power-supply flash memory (F-ZTATTM*) and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. On-chip peripheral functions include a 16-bit free-running timer (FRT), 8-bit timer (TMR), watchdog timer (WDT), two PWM timers (PWM and PWMX), a serial communication interface (SCI, IrDA), host interface (HIF), D/A converter (DAC), A/D converter (ADC), and I/O ports. 2 An I C bus interface (IIC) can also be incorporated as an option. An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer without CPU intervention. The H8S/2138 Series has all the above on-chip supporting functions, and can also be provided with an IIC module as an option. The H8S/2134 Series comprises reduced-function versions, with fewer TMR channels, and no PWM, HIF, IIC, or DTC modules. Use of the H8S/2138 or H8S/2134 Series enables compact, high-performance systems to be implemented easily. The comprehensive PC-related interface functions and 16 x 8 matrix keyscan functions are ideal for applications such as notebook PC keyboard control and intelligent battery and power supply control, while the various timer functions and their interconnectability 2 (timer connection), plus the interlinked operation of the I C bus interface and data transfer controller (DTC), in particular, make these devices ideal for use in PC monitors. In addition, the combination of F-ZTATTM* and reduced-function versions is ideal for applications such as system units in which on-chip program memory is essential to meet performance requirements, product start-up times are short, and program modifications may be necessary after end-product assembly. This manual describes the hardware of the H8S/2138 Series and H8S/2134 Series. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set. Note: * F-ZTATTM (Flexible-ZTAT) is a trademark of Hitachi, Ltd. 1 On-Chip Supporting Modules Series Product names Bus controller (BSC) Data transfer controller (DTC) 8-bit PWM timer (PWM) 14-bit PWM timer (PWMX) 16-bit free-running timer (FRT) 8-bit timer (TMR) Timer connection Watchdog timer (WDT) Serial communication interface (SCI) I C bus interface (IIC) Host interface (HIF) D/A converter A/D converter 2 H8S/2138 Series H8S/2138, 2137 Available (8 bits) Available x16 x2 x1 x4 Available x2 x3 x2 (option) Available x2 x8 (analog input) H8S/2134 Series H8S/2134, 2133, 2132, 2130 Available (8 bits) -- -- x2 x1 x3 -- x2 x3 -- -- x2 x8 (analog input) x8 x8 (expansion A/D inputs) (expansion A/D inputs) 2 Section 1 Overview 1.1 Overview The H8S/2138 Series and H8S/2134 Series comprise microcomputers (MCUs) built around the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with supporting modules on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip supporting modules required for system configuration include a data transfer controller (DTC) bus master, ROM and RAM memory, a16-bit free-running timer module (FRT), 8-bit timer module (TMR), watchdog timer module (WDT), two PWM timers (PWM and PWMX), serial communication interface (SCI), host interface (HIF), D/A converter (DAC), A/D converter 2 (ADC), and I/O ports. An I C bus interface (IIC) can also be incorporated as an option. The on-chip ROM is either flash memory (F-ZTATTM*) or mask ROM, with a capacity of 128, 96, 64, or 32 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Three operating modes, modes 1 to 3, are provided, and there is a choice of address space and single-chip mode or externally expanded modes. The features of the H8S/2138 Series and H8S/2134 Series are shown in Table 1.1. Note: * F-ZTATTM is a trademark of Hitachi, Ltd. 3 Table 1.1 Item CPU Overview Specifications * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for real-time control Maximum operating frequency: 20 MHz/5 V, 10 MHz/3 V High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 50 ns (20 MHz operation) 16 x 16-bit register-register multiply: 1000 ns (20 MHz operation) 32 / 16-bit register-register divide: 1000 ns (20 MHz operation) Instruction set suitable for high-speed operation Sixty-five basic instructions 8/16/32-bit transfer/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Powerful bit-manipulation instructions Two CPU operating modes Normal mode: 64-kbyte address space Advanced mode: 16-Mbyte address space Three MCU operating modes External Data Bus CPU Operating Mode Mode Description 1 Normal Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM enabled Single-chip mode 3 Normal Expanded mode with on-chip ROM enabled Single-chip mode * * Enabled On-Chip Initial ROM Value Disabled 8 bits Maximum Value 8 bits * * * Operating modes * 2 Advanced Enabled 8 bits 8 bits None 8 bits 8 bits None Bus controller 2-state or 3-state access space can be designated for external expansion areas Number of program wait states can be set for external expansion areas 4 Table 1.1 Item Overview (cont) Specifications * * * * Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC One 16-bit free-running counter (also usable for external event counting) Two output compare outputs Four input capture inputs (with buffer operation capability) One 8-bit up-counter (also usable for external event counting) Two timer constant registers The two channels can be connected Measurement of input signal or frequency-divided waveform pulse width and cycle (FRT, TMR1) Output of waveform obtained by modification of input signal edge (FRT, TMR1) Determination of input signal duty cycle (TMRX) Output of waveform synchronized with input signal (FRT, TMRX, TMRY) Automatic generation of cyclical waveform (FRT, TMRY) Watchdog timer or interval timer function selectable Subclock operation capability (channel 1 only) Up to 16 outputs Pulse duty cycle settable from 0 to 100% Resolution: 1/256 1.25 MHz maximum carrier frequency (20 MHz operation) Up to 2 outputs Resolution: 1/16384 312.5 kHz maximum carrier frequency (20 MHz operation) Asynchronous mode or synchronous mode selectable Multiprocessor communication function Data transfer controller (DTC) (H8S/2138 Series) 16-bit free-running timer module (FRT: 1 channel) 8-bit timer module (2 channels: TMR0, TMR1) * * * * * * * * * * * * * * * * * * * * Each channel has: Timer connection and 8-bit timer (TMR) module (2 channels: TMRX, TMRY) (Timer connection and TMRX provided in H8S/2138 Series) Input/output and FRT, TMR1, TMRX, TMRY can be interconnected Watchdog timer module (WDT: 2 channels) 8-bit PWM timer (PWM) (H8S/2138 Series) 14-bit PWM timer (PWMX) Serial communication * interface * (SCI: 2 channels, SCI0 and SCI1) 5 Table 1.1 Item Overview (cont) Specifications * * * * * * * * * * * Asynchronous mode or synchronous mode selectable Multiprocessor communication function Compatible with IrDA specification version 1.0 TxD and RxD encoding/decoding in IrDA format 8-bit high-impedance (ISA) port Three host interrupt requests (HIRQ11, HIRQ1, HIRQ12) Normal and fast A20 gate output Two register sets (each comprising two data registers and two status registers) Matrix keyboard control using keyboard scan with wakeup interrupt and sense port configuration Resolution: 10 bits Input: 8 channels (dedicated analog pins) 8 channels (same pins as keyboard sense port) High-speed conversion: 6.7 s minimum conversion time (20 MHz operation) Single or scan mode selectable Sample-and-hold function A/D conversion can be activated by external trigger or timer trigger Resolution: 8 bits Output: 2 channels 58 input/output pins (including 24 with LED drive capability) 8 input-only pins Flash memory or mask ROM High-speed static RAM ROM 128 kbytes 96 kbytes 64 kbytes 32 kbytes RAM 4 kbytes 4 kbytes 2 kbytes 2 kbytes SCI with IrDA: 1 channel (SCI2) Host interface (HIF) (H8S/2138 Series) Keyboard controller A/D converter * * * * * * * * * * D/A converter I/O ports Memory Product Name H8S/2134, H8S/2138 H8S/2133 H8S/2132, H8S/2137 H8S/2130 6 Table 1.1 Item Overview (cont) Specifications * * * * * * * * * * * * * * * Nine external interrupt pins (NMI, ,54 to ,54) 39 internal interrupt sources Three priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Subclock operation Built-in duty correction circuit 80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C) 2 Conforms to Philips I C bus interface standard Single master mode/slave mode Arbitration lost condition can be identified Supports two slave addresses Product Code Series H8S/2138 Mask ROM Versions HD6432138 1 HD6432138W* Interrupt controller Power-down state Clock pulse generator * Packages I C bus interface (IIC: 2 channels) (option in H8S/2138 Series) Product lineup (preliminary) 2 F-ZTATTM Versions 2 HD64F2138* ROM/RAM (Bytes) 128 k/4 k Packages FP-80A, TFP-80C HD6432137 1 HD6432137W* -- 64 k/2 k H8S/2134 HD6432134 HD6432133 HD6432132 HD6432130 HD64F2134 -- HD64F2132R -- 2 128 k/4 k 96 k/4 k 64 k/2 k 32 k/2 k Notes: * "W" indicates the I C bus option. *2 FP-80A only 1 7 1.2 Internal Block Diagram An internal block diagram of the H8S/2138 Series is shown in figure 1.1, and an internal block diagram of the H8S/2134 Series in figure 1.2. VCC1 VCC2 VSS Clock pulse generator RES XTAL EXTAL MD1 MD0 NMI STBY VSS VSS Internal address bus Internal data bus H8S/2000 CPU Bus controller P97/WAIT/SDA0 P96/o/EXCL P95/AS/IOS/CS1 P94/WR/IOW P93/RD/IOR P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG/ECS2 P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P43/TMCI1/HIRQ11/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD Port 4 Port 6 Port 9 Port 2 Interrupt controller P27/A15/PW15/CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 DTC ROM WDT0, WDT1 P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 Port 1 RAM P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 P37/D7/HDB7 P36/D6/HDB6 P35/D5/HDB5 16-bit FRT 8-bit PWM 14-bit PWM Port 3 8-bit timer x 4ch (TMR0, TMR1, TMRX, TMRY) Timer connection Host interface P34/D4/HDB4 P33/D3/HDB3 P32/D2/HDB2 P31/D1/HDB1 P30/D0/HDB0 10-bit A/D SCI x 3ch (IrDA x 1ch) Port 5 8-bit D/A P52/SCK0/SCL0 P51/RxD0 P50/TxD0 IIC x 2ch (option) Port 8 Port 7 AVCC AVSS Figure 1.1 Internal Block Diagram of H8S/2138 Series 8 P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82/HIFSD P81/CS2/GA20 P80/HA0 P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 EXTAL MD1 MD0 NMI STBY Clock pulse generator RES XTAL VCC1 VCC2 VSS VSS VSS Internal address bus Internal data bus H8S/2000 CPU Bus controller P27/A15 P26/A14 P97/WAIT P96/o/EXCL Interrupt controller Port 2 P25/A13 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 P93/RD P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0 P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD Port 9 P95/AS/IOS P94/WR ROM WDT0, WDT1 RAM P17/A7 P16/A6 P15/A5 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 P37/D7 P36/D6 P35/D5 P34/D4 P33/D3 P32/D2 P31/D1 P30/D0 Port 6 16-bit FRT 14-bit PWM Port 4 8-bit timer x 3ch (TMR0, TMR1, TMRY) 10-bit A/D SCI x 3ch (IrDA x 1ch) 8-bit D/A P52/SCK0 P51/RxD0 P50/TxD0 Port 5 Port 8 Port 7 P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82 AVCC AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 Figure 1.2 Internal Block Diagram of H8S/2134 Series P81 P80 P72/AN2 P71/AN1 P70/AN0 Port 3 Port 1 9 1.3 1.3.1 Pin Arrangement and Functions Pin Arrangement The pin arrangement of the H8S/2138 Series is shown in figure 1.3, and the pin arrangement of the H8S/2134 Series in figure 1.4. P45/TMRI1/HIRQ12/CSYNCI P43/TMCI1/HIRQ11/HSYNCI P44/TMO1/HIRQ1/HSYNCO P27/A15/PW15/CBLANK PW3/A3/P13 PW2/A2/P12 PW1/A1/P11 PW0/A0/P10 HDB0/D0/P30 HDB1/D1/P31 HDB2/D2/P32 HDB3/D3/P33 HDB4/D4/P34 HDB5/D5/P35 HDB6/D6/P36 HDB7/D7/P37 VSS HA0/P80 GA20/CS2/P81 HIFSD/P82 P83 TxD1/IRQ3/P84 RxD1/IRQ4/P85 SCL1/SCK1/IRQ5/P86 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 P42/TMRI0/SCK2/SDA1 P22/A10/PW10 P23/A11/PW11 P24/A12/PW12 P25/A13/PW13 P26/A14/PW14 P14/A4/PW4 P15/A5/PW5 P16/A6/PW6 P17/A7/PW7 P20/A8/PW8 P21/A9/PW9 P47/PWX1 P46/PWX0 VCC1 VSS P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC P67/TMOX/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4/CLAMPO P63/FTIB/CIN3/KIN3/VFBACKI P62/FTIA/CIN2/KIN2/VSYNCI/TMIY P61/FTOA/CIN1/KIN1/VSYNCO P60/FTCI/CIN0/KIN0/HFBACKI/TMIX FP-80A TFP-80C (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 9 10 11 12 13 14 15 16 17 18 19 20 Figure 1.3 Pin Arrangement of H8S/2138 Series (FP-80A, TFP-80C: Top View) 10 ADTRG/IRQ2/ECS2/P90 SCL0/SCK0/P52 RxD0/P51 TxD0/P50 CS1/IOS/AS/P95 IOW/WR/P94 IOR/RD/P93 IRQ0/P92 SDA0/WAIT/P97 EXCL/ /P96 IRQ1/P91 EXTAL VCC2 RES MD1 MD0 NMI XTAL STBY VSS A3/P13 A2/P12 A1/P11 A0/P10 D0/P30 D1/P31 D2/P32 D3/P33 D4/P34 D5/P35 D6/P36 D7/P37 VSS P80 P81 P82 P83 TxD1/IRQ3/P84 RxD1/IRQ4/P85 SCK1/IRQ5/P86 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 P42/TMRI0/SCK2 P45/TMRI1 P43/TMCI1 P47/PWX1 P46/PWX0 P44/TMO1 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9 VCC1 VSS P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0 FP-80A TFP-80C (Top view) 31 30 29 28 27 26 25 24 23 22 21 9 10 11 12 13 14 15 16 17 18 19 20 Figure 1.4 Pin Arrangement of H8S/2134 Series (FP-80A, TFP-80C: Top View) ADTRG/IRQ2/P90 EXCL/ /P96 IOS/AS/P95 WR/P94 RD/P93 IRQ0/P92 SCK0/P52 RxD0/P51 TxD0/P50 WAIT/P97 IRQ1/P91 EXTAL RES XTAL MD1 MD0 NMI STBY VCC2 VSS 11 1.3.2 Pin Functions in Each Operating Mode Tables 1.2 and 1.3 show the pin functions of the H8S/2138 Series and H8S/2134 Series in each of the operating modes. Table 1.2 H8S/2138 Series Pin Functions in Each Operating Mode Pin Name Pin No. FP-80A TFP-80C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Mode 1 Expanded Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Flash Memory Writer Mode 5(6 XTAL EXTAL MD1 MD0 NMI 5(6 XTAL EXTAL MD1 MD0 NMI 5(6 XTAL EXTAL MD1 MD0 NMI 5(6 XTAL EXTAL VSS VSS FA9 VCC VCC NC FA17 NC VSS VCC NC FA16 FA15 67%< VCC2 P51/RxD0 P50/TxD0 VSS o/P96/EXCL 67%< VCC2 P51/RxD0 P50/TxD0 VSS o/P96/EXCL 67%< VCC2 P52/SCK0/SCL0 P51/RxD0 P50/TxD0 VSS P97/SDA0 P96/o/EXCL P95/&6 P94/,2: P93/,25 P92/,54 P91/,54 P90/,54/$'75*/ P52/SCK0/SCL0 P52/SCK0/SCL0 P97/:$,7/SDA0 P97/:$,7/SDA0 $6/,26 :5 5' P92/,54 P91/,54 P90/,54/ P60/FTCI/CIN0/ $6/,26 :5 5' P92/,54 P91/,54 P90/,54/$'75* P60/FTCI/CIN0/ :( VSS VCC VCC NC $'75* (&6 .,1/TMIX/ HFBACKI .,1/TMIX/ HFBACKI P60/FTCI/CIN0/ .,1/TMIX/ HFBACKI 22 23 .,1/VSYNCO .,1/TMIY/ VSYNCI P61/FTOA/CIN1/ P61/FTOA/CIN1/ .,1/VSYNCO .,1/TMIY/ P61/FTOA/CIN1/ .,1/VSYNCO .,1/TMIY/ VSYNCI NC NC P62/FTIA/CIN2/ P62/FTIA/CIN2/ VSYNCI P62/FTIA/CIN2/ 12 Table 1.2 H8S/2138 Series Pin Functions in Each Operating Mode (cont) Pin Name Pin No. FP-80A TFP-80C 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Mode 1 Expanded Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) P63/FTIB/CIN3/ Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) P63/FTIB/CIN3/ Flash Memory Writer Mode NC NC NC NC VSS VCC NC NC NC NC NC NC NC NC VSS NC NC NC NC NC NC NC NC VCC .,1/VFBACKI .,1/CLAMPO .,1 P63/FTIB/CIN3/ .,1/VFBACKI .,1/CLAMPO .,1 .,1/VFBACKI .,1/CLAMPO .,1 P64/FTIC/CIN4/ P65/FTID/CIN5/ P64/FTIC/CIN4/ P65/FTID/CIN5/ P64/FTIC/CIN4/ P65/FTID/CIN5/ P66/FTOB/CIN6/ .,1/,54 .,1/,54 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P66/FTOB/CIN6/ P66/FTOB/CIN6/ .,1/,54 .,1/,54 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 .,1/,54 .,1/,54 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P67/TMOX/CIN/ P67/TMOX/CIN7/ P67/TMOX/CIN7/ P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2/SDA1 P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 VCC1 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2/SDA1 P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 VCC1 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2/SDA1 P43/TMCI1/HIRQ11/ HSYNCI P44/TMO1/HIRQ1/ HSYNCO P45/TMRI1/HIRQ12/ CSYNCI P46/PWX0 P47/PWX1 VCC1 13 Table 1.2 H8S/2138 Series Pin Functions in Each Operating Mode (cont) Pin Name Pin No. FP-80A TFP-80C 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Mode 1 A15 A14 A13 A12 A11 A10 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 VSS P80 P81 P82 P83 Expanded Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) A15/P27/PW15/ CBLANK A14/P26/PW14 A13/P25/PW13 A12/P24/PW12 A11/P23/PW11 A10/P22/PW10 A9/P21/PW9 A8/P20/PW8 VSS A7/P17/PW7 A6/P16/PW6 A5/P15/PW5 A4/P14/PW4 A3/P13/PW3 A2/P12/PW2 A1/P11/PW1 A0/P10/PW0 D0 D1 D2 D3 D4 D5 D6 D7 VSS P80 P81 P82 P83 Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) P27/PW15/CBLANK P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8 VSS P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 P30/HDB0 P31/HDB1 P32/HDB2 P33/HDB3 P34/HDB4 P35/HDB5 P36/HDB6 P37/HDB7 VSS P80/HA0 P81/CS2/GA20 P82/HIFSD P83 Flash Memory Writer Mode &( FA14 FA13 FA12 FA11 FA10 2( FA8 VSS FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 FO0 FO1 FO2 FO3 FO4 FO5 FO6 FO7 VSS NC NC NC NC 14 Table 1.2 H8S/2138 Series Pin Functions in Each Operating Mode (cont) Pin Name Pin No. FP-80A TFP-80C 78 79 80 Mode 1 Expanded Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) P84/,54/TxD1 P85/,54/RxD1 Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) P84/,54/TxD1 P85/,54/RxD1 P86/,54/SCK1/ SCL1 Flash Memory Writer Mode NC NC NC P84/,54/TxD1 P85/,54/RxD1 P86/,54/SCK1/ P86/,54/SCK1/ SCL1 SCL1 15 Table 1.3 H8S/2134 Series Pin Functions in Each Operating Mode Pin Name Pin No. FP-80A TFP-80C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Mode 1 Expanded Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) Flash Memory Writer Mode 5(6 XTAL EXTAL MD1 MD0 NMI 5(6 XTAL EXTAL MD1 MD0 NMI 5(6 XTAL EXTAL MD1 MD0 NMI 5(6 XTAL EXTAL VSS VSS FA9 VCC VCC NC FA17 NC VSS VCC NC FA16 FA15 67%< VCC2 P52/SCK0 P51/RxD0 P50/TxD0 VSS P97/:$,7 o/P96/EXCL 67%< VCC2 P52/SCK0 P51/RxD0 P50/TxD0 VSS P97/:$,7 o/P96/EXCL 67%< VCC2 P52/SCK0 P51/RxD0 P50/TxD0 VSS P97 o/P96/EXCL P95 P94 P93 P92/,54 P91/,54 P90/,54/$'75* P60/FTCI/CIN0/ $6/,26 :5 5' P92/,54 P91/,54 P90/,54/ P60/FTCI/CIN0/ $6/,26 :5 5' P92/,54 P91/,54 P90/,54/$'75* P60/FTCI/CIN0/ :( VSS VCC VCC NC NC NC NC NC NC $'75* .,1 .,1 .,1 .,1 .,1 P61/FTOA/ CIN1/.,1 P61/FTOA/CIN1/ P62/FTIA/CIN2/ P61/FTOA/CIN1/ P62/FTIA/CIN2/ .,1/TMIY .,1 .,1 .,1 P62/FTIA/CIN2/ P63/FTIB/CIN3/ .,1/TMIY .,1 .,1 .,1 .,1/TMIY .,1 .,1 .,1 P63/FTIB/CIN3/ P64/FTIC/CIN4/ P65/FTID/CIN5/ P63/FTIB/CIN3/ P64/FTIC/CIN4/ P65/FTID/CIN5/ P64/FTIC/CIN4/ P65/FTID/CIN5/ 16 Table 1.3 H8S/2134 Series Pin Functions in Each Operating Mode (cont) Pin Name Pin No. FP-80A TFP-80C 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Mode 1 Expanded Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) P66/FTOB/CIN6/ Flash Memory Writer Mode NC VSS VCC NC NC NC NC NC NC NC NC VSS NC NC NC NC NC NC NC NC VCC .,1/,54 ,54 P66/FTOB/CIN6/ P66/FTOB/CIN6/ .,1/,54 ,54 .,1/,54 ,54 P67/CIN7/.,1/ P67/CIN7/.,1/ AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VCC1 A15/P27 A14/P26 A13/P25 A12/P24 A11/P23 A10/P22 P67/CIN7/.,1/ AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VCC1 P27 P26 P25 P24 P23 P22 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/ TxD2/IrTxD P41/TMO0/ RxD2/IrRxD P42/TMRI0/ SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VCC1 A15 A14 A13 A12 A11 A10 &( FA14 FA13 FA12 FA11 FA10 17 Table 1.3 H8S/2134 Series Pin Functions in Each Operating Mode (cont) Pin Name Pin No. FP-80A TFP-80C 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Mode 1 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 VSS P80 P81 P82 P83 Expanded Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) A9/P21 A8/P20 VSS A7/P17 A6/P16 A5/P15 A4/P14 A3/P13 A2/P12 A1/P11 A0/P10 D0 D1 D2 D3 D4 D5 D6 D7 VSS P80 P81 P82 P83 P84/,54/TxD1 P85/,54/RxD1 P86/,54/SCK1 Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) P21 P20 VSS P17 P16 P15 P14 P13 P12 P11 P10 P30 P31 P32 P33 P34 P35 P36 P37 VSS P80 P81 P82 P83 P84/,54/TxD1 P85/,54/RxD1 P86/,54/SCK1 Flash Memory Writer Mode 2( FA8 VSS FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 FO0 FO1 FO2 FO3 FO4 FO5 FO6 FO7 VSS NC NC NC NC NC NC NC P84/,54/TxD1 P85/,54/RxD1 P86/,54/SCK1 18 1.3.3 Pin Functions Table 1.4 summarizes the functions of the H8S/2138 Series and H8S/2134 Series pins. Table 1.4 Pin Functions Pin No. Type Power supply Symbol VCC1, VCC2 VSS FP-80A TFP-80C 8, 47 I/O Input Name and Function Power supply: For connection to the power supply. All VCC1 and VCC2 pins should be connected to the system power supply. Ground: For connection to the power supply (0 V). All VSS pins should be connected to the system power supply (0 V). Connected to a crystal oscillator. See section 22, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Connected to a crystal oscillator. The EXTAL pin can also input an external clock. See section 22, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. 12, 56, 73 Input Clock XTAL 2 Input EXTAL 3 Input o EXCL 14 14 Output System clock: Supplies the system clock to external devices. Input External subclock input: Input a 32.768 kHz external subclock. 19 Table 1.4 Pin Functions (cont) Pin No. Type Operating mode control Symbol MD1 MD0 FP-80A TFP-80C 4 5 I/O Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD1 and MD0 and the operating mode is shown below. These pins should not be changed while the MCU is operating. Operating MD1 MD0 Mode Description 0 1 Mode 1 Normal Expanded mode with on-chip ROM disabled Advanced Expanded mode with on-chip ROM enabled or single-chip mode Normal Expanded mode with on-chip ROM enabled or single-chip mode 1 0 Mode 2 1 1 Mode 3 System control 5(6 67%< 1 7 48 to 55, 57 to 64 72 to 65 13 Input Input Reset input: When this pin is driven low, the chip is reset. Standby: When this pin is driven low, a transition is made to hardware standby mode. Address bus Data bus Bus control A15 to A0 D7 to D0 Output Address bus: These pins output an address. Input/ output Input Data bus (upper): Bidirectional data bus. Used for 8-bit data. Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. :$,7 5' :5 $6/,26 17 16 15 Output Read: When this pin is low, it indicates that the external address space is being read. Output Write: When this pin is low, it indicates that the external address space is being written to. Output Address strobe: When this pin is low, it indicates that address output on the address bus is valid. 20 Table 1.4 Pin Functions (cont) Pin No. Type Interrupt signals Symbol NMI FP-80A TFP-80C 6 18 to 20, 78 to 80, 27, 28 21 22 27 23 24 25 26 40 43 28 39 42 41 44 21 23 48 to 55, 57 to 64 45 46 I/O Input Input Name and Function Nonmaskable interrupt: Requests a nonmaskable interrupt. Interrupt request 0 to 7: These pins request a maskable interrupt. FRT counter clock input: Input pin for an external clock signal for the free-running counter (FRC). ,54 to ,54 16-bit free- FTCI running timer (FRT) FTOA FTOB FTIA FTIB FTIC FTID 8-bit timer (TMR0, TMR1, TMRX, TMRY) TMO0 TMO1 TMOX TMCI0 TMCI1 TMRI0 TMRI1 TMIX TMIY PWM timer (PWM) PW15 to PW0 Input Output FRT output compare A output: The output compare A output pin. Output FRT output compare B output: The output compare B output pin. Input Input Input Input FRT input capture A input: The input capture A input pin. FRT input capture B input: The input capture B input pin. FRT input capture C input: The input capture C input pin. FRT input capture D input: The input capture D input pin. Output Compare-match output: TMR0, TMR1, and TMRX compare-match output pins. Input Counter external clock input: Input pins for the external clock input to the TMR0 and TMR1 counters. Counter external reset input: TMR0 and TMR1 counter reset input pins. Counter external clock input and reset input: Dual function as TMRX and TMRY counter clock input pin and reset input pin. Input Input Output PWM timer output: PWM timer pulse output pins. Output PWMX timer output: PWM D/A pulse output pins. 14-bit PWM PWX0 timer PWX1 (PWMX) 21 Table 1.4 Pin Functions (cont) Pin No. Type Serial communication interface (SCI0, SCI1, SCI2) Symbol TxD0 TxD1 TxD2 RxD0 RxD1 RxD2 SCK0 SCK1 SCK2 FP-80A TFP-80C 11 78 39 10 79 40 9 80 41 39 40 72 to 65 15, 75, 20 I/O Name and Function Output Transmit data: Data output pins. Input Receive data: Data input pins. Input/ output Serial clock: Clock input/output pins. The SCK0 output type is NMOS push-pull. (H8S/2138 Series only) SCI with IrTxD IrDA (SCI2) IrRxD Host interface (HIF) HDB7 to HDB0 Output IrDA transmit data/receive data: Input and output Input pins for data encoded for IrDA use. Input/ output Input Host interface data bus: Bidirectional 8-bit bus for accessing the host interface. Chip select 1 and 2: Input pins for selecting host interface channel 1 or 2. I/O read: Input pin that enables reading from the host interface. I/O write: Input pin that enables writing to the host interface. Command/data: Input pin that indicates whether an access is a data access or command access. &6, &6, (&6 ,25 ,2: HA0 GA20 HIRQ11 HIRQ1 HIRQ12 HIFSD 17 16 74 75 42 43 44 76 Input Input Input Output GATE A20: A20 gate control signal output pin. Output Host interrupt 11, 1, and 12: Output pins for interrupt requests to the host. Input Host interface shutdown: Control input pin used to place host interface input/output pins in the highimpedance/cutoff state. Keyboard input: Matrix keyboard input pins. Normally, P10 to P17 and P20 to P27 are used as key-scan outputs. This enables a maximum 16output x 16-input, 256-key matrix to be configured. Keyboard control .,1 to .,1 21 to 24, 25 to 28 Input 22 Table 1.4 Pin Functions (cont) Pin No. Type A/D converter (ADC) Symbol AN7 to AN0 CN0 to CN7 FP-80A TFP-80C 37 to 30 I/O Input Name and Function Analog input: A/D converter analog input pins. 21 to 24, 25 to 28 Input Expansion A/D inputs: Expansion A/D input pins can be connected to the A/D converter, but since they are also used as digital input/output pins, precision will fall. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. $'75* D/A converter (DAC) A/D converter D/A converter DA0 DA1 AVCC 20 36 37 29 Input Output Analog output: D/A converter analog output pins. Input Analog reference voltage: The analog power supply pin for the A/D converter and D/A converter. When the A/D and D/A converters are not used, this pin should be connected to the system power supply (+5 V or +3 V). AVSS 38 Input Analog ground: The ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). Timer connection input: Timer connection synchronous signal input pins. Timer connection VSYNCI, HSYNCI, CSYNCI, VFBACKI, HFBACKI VSYNCO, HSYNCO, CLAMPO, CBLANK 23 42 44 24 21 22 43 25 48 9 80 Input Output Timer connection output: Timer connection synchronous signal output pins. I C bus interface (IIC) (option) 2 SCL0 SCL1 Input/ output I2C clock input/output (channels 0 and 1): I C clock I/O pins. These pins have a bus drive function. The SCL0 output form is NMOS open-drain I2C data input/output (channels 0 and 1): I C data I/O pins. These pins have a bus drive function. The SDA0 output form is NMOS open-drain. 2 2 SDA0 SDA1 13 41 Input/ output 23 Table 1.4 Pin Functions (cont) Pin No. Type I/O ports Symbol P17 to P10 FP-80A TFP-80C 57 to 64 I/O Input/ output Name and Function Port 1: Eight input/output pins. The data direction of each pin can be selected in the port 1 data direction register (P1DDR). These pins have built-in MOS input pull-ups, and also have LED drive capability. Port 2: Eight input/output pins. The data direction of each pin can be selected in the port 2 data direction register (P2DDR). These pins have built-in MOS input pull-ups, and also have LED drive capability. Port 3: Eight input/output pins. The data direction of each pin can be selected in the port 3 data direction register (P3DDR). These pins have built-in MOS input pull-ups, and also have LED drive capability. Port 4: Eight input/output pins. The data direction of each pin can be selected in the port 4 data direction register (P4DDR). Port 5: Three input/output pins. The data direction of each pin can be selected in the port 5 data direction register (P5DDR). P52 is an NMOS pushpull output. (H8S/2138 Series only) Port 6: Eight input/output pins. The data direction of each pin can be selected in the port 6 data direction register (P6DDR). These pins have built-in MOS input pull-ups. Port 7: Eight input pins. Port 8: Seven input/output pins. The data direction of each pin can be selected in the port 8 data direction register (P8DDR). Port 9: Eight input/output pins. The data direction of each pin (except P96) can be selected in the port 9 data direction register (P9DDR). P97 is an NMOS push-pull output. (H8S/2138 Series only) P27 to P20 48 to 55 Input/ output P37 to P30 72 to 65 Input/ output P47 to P40 P52 to P50 46 to 39 Input/ output Input/ output 9 to 11 P67 to P60 28 to 21 Input/ output P77 to P70 P86 to P80 P97 to P90 37 to 30 80 to 74 Input Input/ output Input/ output 13 to 20 24 Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally) 25 * High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 20 MHz 8/16/32-bit register-register add/subtract: 50 ns 8 x 8-bit register-register multiply: 600 ns 16 / 8-bit register-register divide: 600 ns 16 x 16-bit register-register multiply: 1000 ns 32 / 16-bit register-register divide: 1000 ns * Two CPU operating modes Normal mode Advanced mode * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * Number of execution states The number of execution states of the MULXU and MULXS instructions differ as follows. Number of Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 There are also differences in the address space, EXR register functions, power-down state, etc., depending on the product. 26 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit extended registers, and one 8-bit control register, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 27 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16 Mbytes for the program area and a maximum of 4 Gbytes for the data area). The mode is selected by the mode pins of the microcontroller. Maximum 64 kbytes for program and data areas combined Normal mode CPU operating modes Advanced mode Maximum 16 Mbytes for program and data areas combined Figure 2.1 CPU Operating Modes (1) Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with predecrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. 28 Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. 29 Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch Note: * Ignored when returning. (b) Exception Handling Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. 30 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. 31 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP Reserved PC (24 bits) SP CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.5 Stack Structure in Advanced Mode 32 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2138 Series or H8S/2134 Series H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2.6 Memory Map 33 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers (CR) 23 PC 76543210 EXR* T -- -- -- -- I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Note: * Does not affect operation in the H8S/2138 Series and H8S/2134 Series. Figure 2.7 CPU Registers 34 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers E registers (extended registers) (E0 to E7) * 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2.8 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. 35 Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR): An 8-bit register. In the H8S/2138 Series and H8S/2134 Series, this register does not affect operation. Bit 7--Trace Bit (T): This bit is reserved. In the H8S/2138 Series and H8S/2134 Series, this bit does not affect operation. Bits 6 to 3--Reserved: These bits are reserved. They are always read as 1. Bits 2 to 0--Interrupt Mask Bits (I2 to I0): These bits are reserved. In the H8S/2138 Series and H8S/2134 Series, these bits do not affect operation. (3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 36 Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, refer to section 5, Interrupt Controller. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to store the carry The carry flag is also used as a bit accumulator by bit-manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 37 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers. Data Type General Register Data Format 1-bit data RnH 7 0 76543210 Don't care 1-bit data RnL Don't care 7 0 76543210 4-bit BCD data RnH 43 7 0 Upper digit Lower digit Don't care 4-bit BCD data RnL Don't care 43 7 0 Upper digit Lower digit Byte data RnH 7 MSB 0 Don't care LSB 7 Don't care Byte data RnL 0 LSB MSB Figure 2.10 General Register Data Formats 38 Data Type General Register Data Format Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (cont) 39 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address Data Format 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.11 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. 40 2.6 2.6.1 Instruction Set Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* 3 3 1 1 Size BWL WL L B BWL B BWL L BW WL B BWL Types 5 Arithmetic operations ADD, SUB, CMP, EG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS 19 Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT 4 8 14 5 9 1 SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* , JMP, BSR, JSR, RTS 2 B -- TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- -- Block data transfer EEPMOV Total: 65 types Notes: B: byte size; W: word size; L: longword size. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2138 Series or H8S/2134 Series. 41 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes @(d:16,ERn) @-ERn/@ERn+ @(d:32,ERn) @(d:8,PC) Function Instruction @(d:16,PC) @@aa:8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- @aa:16 @aa:24 @aa:32 @aa:8 @ERn #xx Rn Data transfer MOV POP, PUSH LDM, STM MOVFPE*, MOVTPE* BWL -- -- -- BWL WL B -- -- -- -- -- -- -- -- BWL -- -- -- BWL BWL B L BWL B BW BW BWL WL -- BWL BWL BWL B -- -- -- BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- BWL -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS Logic operations AND, OR, XOR BWL NOT -- -- -- -- -- -- Shift Bit manipulation Branch Bcc, BSR JMP, JSR RTS -- -- -- -- -- -- Note: * Cannot be used in the H8S/2138 Series or H8S/2134 Series. 42 -- -- Table 2.2 Combinations of Instructions and Addressing Modes (cont) Addressing Modes @(d:16,ERn) @-ERn/@ERn+ @(d:32,ERn) @(d:8,PC) Function Instruction @(d:16,PC) @@aa:8 -- -- -- -- -- -- -- -- @aa:16 @aa:24 @aa:32 @aa:8 @ERn #xx Rn System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP -- -- -- B -- B -- -- -- -- -- B B -- -- -- -- -- -- W W -- -- -- -- -- -- W W -- -- -- -- -- -- W W -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Block data transfer BW Legend: B: Byte W: Word L: Longword -- -- -- -- 43 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 44 Table 2.3 Type Data transfer Instructions Classified by Function Instruction MOV Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2138 Series or H8S/2134 Series. Cannot be used in the H8S/2138 Series or H8S/2134 Series. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. LDM STM L L @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. MOVFPE MOVTPE POP B B W/L 45 Table 2.3 Type Arithmetic operations Instructions Classified by Function (cont) Instruction ADD SUB Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. ADDX SUBX B INC DEC B/W/L ADDS SUBS DAA DAS L B MULXU B/W MULXS B/W DIVXU B/W 46 Table 2.3 Type Arithmetic operations Instructions Classified by Function (cont) Instruction DIVXS Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS B 47 Table 2.3 Type Logic operations Instructions Classified by Function (cont) Instruction AND Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement (logical complement) of general register contents. Rd (shift) Rd Performs an arithmetic shift on general register contents. A 1-bit or 2-bit shift is possible. Rd (shift) Rd Performs a logical shift on general register contents. A 1-bit or 2-bit shift is possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. OR B/W/L XOR B/W/L NOT B/W/L Shift operations SHAL SHAR B/W/L SHLL SHLR ROTL ROTR ROTXL ROTXR B/W/L B/W/L B/W/L 48 Table 2.3 Type Bitmanipulation instructions Instructions Classified by Function (cont) Instruction BSET Size* B Function 1 ( BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B 49 Table 2.3 Type Bitmanipulation instructions Instructions Classified by Function (cont) Instruction BXOR Size* B Function C ( BIXOR B BLD B BILD B BST B BIST B 50 Table 2.3 Type Branch instructions Instructions Classified by Function (cont) Instruction Bcc Size* -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS -- -- -- -- Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1 Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine 51 Table 2.3 Type Instructions Classified by Function (cont) Instruction Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves contents of a general register or memory or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. System control TRAPA instructions RTE SLEEP LDC STC B/W ANDC B ORC B XORC B NOP -- 52 Table 2.3 Type Block data transfer instructions Instructions Classified by Function (cont) Instruction EEPMOV.B Size* -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Block transfer instruction. Transfers the number of data bytes specified by R4L or R4 from locations starting at the address indicated by ER5 to locations starting at the address indicated by ER6. After the transfer, the next instruction is executed. EEPMOV.W -- Note: * Size refers to the operand size. B: Byte W: Word L: Longword 53 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. Condition Field: Specifies the branching condition of Bcc instructions. Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2.12 Instruction Formats (Examples) 54 2.6.5 Notes on Use of Bit-Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit manipulation, then write back the byte of data. Caution is therefore required when using these instructions on a register containing write-only bits, or a port. The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4 No. 1 2 3 4 5 6 7 8 Addressing Modes Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 55 Register Direct--Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. Register Indirect--@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand in memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn: * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.5 indicates the accessible absolute address ranges. 56 Table 2.5 Absolute Address Access Ranges Normal Mode 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Absolute Address Data address Program instruction address 24 bits (@aa:24) Immediate--#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. Program-Counter Relative--@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 57 Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 58 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.6 No. 1 Effective Address Calculation Effective Address (EA) Operand is general register contents. Addressing Mode and Instruction Effective Address Calculation Format Register direct (Rn) op rm rn 2 Register indirect (@ERn) 31 General register contents op r 0 31 24 23 0 Don't care 3 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 31 General register contents 31 op r disp 31 Sign extension disp 0 24 23 0 Don't care 0 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 31 General register contents 0 31 24 23 0 Don't care op r 1, 2, or 4 * Register indirect with pre-decrement @-ERn 31 General register contents 31 op r Operand Size Byte Word Longword Value Added 1 2 4 1, 2, or 4 24 23 0 Don't care 0 59 Table 2.6 No. 5 Effective Address Calculation (cont) Effective Address Calculation Effective Address (EA) Addressing Mode and Instruction Format Absolute address @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care @aa:16 op abs 31 Don't care 24 23 16 15 Sign extension 0 @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8, PC)/@(d:16, PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care 60 Table 2.6 No. 8 Effective Address Calculation (cont) Effective Address Calculation Effective Address (EA) Addressing Mode and Instruction Format Memory indirect @@aa:8 * Normal mode op abs 31 H'000000 87 abs 0 31 24 23 16 15 0 Don't care 15 Memory contents 0 H'00 * Advanced mode op abs 31 H'000000 87 abs 0 31 Memory contents 0 31 24 23 0 Don't care 61 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode, sub-active mode, sub-sleep mode, and watch mode. Figure 2.14 Processing States 62 End of bus request Bus request Program execution state End of bus request Bus request Bus-released state End of exception handling SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 SLEEP instruction with LSON = 0, SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt RES = high Software standby mode Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For details, refer to section 23, Power-Down State. Figure 2.15 State Transitions 63 2.8.2 Reset State When the 5(6 input goes low all current processing stops and the CPU enters the reset state. All interrupts are disabled in the reset state. Reset exception handling starts when the 5(6 signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 14, Watchdog Timer. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. Types of Exception Handling and Their Priority: Exception handling is performed for resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7 Priority High Exception Handling Types and Priority Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the 5(6 pin, or when the watchdog timer overflows. When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence. Exception handling starts when a trap (TRAPA) instruction is 2 executed.* Interrupt End of instruction execution or end of exception-handling 1 sequence* When TRAPA instruction is executed Trap instruction Low Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 2. Trap instruction exception handling is always accepted in the program execution state. 64 Reset Exception Handling: After the 5(6 pin has gone low and the reset state has been entered, when 5(6 goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. Interrupt Exception Handling and Trap Instruction Exception Handling: When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.16 shows the stack after exception handling ends. Normal mode Advanced mode SP CCR CCR* PC (16 bits) SP CCR PC (24 bits) Note: * Ignored when returning. Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 65 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts except for internal operations. There is one other bus master in addition to the CPU: the data transfer controller (DTC). For further details, refer to section 6, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode, the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode are power-down modes that use subclock input. For details, refer to section 23, Power-Down State. Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the low-power control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1 and the LSON bit in LPWRCR and the PSS bit in the WDT1 timer control/status register (TCSR) are both cleared to 0. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Hardware Standby Mode: A transition to hardware standby mode is made when the 67%< pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. 66 2.9 2.9.1 Basic Timing Overview The CPU is driven by a system clock, denoted by the symbol o. The period from one rising edge of o to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows the pin states. Bus cycle T1 o Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2.17 On-Chip Memory Access Cycle 67 Bus cycle T1 o Address bus AS RD WR Data bus Unchanged High High High High impedance Figure 2.18 Pin States during On-Chip Memory Access 68 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Figure 2.20 shows the pin states. Bus cycle T1 T2 o Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2.19 On-Chip Supporting Module Access Cycle 69 Bus cycle T1 T2 o Address bus Unchanged AS RD WR High High High Data bus High impedance Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. 70 Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection The H8S/2138 Series and H8S/2134 Series have three operating modes (modes 1 to 3). These modes enable selection of the CPU operating mode and enabling/disabling of on-chip ROM, by setting the mode pins (MD1 and MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode 0 1 2 3 1 MCU Operating Mode Selection CPU Operating Mode -- Normal Advanced Normal On-Chip ROM -- MD1 0 MD0 0 1 0 1 Description -- Expanded mode with on-chip ROM disabled Disabled Expanded mode with on-chip ROM enabled Enabled Single-chip mode Expanded mode with on-chip ROM enabled Single-chip mode The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2138 Series and H8S/2134 Series actually access a maximum of 16 Mbytes. However, as there are 16 external address output pins, advanced mode is enabled only in single-chip mode or in expanded mode with on-chip ROM enabled when a specific area in the external address space is accessed using ,26. The external data bus width is 8 bits. Mode 1 is an externally expanded mode that allows access to external memory and peripheral devices. With modes 2 and 3, operation begins in single-chip mode after reset release, but a transition can be made to external expansion mode by setting the EXPE bit in MDCR. The H8S/2138 Series and H8S/2134 Series can only be used in modes 1 to 3. These means that the mode pins must select one of these modes. Do not changes the inputs at the mode pins during operation. 71 3.1.2 Register Configuration The H8S/2138 Series and H8S/2134 Series have a mode control register (MDCR) that indicates the inputs at the mode pins (MD1 and MD0), a system control register (SYSCR) and bus control register (BCR) that control the operation of the MCU, and a serial/timer control register (STCR) that controls the operation of the supporting modules. Table 3.2 summarizes these registers. Table 3.2 Name Mode control register System control register Bus control register Serial/timer control register MCU Registers Abbreviation MDCR SYSCR BCR STCR R/W R/W R/W R/W R/W Initial Value Undetermined H'09 H'D7 H'00 Address* H'FFC5 H'FFC4 H'FFC6 H'FFC3 Note: * Lower 16 bits of the address. 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) 7 EXPE --* R/W* 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 MDS1 --* R 0 MDS0 --* R Initial value Read/Write Note: * Determined by pins MD1 and MD0. MDCR is an 8-bit read-only register that indicates the operating mode setting and the current operating mode of the MCU. The EXPE bit is initialized in coordination with the mode pin states by a reset and in hardware standby mode. 72 Bit 7--Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, this bit is fixed at 1 and cannot be modified. In modes 2 and 3, this bit has an initial value of 0, and can be read and written. Bit 7 EXPE 0 1 Description Single chip mode is selected Expanded mode is selected Bits 6 to 2--Reserved: These bits cannot be modified and are always read as 0. Bits 1 and 0--Mode Select 1 and 0 (MDS1, MDS0): These bits indicate the input levels at pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to MD1 and MD0. MDS1 and MDS0 are read-only bits--they cannot be written to. The mode pin (MD1 and MD0) input levels are latched into these bits when MDCR is read. 3.2.2 Bit Initial value Read/Write System Control Register (SYSCR) 7 CS2E 0 R/W 6 IOSE 0 R/W 5 INTM1 0 R 4 INTM0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W SYSCR is an 8-bit readable/writable register that performs selection of system pin functions, reset source monitoring, interrupt control mode selection, NMI detected edge selection, supporting module pin location selection, supporting module register access control, and RAM address space control. Only bits 7, 6, 3, 1, and 0 are described here. For a detailed description of these bits, refer also to the description of the relevant modules (host interface, bus controller, watchdog timer, RAM, etc.). For information on bits 5, 4, and 2, see section 5.2.1, System Control Register (SYSCR). SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Chip Select 2 Enable (CS2E): Specifies the location of the host interface control pin (&6). For details, see section 17, Host Interface. 73 Bit 6--IOS Enable (IOSE): Controls the function of the $6/,26 pin in expanded mode. Bit 6 IOSE 0 1 Description The $6/,26 pin functions as the address strobe pin (Low output when accessing an external area) (Initial value) The $6/,26 pin functions as the I/O strobe pin (Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F) Bit 3--External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow. Bit 3 XRST 0 1 Description A reset is generated by watchdog timer overflow A reset is generated by an external reset (Initial value) Bit 1--Host Interface Enable (HIE): This bit controls CPU access to the host interface data registers and control registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2), the keyboard controller and MOS input pull-up control registers (KMIMR and KMPCR), the 8-bit timer (channel X and Y) data registers and control registers (TCRX/TCRY, TCSRX/TCSRY, TICRR/TCORAY, TICRF/TCORBY, TCNTX/TCNTY, TCORC/TISR, TCORAX, and TCORBX), and the timer connection control registers (TCONRI, TCONRO, TCONRS, and SEDGR). Bit 1 HIE 0 Description In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, (Initial value) CPU access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers, is permitted In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to host interface data registers and control registers, and keyboard controller and MOS input pull-up control registers, is permitted 1 74 Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 3.2.3 Bit Bus Control Register (BCR) 7 ICIS1 1 R/W 6 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 -- 1 R/W 1 IOS1 1 R/W 0 IOS0 1 R/W ICIS0 BRSTRM BRSTS1 BRSTS0 Initial value Read/Write BCR is an 8-bit readable/writable register that specifies the external memory space access mode, and the I/O area range when the $6 pin is designated for use as the I/O strobe. For details on bits 7 to 2, see section 6.2.1, Bus Control Register (BCR). BCR is initialized to H'D7 by a reset and in hardware standby mode. Bits 1 and 0--IOS Select 1 and 0 (IOS1, IOS0): These bits specify the addresses for which the $6/,26 pin output goes low when IOSE = 1. BCR Bit 1 IOS1 0 Bit 0 IOS0 0 1 1 0 1 Description The $6/,26 pin output goes low in accesses to addresses H'(FF)F000 to H'(FF)F03F The $6/,26 pin output goes low in accesses to addresses H'(FF)F000 to H'(FF)F0FF The $6/,26 pin output goes low in accesses to addresses H'(FF)F000 to H'(FF)F3FF The $6/,26 pin output goes low in accesses to addresses H'(FF)F000 to H'(FF)FE4F (Initial value) 75 3.2.4 Bit Serial Timer Control Register (STCR) 7 IICS 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W 3 FLSHE 0 R/W 2 -- 0 R/W 1 ICKS1 0 R/W 0 ICKS0 0 R/W Initial value Read/Write STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), an on-chip flash memory control (in F-ZTAT versions), and also selects the TCNT input clock. For details of functions other than register access control, see the descriptions of the relevant modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 5--I C Control (IICS, IICX1, IICX0): These bits control the operation of the I C bus 2 interface when the on-chip IIC option is included. For details, see section 16, I C Bus Interface. Bit 4--I C Master Enable (IICE): Controls CPU access to the I C bus interface data registers and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR), the PWMX data registers and control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL), and the SCI control registers (SMR, BRR, and SCMR). Bit 4 IICE 0 Description Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used for SCI1 control register access Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used for SCI2 control register access Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used for SCI0 control register access 1 Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used for IIC1 data register and control register access Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used for PWMX data register and control register access Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used for IIC0 data register and control register access (Initial value) 2 2 2 2 76 Bit 3--Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), the power-down mode control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and the supporting module control register (PCSR and SYSCR2). Bit 3 FLSHE 0 1 Description Addresses H'(FF)FF80 to H'(FF)FF87 are used for power-down mode control register and supporting module control register access Addresses H'(FF)FF80 to H'(FF)FF87 are used for flash memory control register access (F-ZTAT version only) (Initial value) Bit 2--Reserved: Do not write 1 to this bit. Bits 1 and 0--Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12, 8-Bit Timers. 3.3 3.3.1 Operating Mode Descriptions Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled. Ports 1 and 2 function as an address bus, port 3 function as a data bus, and part of port 9 carries bus control signals. 3.3.2 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use external addresses. However, as these series have a maximum of 16 address outputs, an external address can be specified correctly only when the I/O strobe function of the $6/,26 pin is used. When the EXPE bit in MDCR is set to 1, ports 1, and 2 function as input ports after a reset. They can be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port 3 function as a data bus, and part of port 9 carries bus control signals. 77 3.3.3 Mode 3 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use external addresses. When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They can be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port 3 function as a data bus, and part of port 9 carries bus control signals. In products with an on-chip ROM capacity of 64 kbytes or more, the amount of on-chip ROM that can be used is limited to 56 kbytes. 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1 to 3, and 9 vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3 Port Port 1 Port 2 Port 3 Port 9 P97 P96 P95 to P93 P92 to P90 Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: After reset Pin Functions in Each Mode Mode 1 A A D P*/C C */P C P Mode 2 P*/A P*/A P*/D P*/C P*/C P*/C P Mode 3 P*/A P*/A P*/D P*/C P*/C P*/C P 78 3.5 Memory Map in Each Operating Mode Figures 3.1 to 3.4 show memory maps for each of the operating modes. The address space is 64 kbytes in modes 1 and 3 (normal modes), and 16 Mbytes in mode 2 (advanced mode). The on-chip ROM capacity is 32 kbytes (H8S/2130), 64 kbytes (H8S/2132 and H8S/2137), 96 kbytes (H8S/2133), or 128 kbytes (H8S/2134 and H8S/2138), but for products with an on-chip ROM capacity of 64 kbytes or more, the amount of on-chip ROM that can be used is limited to 56 kbytes in mode 3 (normal mode). For details, see section 6, Bus Controller. 79 Mode 1 (normal expanded mode with on-chip ROM disabled) Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) Mode 3/EXPE = 0 (normal single-chip mode) H'0000 H'0000 H'0000 External address space On-chip ROM On-chip ROM H'DFFF External address space H'E080 On-chip RAM* H'EFFF External address space H'DFFF H'E080 On-chip RAM* H'EFFF External address space H'E080 On-chip RAM H'EFFF H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes) H'FF7F H'FF80 Internal I/O registers 1 H'FFFF H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O registers 1 H'FFFF H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O registers 1 H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.1 H8S/2138 and H8S/2134 Memory Map in Each Operating Mode 80 Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'01FFFF H'020000 H'FFE080 H'01FFFF External address space*2 H'FFE080 On-chip RAM*1 On-chip RAM H'FFEFFF External address space*2 H'FFEFFF H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)*1 H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 2. For these models, the maximum number of external address pins is 16. An external address can only be specified correctly for an area that uses the I/O strobe function. Figure 3.1 H8S/2138 and H8S/2134 Memory Map in Each Operating Mode (cont) 81 Mode 1 (normal expanded mode with on-chip ROM disabled) Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) Mode 3/EXPE = 0 (normal single-chip mode) H'0000 H'0000 H'0000 External address space On-chip ROM On-chip ROM H'DFFF External address space H'E080 On-chip RAM* H'EFFF External address space H'DFFF H'E080 On-chip RAM* H'EFFF External address space H'E080 On-chip RAM H'EFFF H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes) H'FF7F H'FF80 Internal I/O registers 1 H'FFFF H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O registers 1 H'FFFF H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O registers 1 H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.2 H8S/2133 Memory Map in Each Operating Mode 82 Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'017FFF H'017FFF Reserved area H'01FFFF H'020000 H'FFE080 On-chip RAM*1 H'FFEFFF External address space*2 Reserved area H'01FFFF External address space*2 H'FFE080 On-chip RAM H'FFEFFF H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O registers 2 On-chip RAM (128 bytes) H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)*1 H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF Internal I/O registers 1 Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 2. For these models, the maximum number of external address pins is 16. An external address can only be specified correctly for an area that uses the I/O strobe function. Figure 3.2 H8S/2133 Memory Map in Each Operating Mode (cont) 83 Mode 1 (normal expanded mode with on-chip ROM disabled) Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) Mode 3/EXPE = 0 (normal single-chip mode) H'0000 H'0000 H'0000 External address space On-chip ROM On-chip ROM H'DFFF External address space H'E080 Reserved area* H'E880 H'EFFF On-chip RAM* External address space H'DFFF H'E080 Reserved area* H'E880 H'EFFF On-chip RAM* External address space H'E080 Reserved area H'E880 H'EFFF On-chip RAM H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O registers 1 H'FFFF H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O registers 1 H'FFFF H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes) H'FF7F H'FF80 Internal I/O registers 1 H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.3 H8S/2137 and H8S/2132 Memory Map in Each Operating Mode 84 Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'00FFFF H'00FFFF Reserved area Reserved area H'01FFFF H'020000 H'FFE080 H'01FFFF External address space*2 H'FFE080 Reserved area*1 Reserved area H'FFE880 H'FFEFFF H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF On-chip RAM H'FFE880 H'FFEFFF On-chip RAM*1 External address space*2 H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)*1 H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 2. For these models, the maximum number of external address pins is 16. An external address can only be specified correctly for an area that uses the I/O strobe function. Figure 3.3 H8S/2137 and H8S/2132 Memory Map in Each Operating Mode (cont) 85 Mode 1 (normal expanded mode with on-chip ROM disabled) Mode 3/EXPE = 1 (normal expanded mode with on-chip ROM enabled) Mode 3/EXPE = 0 (normal single-chip mode) H'0000 H'0000 H'0000 On-chip ROM On-chip ROM External address space H'7FFF H'7FFF Reserved area Reserved area H'DFFF External address space H'E080 Reserved area* H'E880 H'EFFF On-chip RAM* External address space H'DFFF H'E080 Reserved area* H'E880 H'EFFF On-chip RAM* External address space H'E080 Reserved area H'E880 H'EFFF On-chip RAM H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O registers 1 H'FFFF H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes)* H'FF7F H'FF80 Internal I/O registers 1 H'FFFF H'FE50 H'FEFF Internal I/O registers 2 On-chip RAM H'FF00 (128 bytes) H'FF7F H'FF80 Internal I/O registers 1 H'FFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.4 H8S/2130 Memory Map in Each Operating Mode 86 Mode 2/EXPE = 1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 2/EXPE = 0 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'007FFF H'007FFF Reserved area Reserved area H'01FFFF H'020000 H'FFE080 H'01FFFF External address space*2 H'FFE080 Reserved area*1 Reserved area H'FFE880 H'FFEFFF H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF On-chip RAM H'FFE880 H'FFEFFF On-chip RAM*1 External address space*2 H'FFFE50 H'FFFEFF Internal I/O registers 2 On-chip RAM H'FFFF00 (128 bytes)*1 H'FFFF7F H'FFFF80 Internal I/O registers 1 H'FFFFFF Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 2. For these models, the maximum number of external address pins is 16. An external address can only be specified correctly for an area that uses the I/O strobe function. Figure 3.4 H8S/2130 Memory Map in Each Operating Mode (cont) 87 88 Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, direct transition, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Trace* 1 Start of Exception Handling Starts immediately after a low-to-high transition at the 5(6 pin, or when the watchdog timer overflows. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been 2 issued.* Started by a direct transition resulting from execution of a SLEEP instruction. 3 Interrupt Direct transition Low Trap instruction (TRAPA)* Started by execution of a trap instruction (TRAPA). Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. (They cannot be used in the H8S/2138 Series or H8S/2134 Series.) Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in the program execution state. 89 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Sources and Vector Table The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Reset Trace Exception sources (Cannot be used in the H8S/2138 Series or H8S/2134 Series) External interrupts: NMI, IRQ7 to IRQ0 Interrupts Internal interrupts: interrupt sources in on-chip supporting modules Direct transition Trap instruction Figure 4.1 Exception Sources 90 Table 4.2 Exception Vector Table Vector Address*1 Exception Source Reset Reserved for system use Vector Number 0 1 2 3 4 5 Normal Mode H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0006 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'00CE to H'00CF Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'019C to H'019F Direct transition External interrupt NMI 6 7 8 9 10 11 Trap instruction (4 sources) Reserved for system use 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 2 16 17 18 19 20 21 22 23 24 103 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. For details on internal interrupt vectors, see section 5.3.3, Interrupt Exception Vector Table. 91 4.2 4.2.1 Reset Overview A reset has the highest exception priority. When the 5(6 pin goes low, all processing halts and the MCU enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the 5(6 pin changes from low to high. H8S/2138 Series and H8S/2134 Series MCUs can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog Timer. 4.2.2 Reset Sequence The MCU enters the reset state when the 5(6 pin goes low. To ensure that the chip is reset, hold the 5(6 pin low for at least 20 ms when powering on. To reset the chip during operation, hold the 5(6 pin low for at least 20 states. For pin states in a reset, see Appendix D.1, Pin States at Reset. When the 5(6 pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: [1] The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. [2] The reset exception vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.2 and 4.3 show examples of the reset sequence. 92 Fetch of Vector Internal first program fetch processing instruction o RES Internal address bus Internal read signal Internal write signal Internal data bus (2) High (4) (1) (3) (1) Reset exception vector address ((1) = H'0000) (2) Start address (contents of reset exception vector address) (3) Start address ((3) = (2)) (4) First program instruction Figure 4.2 Reset Sequence (Mode 3) 93 Vector fetch Internal processing * Fetch of first program instruction * * o RES Address bus RD WR D7 to D0 (2) (1) (3) (5) High (4) (6) (1) (3) Reset exception vector address ((1) = H'0000, (3) = H'0001) (2) (4) Start address (contents of reset exception vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Note: * 3 program wait states are inserted. Figure 4.3 Reset Sequence (Mode 1) 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). 94 4.3 Interrupts Interrupt exception handling can be requested by nine external sources (NMI and IRQ7 to IRQ0) from 17 input pins (NMI, ,54 to ,54, and .,1 to .,1), and internal sources in the on-chip supporting modules. Figure 4.4 shows the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit free-running timer (FRT), 8-bit timer (TMR), serial communication interface (SCI), data 2 transfer controller (DTC), A/D converter (ADC), host interface (HIF), and I C bus interface (option). Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to either three priority/mask levels to enable multiplexed interrupt control. For details on interrupts, see section 5, Interrupt Controller. External interrupts Interrupts NMI (1) IRQ7 to IRQ0 (8) WDT* (2) FRT (7) TMR (10) SCI (12) DTC (1) ADC (1) HIF (2) IIC (3) (option) Other (1) Internal interrupts Note: Numbers in parentheses are the numbers of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. Figure 4.4 Interrupt Sources and Number of Interrupts 95 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.3 Status of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 1 I 1 1 UI -- 1 I2 to I0 -- -- EXR T -- -- Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. 96 4.5 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR* PC (16 bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 4.5 (1) Stack Status after Exception Handling (Normal Mode) SP CCR PC (24bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 4.5 (2) Stack Status after Exception Handling (Advanced Mode) 97 4.6 Notes on Use of the Stack When accessing word data or longword data, the H8S/2138 Series or H8S/2134 Series chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF SP TRAP instruction executed MOV.B R1L, @-ER7 SP set to H'FFFEFF Legend: CCR: Condition-code register PC: Program counter R1L: General register R1L SP: Stack pointer Data saved above SP Contents of CCR lost Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.6 Operation when SP Value is Odd 98 Section 5 Interrupt Controller 5.1 5.1.1 Overview Features H8S/2138 Series and H8S/2134 Series MCUs control interrupts by means of an interrupt controller. The interrupt controller has the following features: * Two interrupt control modes Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Fifteen external interrupt pins (nine external sources) NMI is the highest-priority interrupt, and is accepted at all times. A rising or falling edge at the NMI pin can be selected for the NMI interrupt. Falling edge, rising edge, or both edge detection, or level sensing, at pins ,54 to ,54 can be selected for interrupts IRQ7 to IRQ0. The IRQ6 interrupt is shared by the interrupt from the ,54 pin and eight external interrupt inputs (.,1 to .,1). * DTC control DTC activation is controlled by means of interrupts. 99 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I, UI Interrupt request Vector number CPU Internal interrupt requests WOVI to interrupt D CCR ICR Interrupt controller Legend: ISCR: IER: ISR: ICR: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt control register System control register Figure 5.1 Block Diagram of Interrupt Controller 100 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Name Nonmaskable interrupt External interrupt requests 7 to 0 Key input interrupt requests 7 to 0 Interrupt Controller Pins Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected. Maskable external interrupts: falling edge or level sensing can be selected. ,54 to ,54 Input .,1 to .,1 Input 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt Controller Registers Abbreviation SYSCR ISCRH ISCRL IER ISR R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W 2 Initial Value H'09 H'00 H'00 H'00 H'00 H'BF H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address*1 H'FFC4 H'FEEC H'FEED H'FFC2 H'FEEB H'FFF1* H'FEE8 H'FEE9 H'FEEA H'FEF4 H'FEF5 H'FEF6 H'FEF7 3 Keyboard matrix interrupt mask KMIMR register Interrupt control register A Interrupt control register B Interrupt control register C Address break control register Break address register A Break address register B Break address register C ICRA ICRB ICRC ABRKCR BARA BARB BARC Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, for flag clearing. 3. When setting KMIMR, the HIE bit in SYSCR must be set to 1. 101 5.2 5.2.1 Bit Register Descriptions System Control Register (SYSCR) 7 CS2E 0 R/W 6 IOSE 0 R/W 5 INTM1 0 R 4 INTM0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W Initial value Read/Write SYSCR is an 8-bit readable/writable register of which bits 5, 4, and 2 select the interrupt control mode and the detected edge for NMI. Only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of four interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 1 2 3 Description Interrupts are controlled by I bit (Initial value) Interrupts are controlled by I and UI bits and ICR Cannot be used in the H8S/2138 Series or H8S/2134 Series Cannot be used in the H8S/2138 Series or H8S/2134 Series Bit 2--NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 2 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) 102 5.2.2 Bit Interrupt Control Registers A to C (ICRA to ICRC) 7 ICR7 0 R/W 6 ICR6 0 R/W 5 ICR5 0 R/W 4 ICR4 0 R/W 3 ICR3 0 R/W 2 ICR2 0 R/W 1 ICR1 0 R/W 0 ICR0 0 R/W Initial value Read/Write The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI. The correspondence between ICR settings and interrupt sources is shown in table 5.3. The ICR registers are initialized to H'00 by a reset and in hardware standby mode. Bit n--Interrupt Control Level (ICRn): Sets the control level for the corresponding interrupt source. Bit n ICRn 0 1 Description Corresponding interrupt source is control level 0 (non-priority) Corresponding interrupt source is control level 1 (priority) (n = 7 to 0) (Initial value) Table 5.3 Correspondence between Interrupt Sources and ICR Settings Bits Register 7 ICRA ICRB IRQ0 6 IRQ1 5 IRQ2 IRQ3 -- 4 IRQ4 IRQ5 -- 3 IRQ6 IRQ7 2 DTC 1 0 Watchdog Watchdog timer 0 timer 1 A/D Freeconverter running timer 8-bit 8-bit 8-bit HIF timer timer timer channel 0 channel 1 channels X, Y -- -- ICRC SCI SCI SCI IIC IIC -- channel 0 channel 1 channel 2 channel 0 channel 1 (option) (option) 103 5.2.3 Bit IRQ Enable Register (IER) 7 IRQ7E 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value Read/Write IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0--IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupt disabled IRQn interrupt enabled (n = 7 to 0) (Initial value) 104 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) * ISCRH Bit Initial value Read/Write 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA * ISCRL Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA ISCRH and ISCRL are 8-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins ,54 to ,54. Each of the ISCR registers is initialized to H'00 by a reset and in hardware standby mode. ISCRH Bits 7 to 0, ISCRL Bits 7 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) ISCRH Bits 7 to 0 ISCRL Bits 7 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at ,54 to ,54 input low level (Initial value) Interrupt request generated at falling edge of ,54 to ,54 input Interrupt request generated at rising edge of ,54 to ,54 input Interrupt request generated at both falling and rising edges of ,54 to ,54 input 105 5.2.5 Bit IRQ Status Register (ISR) 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value Read/Write Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0--IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF 0 Description [Clearing conditions] * * * 1 (Initial value) Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and ,54Q input is high When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When ,54Q input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in ,54Q input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in ,54Q input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in ,54Q input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) [Setting conditions] * * * * 106 5.2.6 Bit Keyboard Matrix Interrupt Mask Register (KMIMR) 7 1 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial value Read/Write KMIMR is an 8-bit readable/writable register that performs mask control for the keyboard matrix interrupt inputs (pins .,1 to .,1). To enable key-sense input interrupts from multiple pin inputs in keyboard matrix scanning/sensing, clear the corresponding mask bits to 0. KMIMR is initialized to H'BF by a reset and in hardware standby mode. Bits 7 to 0--Keyboard Matrix Interrupt Mask (KMIMR7 to KMIMR0): These bits control key-sense input interrupt requests (KIN7 to KIN0). Bits 7 to 0 KMIMR7 to KMIMR0 Description 0 1 Key-sense input interrupt requests enabled Key-sense input interrupt requests disabled (Initial value)* Note: * However, the initial value of KMIMR6 is 0. Figure 5.2 shows the relationship between interrupts IRQ6, interrupts KIN7 to KIN0, and registers KMIMR. KMIMR0 (initial value 1) P60/KIN0 KMIMR5 (initial value 1) P65/KIN5 KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7 IRQ6 internal signal Edge/level selection enable/disable circuit IRQ6 interrupt IRQ6E IRQ6SC Figure 5.2 Relationship between Interrupts IRQ6, Interrupts KIN7 to KIN0, and Registers KMIMR 107 When pins .,1 to .,1 are used as key-sense interrupt input pins, either low-level sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6). 5.2.7 Bit Initial value Read/Write Address Break Control Register (ABRKCR) 7 CMF 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 BIE 0 R/W ABRKCR is an 8-bit readable/writable register that performs address break control. ABRKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Condition Match Flag (CMF): This is the address break source flag, used to indicate that the address set by BAR has been prefetched. When the CMF flag and BIE flag are both set to 1, an address break is requested. Bit 7 CMF 0 1 Description [Clearing condition] When address break interrupt exception handling is executed [Setting condition] When address set by BARA to BARC is prefetched while BIE = 1 (Initial value) Bits 6 to 1--Reserved: These bits cannot be modified and are always read as 0. Bit 0--Break Interrupt Enable (BIE): Selects address break enabling or disabling. Bit 0 BIE 0 1 Description Address break disabled Address break enabled (Initial value) 108 5.2.8 Bit BARA Break Address Registers A, B, C (BARA, BARB, BARC) 7 A23 0 R/W 7 A15 0 R/W 7 A7 0 R/W 6 A22 0 R/W 6 A14 0 R/W 6 A6 0 R/W 5 A21 0 R/W 5 A13 0 R/W 5 A5 0 R/W 4 A20 0 R/W 4 A12 0 R/W 4 A4 0 R/W 3 A19 0 R/W 3 A11 0 R/W 3 A3 0 R/W 2 A18 0 R/W 2 A10 0 R/W 2 A2 0 R/W 1 A17 0 R/W 1 A9 0 R/W 1 A1 0 R/W 0 A16 0 R/W 0 A8 0 R/W 0 -- 0 -- Initial value Read/Write Bit BARB Initial value Read/Write Bit BARC Initial value Read/Write BAR consists of three 8-bit readable/writable registers (BARA, BARB, and BARC), and is used to specify the address at which an address break is to be executed. Each of the BAR registers is initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. BARA Bits 7 to 0--Address 23 to 16 (A23 to A16) BARB Bits 7 to 0--Address 15 to 8 (A15 to A8) BARC Bits 7 to 1--Address 7 to 1 (A7 to A1) These bits specify the address at which an address break is to be executed. BAR bits A15 to A1 are compared with internal address bus lines A15 to A1, respectively. The address at which the first instruction byte is located should be specified as the break address. Occurrence of the address break condition may not be recognized for other addresses. In normal mode, no comparison is made with address lines A23 to A16. BARC Bit 0--Reserved: This bit cannot be modified and is always read as 0. 109 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts. 5.3.1 External Interrupts There are nine external interrupt sources from 17 input pins (15 actual pins): NMI, ,54 to ,54, and .,1 to .,1. KIN7 to KIN0 share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to restore the H8S/2138 Series or H8S/2134 Series chip from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode and the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins ,54 to ,54. Interrupts IRQ7 to IRQ0 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins ,54 to ,54. * Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. * The interrupt control level can be set with ICR. * The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n: 7 to 0 S R Q IRQn interrupt request Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 110 Figure 5.4 shows the timing of IRQnF setting. o IRQn input pin IRQnF Figure 5.4 Timing of IRQnF Setting The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. Therefore, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR bit to 0 and use the pin as an I/O pin for another function. As interrupt request flags IRQ7F to IRQ0F are set when the setting condition is met, regardless of the IER setting, only the necessary flags should be referenced. Interrupts KIN7 to KIN0: Interrupts KIN7 to KIN0 are requested by input signals at pins .,1 to .,1. When any of pins .,1 to .,1 are used as key-sense inputs, the corresponding KMIMR bits should be cleared to 0 to enable those key-sense input interrupts. The remaining unused key-sense input KMIMR bits should be set to 1 to disable those interrupts. Interrupts KIN7 to KIN0 correspond to the IRQ6 interrupt. Interrupt request generation pin conditions, interrupt request enabling, interrupt control level setting, and interrupt request status indications, are all in accordance with the IRQ6 interrupt settings. When pins .,1 to .,1 are used as key-sense interrupt input pins, either low-level sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6). 111 5.3.2 Internal Interrupts There are 38 sources for internal interrupts from on-chip supporting modules, plus one software interrupt source (PC break). * For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If any one of these is set to 1, an interrupt request is issued to the interrupt controller. * The interrupt control level can be set by means of ICR. * The DTC can be activated by an FRT, TMR, SCI, or other interrupt request. When the DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect. 5.3.3 Interrupt Exception Vector Table Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of ICR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. 112 Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source External pin Vector Address Vector Normal Number Mode 7 16 17 18 19 20 21 22 23 DTC Watchdog timer 0 Watchdog timer 1 -- A/D -- 24 25 26 27 28 29 to 47 H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A to H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 to H'007E Advanced Mode H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 H'00006C H'000070 H'000074 to H'0000BC H'0000C0 H'0000C4 H'0000C8 H'0000CC H'0000D0 H'0000D4 H'0000D8 H'0000DC H'0000E0 to H'0000FC ICRB6 ICRB7 ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0 ICR Priorit y High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 IRQ7 SWDTEND (software activation interrupt end) WOVI0 (interval timer) WOVI1 (interval timer) PC break ADI (A/D conversion end) Reserved ICIA (input capture A) ICIB (input capture B) ICIC (input capture C) ICID (input capture D) OCIA (output compare A) OCIB (output compare B) FOVI (overflow) Reserved Reserved Free-running 48 timer 49 50 51 52 53 54 55 -- 56 to 63 Low 113 Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) Origin of Interrupt Source 8-bit timer channel 0 Vector Address Vector Normal Number Mode 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AA H'00AC H'00AE H'00B0 H'00B2 H'00B4 H'00B6 H'00B8 H'00BA H'00BC H'00BE H'00C0 to H'00CE Advanced Mode H'000100 H'000104 H'000108 H'00010C H'000110 H'000114 H'000118 H'00011C H'000120 H'000124 H'000128 H'00012C H'000130 H'000134 H'000138 H'00013C H'000140 H'000144 H'000148 H'00014C H'000150 H'000154 H'000158 H'00015C H'000160 H'000164 H'000168 H'00016C H'000170 H'000174 H'000178 H'00017C H'000180 to H'00019C ICRC3 ICR Priority Interrupt Source CMIA0 (compare-match A) CMIB0 (compare-match B) OVI0 (overflow) Reserved CMIA1 (compare-match A) CMIB1 (compare-match B) OVI1 (overflow) Reserved CMIAY (compare-match A) CMIBY (compare-match B) OVIY (overflow) ICIX (input capture X) ICRB3 High 8-bit timer channel 1 ICRB2 8-bit timer channels Y, X ICRB1 IBF1 (IDR1 reception completed) Host IBF2 (IDR2 reception completed) interface Reserved Reserved ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) RXI2 (reception completed 2) TXI2 (transmit data empty 2) TEI2 (transmission end 2) IICI0 (1-byte transmission/ reception completed) DDCSWI (format switch) IICI1 (1-byte transmission/ reception completed) Reserved Reserved SCI channel 0 ICRB0 ICRC7 SCI channel 1 ICRC6 SCI channel 2 ICRC5 IIC channel 0 92 (option) 93 IIC channel 1 94 (option) 95 -- 96 to 103 ICRC4 Low 114 5.4 5.4.1 Address Breaks Features With the H8S/2138 Series and H8S/2134 Series, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed. This function can be used to detect the beginning of execution of a bug location in the program, and branch to a correction routine. 5.4.2 Block Diagram A block diagram of the address break function is shown in figure 5.5. BAR ABRKCR Comparator Match signal Control logic Address break interrupt request Internal address Prefetch signal (internal signal) Figure 5.5 Block Diagram of Address Break Function 115 5.4.3 Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority. When the interrupt is accepted, interrupt exception handling is started on completion of the currently executing instruction. With an address break interrupt, interrupt mask control by the I and UI bits in the CPU's CCR is ineffective. The register settings when the address break function is used are as follows. 1. Set the break address in bits A23 to A1 in BAR. 2. Set the BIE bit in ABRKCR to 1 to enable address breaks. An address break will not be requested if the BIE bit is cleared to 0. When the setting condition occurs, the CMF flag in ABRKCR is set to 1 and an interrupt is requested. If necessary, the source should be identified in the interrupt handling routine. 5.4.4 Usage Notes 1. With the address break function, the address at which the first instruction byte is located should be specified as the break address. Occurrence of the address break condition may not be recognized for other addresses. 2. In normal mode, no comparison is made with address lines A23 to A16. 3. If a branch instruction (Bcc, BSR), jump instruction (JMP, JSR), RTS instruction, or RTE instruction is located immediately before the address set in BAR, execution of this instruction will output a prefetch signal for that address, and an address break may be requested. This can be prevented by not making a break address setting for an address immediately following one of these instructions, or by determining within the interrupt handling routine whether interrupt handling was initiated by a genuine condition occurrence. 4. As an address break interrupt is generated by a combination of the internal prefetch signal and address, the timing of the start of interrupt exception handling depends on the content and execution cycle of the instruction at the set address and the preceding instruction. Figure 5.6 shows some address timing examples. 116 * Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch operation fetch o Stack save Vector fetch Internal Instruction operation fetch Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 NOP NOP NOP execution execution execution Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Breakpoint Interrupt exception handling NOP instruction is executed at breakpoint address H'0312 and next address, H'0314; fetch from address H'0316 starts after end of exception handling. * Program area in on-chip memory, 2-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Stack save Vector fetch Internal Instruction operation fetch o Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 NOP execution Break request signal H'0310 H'0312 H'0316 H'0318 NOP MOV.W NOP NOP MOV.W execution Interrupt exception handling #xx:16,Rd Breakpoint MOV instruction is executed at breakpoint address H'0312, NOP instruction at next address, H'0316, is not executed; fetch from address H'0316 starts after end of exception handling. * Program area in external memory (2-state access, 16-bit-bus access), 1-state execution instruction at specified break address Instruction fetch o Instruction fetch Instruction fetch Internal operation Stack save Vector fetch Internal operation Address bus H'0310 H'0312 H'0314 SP-2 SP-4 H'0036 NOP execution Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Breakpoint Interrupt exception handling NOP instruction at breakpoint address H'0312 is not executed; fetch from address H'0312 starts after end of exception handling. Figure 5.6 Examples of Address Break Timing 117 5.5 5.5.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2138 Series and H8S/2134 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated by the I and UI bits in the CPU's CCR. Table 5.5 Interrupt Control Modes Interrupt Mask Bits Description I Interrupt mask control is performed by the I bit Priority can be set with ICR 1 1 ICR I, UI 3-level interrupt mask control is performed by the I and UI bits Priority can be set with ICR SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Register 0 0 0 ICR 118 Figure 5.7 shows a block diagram of the priority decision circuit. I ICR UI Interrupt source Interrupt acceptance control and 3-level mask control Default priority determination Vector number Interrupt control modes 0 and 1 Figure 5.7 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR (control level). Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode 0 I 0 1 1 0 1 Legend: *: Don't care UI * * * 0 1 Selected Interrupts All interrupts (control level 1 has priority) NMI interrupts All interrupts (control level 1 has priority) NMI and control level 1 interrupts NMI interrupts 119 Default Priority Determination: The priority is determined for the selected interrupt, and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.7 shows operations and control signal functions in each interrupt control mode. Table 5.7 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control Interrupt Control Mode Setting INTM1 INTM0 I 3-Level Control UI ICR Default Priority Determination T (Trace) 0 1 0 0 1 O O IM IM -- IM PR PR O O -- -- Legend: O: Interrupt operation control performed IM: Used as interrupt mask bit PR: Sets priority --: Not used 120 5.5.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Control level 1 interrupt sources have higher priority. Figure 5.8 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. 3. The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only NMI and address break interrupts are accepted, and other interrupt requests are held pending. 4. When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This disables all interrupts except NMI and address break interrupts. 7. A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 121 Program execution state Interrupt generated? Yes Yes No NMI? No Control level 1 interrupt? Yes No IRQ0? Yes No IRQ1? Yes No Hold pending No IRQ0? Yes IRQ1? Yes IICI1? Yes IICI1? Yes No I = 0? Yes No Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5.8 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 122 5.5.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU's CCR, and ICR. * Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1. * Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and disabled when both the I bit and the UI bit are set to 1. For example, if the interrupt enable bit for an interrupt request is set to 1, and H'20, H'00, and H'00 are set in ICRA, ICRB, and ICRC, respectively, (i.e. IRQ2 and IRQ3 interrupts are set to control level 1 and other interrupts to control level 0), the situation is as follows: * When I = 0, all interrupts are enabled (Priority order: NMI > IRQ2 > IRQ3 > IRQ0 > IRQ1 ...) * When I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 interrupts are enabled * When I = 1 and UI = 1, only NMI interrupts are enabled Figure 5.9 shows the state transitions in these cases. I0 All interrupts enabled I1, UI0 Only NMI, IRQ2, and IRQ3 interrupts enabled I0 Exception handling execution or I1, UI1 UI0 Exception handling execution or UI1 Only NMI interrupts enabled Figure 5.9 Example of State Transitions in Interrupt Control Mode 1 123 Figure 5.10 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. 3. The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect. An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. An interrupt request set to interrupt control level 1 has priority over an interrupt request set to interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1 and the UI bit is cleared to 0. When both the I bit and the UI bit are set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. 4. When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I and UI bits in CCR are set to 1. This disables all interrupts except NMI. 7. A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 124 Program execution state No Interrupt generated? Yes Yes NMI? No Control level 1 interrupt? Yes No No IRQ1? Yes IICI1? Yes No Hold pending No IRQ0? Yes IRQ1? Yes IICI1? Yes No IRQ0? Yes I = 0? Yes No I=0 No Yes No UI = 0? Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 125 126 Interrupt acceptance Interrupt level determination Wait for end of instruction Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt handling routine instruction prefetch o Interrupt request signal Internal address bus (1) (7) (9) 5.5.4 (3) (5) (11) (13) Interrupt Exception Handling Sequence Internal read signal Internal write signal Internal data bus (2) (4) (6) (8) (10) (12) (14) Figure 5.11 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5.11 Interrupt Exception Handling (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine 5.5.5 Interrupt Response Times The H8S/2138 Series and H8S/2134 Series are capable of fast word access to on-chip memory, and high-speed processing can be achieved by providing the program area in on-chip ROM and the stack area in on-chip RAM. Table 5.8 shows interrupt response times--the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols used in table 5.8 are explained in table 5.9. Table 5.8 Interrupt Response Times Number of States No. 1 2 3 4 5 6 Item Interrupt priority determination* 1 Normal Mode 3 1 to 19+2*SI 2*SK SI 3 Advanced Mode 3 1 to 19+2*SI 2*SK 2*SI 2*SI 2 12 to 32 Number of wait states until executing 2 instruction ends* PC, CCR stack save Vector fetch Instruction fetch* 4 2*SI 2 11 to 31 Internal processing* Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5.9 Number of States in Interrupt Handling Routine Execution Object of Access External Device 8-Bit Bus Symbol Internal Memory 1 2-State Access 4 3-State Access 6+2m Instruction fetch Branch address read Stack manipulation SI SJ SK Legend: m: Number of wait states in an external device access 127 5.6 5.6.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.12 shows an example in which the CMIEA bit in 8-bit timer register TCR is cleared to 0. TCR write cycle by CPU CMIA exception handling o Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.12 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 128 5.6.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts, including NMI, are disabled, and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.6.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 129 5.7 5.7.1 DTC Activation by Interrupt Overview The DTC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Both of the above For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller. 5.7.2 Block Diagram Figure 5.13 shows a block diagram of the DTC and interrupt controller. Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, UI Interrupt controller Figure 5.13 Interrupt Control for DTC 130 5.7.3 Operation The interrupt controller has three main functions in DTC control. Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC performs the specified number of data transfers and the transfer counter reaches 0, following the DTC data transfer the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU. Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table, for the respective priorities. Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.10 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB in the DTC. Table 5.10 Interrupt Source Selection and Clearing Control Settings DTC DTCE 0 1 DISEL * 0 1 x Interrupt Source Selection/Clearing Control DTC CPU x Legend : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. x: The relevant bit cannot be used. *: Don't care Usage Note: SCI, IIC, and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent upon the DISEL bit. 131 132 Section 6 Bus Controller 6.1 Overview The H8S/2138 Series and H8S/2134 Series have a built-in bus controller (BSC) that allows external address space bus specifications, such as bus width and number of access states, to be set. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 6.1.1 Features The features of the bus controller are listed below. * Basic bus interface 2-state access or 3-state access can be selected Program wait states can be inserted * Burst ROM interface External space can be designated as ROM interface space 1-state or 2-state burst access can be selected * Idle cycle insertion An idle cycle can be inserted when an external write cycle immediately follows an external read cycle * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC 133 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. External bus control signals Bus controller Internal control signals Bus mode signal WSCR BCR WAIT Internal data bus Wait controller CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Figure 6.1 Block Diagram of Bus Controller 134 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Name Address strobe I/O select Read Write Wait Bus Controller Pins Symbol I/O Output Output Output Output Input Function Strobe signal indicating that address output on address bus is enabled (when IOSE bit is 0) I/O select signal (when IOSE bit is 1) Strobe signal indicating that external space is being read Strobe signal indicating that external space is being written to, and that data bus is enabled Wait request signal when external 3-state access space is accessed $6 ,26 5' :5 :$,7 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Name Bus control register Wait state control register Bus Controller Registers Abbreviation BCR WSCR R/W R/W R/W Initial Value H'D7 H'33 Address* H'FFC6 H'FFC7 Note: * Lower 16 bits of the address. 135 6.2 6.2.1 Bit Register Descriptions Bus Control Register (BCR) 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 -- 1 R/W 1 IOS1 1 R/W 0 IOS0 1 R/W BRSTRM BRSTS1 BRSTS0 Initial value Read/Write BCR is an 8-bit readable/writable register that specifies the external memory space access mode, and the extent of the I/O area when the I/O strobe function has been selected for the $6 pin. BCR is initialized to H'D7 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Idle Cycle Insert 1 (ICIS1): Reserved. Do not write 0 to this bit. Bit 6--Idle Cycle Insert 0 (ICIS0): Selects whether or not a one-state idle cycle is to be inserted between bus cycles when successive external read and external write cycles are performed. Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value) Bit 5--Burst ROM Enable (BRSTRM): Selects whether external space is designated as a burst ROM interface space. The selection applies to the entire external space . Bit 5 BRSTRM 0 1 Description Basic bus interface Burst ROM interface (Initial value) 136 Bit 4--Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3--Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bit 2--Reserved: Do not write 0 to this bit. Bits 1 and 0--IOS Select 1 and 0 (IOS1, IOS0): See table 6.4. 6.2.2 Bit Initial value Read/Write Wait State Control Register (WSCR) 7 RAMS 0 R/W 6 RAM0 0 R/W 5 ABW 1 R/W 4 AST 1 R/W 3 WMS1 0 R/W 2 WMS0 0 R/W 1 WC1 1 R/W 0 WC0 1 R/W WSCR is an 8-bit readable/writable register that specifies the data bus width, number of access states, wait mode, and number of wait states for external memory space. The on-chip memory and internal I/O register bus width and number of access states are fixed, irrespective of the WSCR settings. WSCR is initialized to H'33 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--RAM Select (RAMS)/Bit 6--RAM Area Setting (RAM0): Reserved bits. 137 Bit 5--Bus Width Control (ABW): Specifies whether the external memory space is 8-bit access space or 16-bit access space. However, a 16-bit access space cannot be specified for these series, and therefore 0 should not be written to this bit. Bit 5 ABW 0 1 Description External memory space is designated as 16-bit access space (A 16-bit access space cannot be specified for these series) External memory space is designated as 8-bit access space (Initial value) Bit 4--Access State Control (AST): Specifies whether the external memory space is 2-state access space or 3-state access space, and simultaneously enables or disables wait state insertion. Bit 4 AST 0 1 Description External memory space is designated as 2-state access space Wait state insertion in external memory space accesses is disabled External memory space is designated as 3-state access space Wait state insertion in external memory space accesses is enabled (Initial value) Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1, WMS0): These bits select the wait mode when external memory space is accessed while the AST bit is set to 1. Bit 3 WMS1 0 Bit 2 WMS0 0 1 1 0 1 Description Program wait mode Wait-disabled mode Pin wait mode Pin auto-wait mode (Initial value) 138 Bits 1 and 0--Wait Count 1 and 0 (WC1, WC0): These bits select the number of program wait states when external memory space is accessed while the AST bit is set to 1. Bit 1 WC1 0 Bit 0 WC0 0 1 1 0 1 Description No program wait states are inserted 1 program wait state is inserted in external memory space accesses 2 program wait states are inserted in external memory space accesses 3 program wait states are inserted in external memory space accesses (Initial value) 6.3 6.3.1 Overview of Bus Control Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and wait mode and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with the ABW bit. A 16-bit access space cannot be specified for these series. Number of Access States: Two or three access states can be selected with the AST bit. When 2-state access space is designated, wait insertion is disabled. The number of access states on the burst ROM interface is determined without regard to the AST bit setting. 139 Wait Mode and Number of Program Wait States: When 3-state access space is designated by the AST bit, the wait mode and the number of program wait states to be inserted automatically is selected with WMS1, WMS0, WC1, and WC0. From 0 to 3 program wait states can be selected. Table 6.3 shows the bus specifications for each basic bus interface area. Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) Bus Specifications (Basic Bus Interface) ABW 0 1 AST 0 0 1 WMS1 WMS0 WC1 -- -- 0 --* -- -- 1 --* -- -- -- 0 WC0 -- -- -- 0 1 1 0 1 Note: * Except when WMS1 = 0 and WMS0 = 1 Bus Width Access States Program Wait States Cannot be used in the H8S/2138 Series or H8S/2134 Series. 8 8 2 3 3 0 0 0 1 2 3 6.3.2 Advanced Mode The H8S/2138 and H8S/2134 have 16 address output pins, so there are no pins for output of the upper address bits (A16 to A23) in advanced mode. H'FFF000 to H'FFFE4F can be accessed by designating the $6 pin as an I/O strobe pin. The accessible external space is therefore H'FFF000 to H'FFFE4F even when expanded mode with ROM enabled is selected in advanced mode. The initial state of the external space is basic bus interface, three-state access space. In ROMenabled expanded mode, the space excluding the on-chip ROM, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. 140 6.3.3 Normal Mode The initial state of the external memory space is basic bus interface, three-state access space. In ROM-disabled expanded mode, the space excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled expanded mode, the space excluding the on-chip ROM, onchip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. 6.3.4 I/O Select Signal In the H8S/2138 Series and H8S/2134 Series, an I/O select signal (,26) can be output, with the signal output going low when the designated external space is accessed. Figure 6.2 shows an example of ,26 signal output timing. Bus cycle T1 o T2 T3 Address bus External address in IOS set range IOS Figure 6.2 ,26 Signal Output Timing 141 Enabling or disabling of ,26 signal output is controlled by the setting of the IOSE bit in SYSCR. In expanded mode, this pin operates as the $6 output pin after a reset, and therefore the IOSE bit in SYSCR must be set to 1 in order to use this pin as the ,26 signal output. See section 8, I/O Ports, for details. The range of addresses for which the ,26 signal is output can be set with bits IOS1 and IOS0 in BCR. The ,26 signal address ranges are shown in table 6.4. Table 6.4 IOS1 0 ,26 Signal Output Range Settings ,26 IOS0 0 1 Signal Output Range H'(FF)F000 to H'(FF)F03F H'(FF)F000 to H'(FF)F0FF H'(FF)F000 to H'(FF)F3FF H'(FF)F000 to H'(FF)FE4F (Initial value) 1 0 1 6.4 6.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with the AST bit, and the WMS1, WMS0, WC1, and WC0 bits (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. These series only have an upper data bus, and only 8-bit access space alignment is used. In these series, the upper data bus pins are designated D7 to D0. 142 8-Bit Access Space: Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space (Cannot be Used in the H8S/2138 Series or H8S/2134 Series): Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Lower data bus Upper data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle * Even address * Odd address Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space) 143 6.4.3 Valid Strobes Table 6.5 shows the data buses used and valid strobes for the access spaces. In a read, the 5' signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the +:5 signal is valid for the upper half of the data bus, and the /:5 signal for the lower half. These series only have an upper data bus, and only the 5' and +:5 signals are valid. In these series, the +:5 signal pin is designated :5. Table 6.5 Area 8-bit access space Data Buses Used and Valid Strobes Access Read/ Size Write Byte Read Write Valid Address Strobe -- -- Even Odd Write Even Odd Word Read Write -- -- Upper Data Bus Lower Data Bus (D15 to D8)*1 (D7 to D0)*3 Valid 2 16-bit access space Byte (Cannot be used in the H8S/2138 Series or H8S/2134 Series) Read 5' +:5* 5' Port, etc. Port, etc. Valid Invalid Invalid Valid Undefined Valid Valid Valid +:5 /:5 5' +:5, /:5 Valid Undefined Valid Valid Notes: Undefined: Undefined data is output. Invalid: Input state; input value is ignored. Port, etc.: Pins are used as port or on-chip supporting module input/output pins, and not as data bus pins. 1. The pin names in these series are D7 to D0. 2. The pin name in these series is :5. 3. There are no lower data bus pins in these series. 144 6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. These series have no lower data bus (D7 to D0) pins or /:5 pin. In these series, the upper data bus (D15 to D8) pins are designated D7 to D0, and the +:5 signal pin is designated :5. Bus cycle T1 o T2 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.5 Bus Timing for 8-Bit 2-State Access Space 145 8-Bit 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. These series have no lower data bus (D7 to D0) pins or /:5 pin. In these series, the upper data bus (D15 to D8) pins are designated D7 to D0, and the +:5 signal pin is designated :5. Bus cycle T1 o T2 T3 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.6 Bus Timing for 8-Bit 3-State Access Space 146 6.4.5 Wait Control When accessing external space, the MCU can extend the bus cycle by inserting one or more wait states (TW). There are three ways of inserting wait states: program wait insertion, pin wait insertion using the :$,7 pin, and a combination of the two. Program Wait Mode In program wait mode, the number of TW states specified by bits WC1 and WC0 are always inserted between the T2 and T3 states when external space is accessed. Pin Wait Mode In pin wait mode, the number of TW states specified by bits WC1 and WC0 are always inserted between the T2 and T3 states when external space is accessed. If the :$,7 pin is low at the fall of o in the last T2 or TW state, another TW state is inserted. If the :$,7 pin is held low, TW states are inserted until it goes high. Pin wait mode is useful for inserting four or more wait states, or for changing the number of T W states for different external devices. Pin Auto-Wait Mode In pin auto-wait mode, if the :$,7 pin is low at the fall of the system clock in the T2 state, the number of TW states specified by bits WC1 and WC0 are inserted between the T2 and T3 states when external space is accessed. No additional TW states are inserted even if the :$,7 pin remains low. Pin auto-wait mode can be used for an easy interface to low-speed memory, simply by routing the chip select signal to the :$,7 pin. Figure 6.7 shows an example of wait state insertion timing. 147 By program wait T1 o T2 Tw By WAIT pin Tw Tw T3 WAIT Address bus AS (IOSE = 0) RD Read Data bus Read data WR Write Data bus Write data Note: indicates the timing of WAIT pin sampling using the o clock. Figure 6.7 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, insertion of 3 program wait states, and WAIT input disabled. 148 6.5 6.5.1 Burst ROM Interface Overview With the H8S/2138 Series and H8S/2134 Series, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. External space can be designated as burst ROM space by means of the BRSTRM bit in BCR. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 6.5.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST bit. Also, when the AST bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCR. Wait states cannot be inserted. When the BRSTS0 bit in BCR is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figure 6.8 (a) and (b). The timing shown in figure 6.8 (a) is for the case where the AST and BRSTS1 bits are both set to 1, and that in figure 6.8 (b) is for the case where both these bits are cleared to 0. 149 Full access T1 o T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changed AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.8 (a) Example of Burst ROM Access Timing (When AST = BRSTS1 = 1) Full access T1 T2 Burst access T1 T1 o Address bus Only lower address changed AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.8 (b) Example of Burst ROM Access Timing (When AST = BRSTS1 = 0) 150 6.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the :$,7 pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. 6.6 6.6.1 Idle Cycle Operation When the H8S/2138 Series or H8S/2134 Series chip accesses external space, it can insert a 1state idle cycle (TI) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. If an external write occurs after an external read while the ICIS0 bit in BCR is set to 1, an idle cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal mode. Figure 6.9 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 o Address bus T2 T3 Bus cycle B T1 T2 o Address bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 RD WR Data bus RD WR Data bus Data collision Long output floating time (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.9 Example of Idle Cycle Operation 151 6.6.2 Pin States in Idle Cycle Table 6.5 shows pin states in an idle cycle. Table 6.5 Pins A15 to A0, ,26 D7 to D0 Pin States in Idle Cycle Pin State Contents of next bus cycle High impedance High High High $6 5' :5 6.7 6.7.1 Bus Arbitration Overview The H8S/2138 Series and H8S/2134 Series have a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and the DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 6.7.2 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from both bus masters, the bus request acknowledge signal is sent to the one with the higher priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) 152 6.7.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the DTC. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not transferred. * If the CPU is executing a multiply or divide instruction or similar internal operation, it transfers the bus immediately. * If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC does not release the bus until it has completed a series of processing operations. 153 154 Section 7 Data Transfer Controller [H8S/2138 Series] Provided in the H8S/2138 Series; not provided in the H8S/2134 Series. 7.1 Overview The H8S/2138 Series includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 7.1.1 Features * Transfer possible over any number of channels Transfer information is stored in memory One activation source can trigger a number of data transfers (chain transfer) * Wide range of transfer modes Normal, repeat, and block transfer modes available Incrementing, decrementing, and fixing of transfer source and destination addresses can be selected * Direct specification of 16-Mbyte address space possible 24-bit transfer source and destination addresses can be specified * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends An interrupt request can be issued to the CPU after all specified data transfers have ended * Activation by software is possible * Module stop mode can be set The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode 155 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request Legend: MRA, MRB: DTC mode registers A and B CRA, CRB: DTC transfer count registers A and B SAR: DTC source address register DAR: DTC destination address register DTCERA to DTCERE: DTC enable registers A to E DTVECR: DTC vector register DTC activation request Figure 7.1 Block Diagram of DTC 156 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information Control logic DTCERA to DTCERE DTVECR 7.1.3 Register Configuration Table 7.1 summarizes the DTC registers. Table 7.1 Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register DTC Registers Abbreviation MRA MRB SAR DAR CRA CRB DTCER* 4 4 R/W --* --* --* --* --* --* 2 2 Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3F H'FF Address*1 --* --* --* --* --* --* 3 3 2 3 2 3 2 3 2 3 R/W R/W R/W R/W H'FEEE to H'FEF2 H'FEF3 H'FF86 H'FF87 DTVECR* MSTPCRH MSTPCRL Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Addresses H'EC00 to H'EFFF contain register information. They cannot be located in external memory space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. 4. The H8S/2134 Series does not include an on-chip DTC, and therefore the DTCER and DTVECR register addresses should not be accessed by the CPU. 157 7.2 7.2.1 Bit Register Descriptions DTC Mode Register A (MRA) 7 SM1 Undefined -- 6 SM0 Undefined -- 5 DM1 Undefined -- 4 DM0 Undefined -- 3 MD1 Undefined -- 2 MD0 Undefined -- 1 DTS Undefined -- 0 Sz Undefined -- Initial value Read/Write MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6--Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 -- 0 1 Description SAR is fixed SAR is incremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) SAR is decremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) Bits 5 and 4--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 -- 0 1 Description DAR is fixed DAR is incremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) DAR is decremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) 158 Bits 3 and 2--DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 Bit 2 MD0 0 1 1 0 1 Description Normal mode Repeat mode Block transfer mode -- Bit 1--DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0--DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer 159 7.2.2 Bit DTC Mode Register B (MRB) 7 CHNE Undefined -- 6 DISEL Undefined -- 5 -- Undefined -- 4 -- Undefined -- 3 -- Undefined -- 2 -- Undefined -- 1 -- Undefined -- 0 -- Undefined -- Initial value Read/Write MRB is an 8-bit register that controls the DTC operating mode. Bit 7--DTC Chain Transfer Enable (CHNE): Specifies chain transfer. In chain transfer, multiple data transfers can be performed consecutively in response to a single transfer request. With data transfer for which CHNE is set to 1, there is no determination of the end of the specified number of transfers, clearing of the interrupt source flag, or clearing of DTCER. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred) Bit 6--DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0--Reserved: In the H8S/2138 Series these bits have no effect on DTC operation, and should always be written with 0. 160 7.2.3 Bit DTC Source Address Register (SAR) 23 22 21 20 19 4 3 2 1 0 Initial value Read/write Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4 Bit Initial value Read/write DTC Destination Address Register (DAR) 23 22 21 20 19 4 3 2 1 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 7.2.5 Bit Initial value Read/Write DTC Transfer Count Register A (CRA) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 161 In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are transferred when the count reaches H'00. This operation is repeated. 7.2.6 Bit Initial value Read/Write DTC Transfer Count Register B (CRB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 7.2.7 Bit Initial value Read/Write DTC Enable Registers (DTCER) 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. 162 Bit n--DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by interrupt is disabled [Clearing conditions] * * 1 When data transfer ends with the DISEL bit set to 1 When the specified number of transfers end (Initial value) DTC activation by interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number generated by the interrupt controller in each case. For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. 7.2.8 Bit Initial value Read/Write DTC Vector Register (DTVECR) 7 0 R/(W)* 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. 163 Bit 7--DTC Software Activation Enable (SWDTE): Specifies enabling or disabling of DTC software activation. To clear the SWDTE bit by software, read SWDTE when set to 1, then write 0 in the bit. Bit 7 SWDTE 0 1 Description DTC software activation is disabled (Initial value) [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended DTC software activation is enabled [Holding conditions] * When data transfer ends with the DISEL bit set to 1 * When the specified number of transfers end * During software-activated data transfer Bits 6 to 0--DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is H'0400 + (vector number) << 1 (where << 1 indicates a 1-bit left shift). For example, if DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. 7.2.9 Module Stop Control Register (MSTPCR) MSTPCRH Bit Initial value Read/Write 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP14 bit in MSTPCR is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. Note that 1 cannot be written to the MSTP14 bit when the DTC is being activated. For details, see section 23.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. 164 MSTPCRH Bit 6--Module Stop (MSTP14): Specifies the DTC module stop mode. MSTPCRH Bit 6 MSTP14 0 1 Description DTC module stop mode is cleared DTC module stop mode is set (Initial value) 7.3 7.3.1 Operation Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation. Figure 7.2 shows a flowchart of DTC operation. 165 Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? No Yes Transfer counter = 0 or DISEL = 1? No Clear activation flag Yes Clear DTCER End Interrupt exception handling Figure 7.2 Flowchart of DTC Operation The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. 166 Table 7.2 outlines the functions of the DTC. Table 7.2 DTC Functions Address Registers Transfer Transfer Source Destination 24 bits 24 bits Transfer Mode * Normal mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65,536 transfers possible * Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers (1 to 256), the initial state resumes and operation continues * Block transfer mode One transfer request transfers a block of the specified size Block size is from 1 to 256 bytes or words Up to 65,536 transfers possible A block area can be designated at either the source or destination Activation Source * IRQ * FRT ICI, OCI * 8-bit timer CMI * Host interface IBF * SCI TXI or RXI * A/D converter ADI * IIC IICI * Software 7.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software (software activation). An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. The interrupt request is directed to the DTC when the corresponding bit is set to 1, and to the CPU when the bit is cleared to 0. At the end of one data transfer (or the last of the consecutive transfers in the case of chain transfer) the interrupt source or the corresponding DTCER bit is cleared. Table 7.3 shows activation sources and DTCER clearing. The interrupt source flag for RXI0, for example, is the RDRF flag in SCI0. 167 Table 7.3 Activation Source Software activation Interrupt activation Activation Sources and DTCER Clearing When DISEL Bit Is 0 and Specified Number of Transfers Have Not Ended SWDTE bit cleared to 0 * * Corresponding DTCER bit held at 1 Activation source flag cleared to 0 When DISEL Bit Is 1 or Specified Number of Transfers Have Ended * * * * * SWDTE bit held at 1 Interrupt request sent to CPU Corresponding DTCER bit cleared to 0 Activation source flag held at 1 Activation source interrupt request sent to CPU Figure 7.3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. Source flag cleared Clear control Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request Selection circuit DTC DTVECR Interrupt controller Interrupt mask CPU Figure 7.3 Block Diagram of DTC Activation Source Control When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC is activated in accordance with the default priorities. 168 7.3.3 DTC Vector Table Figure 7.4 shows the correspondence between DTC vector addresses and register information. Table 7.4 shows the correspondence between activation sources, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + DTVECR[6:0] << 1 (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. The register information can be placed at predetermined addresses in the on-chip RAM. The start address of the register information should be an integral multiple of four. The configuration of the vector address is the same in both normal and advanced modes, a 2byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. 169 Table 7.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Vector Interrupt Source Number Software DTVECR Vector Address H'0400 + DTVECR [6:0] << 1 H'0420 H'0422 H'0424 H'0426 H'0438 H'0460 H'0462 H'0468 H'046A H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0498 H'049A H'04A2 H'04A4 H'04AA H'04AC H'04B2 H'04B4 H'04B8 DTCE* -- Priority High Interrupt Source Write to DTVECR IRQ0 IRQ1 IRQ2 IRQ3 ADI (A/D conversion end) ICIA (FRT input capture A) ICIB (FRT input capture B) OCIA (FRT output compare A) OCIB (FRT output compare B) External pin 16 17 18 19 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED7 DTCED6 DTCED5 DTCED4 A/D FRT 28 48 49 52 54 64 65 68 69 72 73 76 77 81 82 85 86 89 90 92 CMIA0 (TMR0 compare-match A) TMR0 CMIB0 (TMR0 compare-match B) CMIA1 (TMR1 compare-match A) TMR1 CMIB1 (TMR1 compare-match B) CMIAY (TMRY compare-match A) TMRY CMIBY (TMRY compare-match B) IBF1 (IDR1 reception completed) IBF2 (IDR2 reception completed) RXI0 (reception completed 0) TXI0 (transmit data empty 0) RXI1 (reception completed 1) TXI1 (transmit data empty 1) RXI2 (reception completed 2) TXI2 (transmit data empty 2) IICI0 (IIC0 1-byte transmission/ reception completed) IIC0 (option) SCI channel 2 SCI channel 1 SCI channel 0 HIF IICI1 (IIC1 1-byte transmission/ IIC1 (option) 94 H'04BC DTCED3 reception completed) Low Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0. 170 DTC vector address Register information start address Register information Chain transfer Figure 7.4 Correspondence between DTC Vector Address and Register Information 7.3.4 Location of Register Information in Address Space Figure 7.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (vector address contents). In chain transfer, locate the register information in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF). Lower address 0 Register information start address Chain transfer MRA MRB CRA MRA MRB CRA 4 bytes SAR DAR CRB 1 2 SAR DAR CRB Register information for 2nd transfer in chain transfer Register information 3 Figure 7.5 Location of DTC Register Information in Address Space 171 7.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in normal mode. Table 7.5 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Information in Normal Mode Abbreviation SAR DAR CRA CRB Function Transfer source address Transfer destination address Transfer count Not used SAR Transfer DAR Figure 7.6 Memory Mapping in Normal Mode 172 7.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial address register state specified by the transfer counter and repeat area resumes and transfer is repeated. In repeat mode the transfer counter does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 7.6 lists the register information in repeat mode and figure 7.7 shows memory mapping in repeat mode. Table 7.6 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds number of transfers Transfer count Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 7.7 Memory Mapping in Repeat Mode 173 7.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is specified as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified in the block area is restored. The other address register is successively incremented or decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 7.7 lists the register information in block transfer mode and figure 7.8 shows memory mapping in block transfer mode. Table 7.7 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds block size Block size count Transfer counter 174 First block SAR or DAR * * * Block area Transfer DAR or SAR Nth block Figure 7.8 Memory Mapping in Block Transfer Mode 175 7.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.9 shows memory mapping for chain transfer. Source Destination Register information CHNE = 1 DTC vector address Register information start address Register information CHNE = 0 Source Destination Figure 7.9 Memory Mapping in Chain Transfer In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. 176 7.3.9 Operation Timing Figures 7.10 to 7.12 show examples of DTC operation timing. o DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Transfer information write Figure 7.10 DTC Operation Timing (Normal Mode or Repeat Mode) o DTC activation request DTC request Vector read Address Transfer information read Data transfer Read Write Read Write Transfer information write Figure 7.11 DTC Operation Timing (Block Transfer Mode, with Block Size of 2) 177 o DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Read Write Data transfer Transfer Transfer information information write read Transfer information write Figure 7.12 DTC Operation Timing (Chain Transfer) 7.3.10 Number of DTC Execution States Table 7.8 lists execution phases for a single DTC data transfer, and table 7.9 shows the number of states required for each execution phase. Table 7.8 DTC Execution Phases Vector Read I 1 1 1 Register Information Read/Write Data Read J K 6 6 6 1 1 N Data Write L 1 1 N Internal Operation M 3 3 3 Mode Normal Repeat Block transfer N: Block size (initial setting of CRAH and CRAL) 178 Table 7.9 Number of States Required for Each Execution Phase OnOnInternal I/O Chip RAM Chip ROM Registers 32 1 SI SJ -- 1 16 1 1 -- 8 2 -- -- 16 2 -- -- External Devices 8 2 4 -- 8 3 6+2m -- Object of Access Bus width Access states Execution phase Vector read Register information read/write Byte data read Word data read Byte data write Word data write SK SK SL SL 1 1 1 1 1 1 1 1 1 1 2 4 2 4 1 2 2 2 2 1 2 4 2 4 1 3+m 6+2m 3+m 6+2m 1 Internal operation SM The number of execution states is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number for which the CHNE bit is set to one, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. 7.3.11 Procedures for Using the DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. 179 Activation by Software: The procedure for using the DTC with software activation is as follows: 1. 2. 3. 4. 5. 6. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Check that the SWDTE bit is 0. Write 1 in the SWDTE bit and the vector number to DTVECR. Check the vector number written to DTVECR. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. Examples of Use of the DTC 7.3.12 Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. 180 Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. 7.4 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software-activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 181 7.5 Usage Notes Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. When the DTC is placed in the module stop state, the DTCER registers must all be in the cleared state when the MSTP14 bit is set to 1. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in onchip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. DTCE Bit Setting: For DTCE bit setting, read/write operations must be performed using bitmanipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. 182 Section 8 I/O Ports 8.1 Overview The H8S/2138 Series and H8S/2134 Series have eight I/O ports (ports 1 to 6, 8, and 9), and one input-only port (port 7). Tables 8.1 and 8.2 summarize the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port) and data registers (DR, ODR) that store output data. Ports 1 to 3, and 6 have a built-in MOS input pull-up function. Ports 1 to 3 and 6 have a MOS input pull-up control register (PCR), in addition to DDR and DR, to control the on/off status of the MOS input pull-ups. Ports 1 to 6, 8, and 9 can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Ports 1, 2, and 3 can drive an LED (10 mA sink current). In the H8S/2138 Series, P52 in port 5 and P97 in port 9 are NMOS push-pull outputs. Note that the H8S/2134 Series has subset specifications that do not include some supporting modules. For differences in pin functions, see table 8.1, H8S/2138 Series Port Functions, and table 8.2, H8S/2134 Series Port Functions. Table 8.1 H8S/2138 Series Port Functions Expanded Modes Port Description Pins Mode 1 Lower address output (A7 to A0) Mode 2, Mode 3 (EXPE = 1) When DDR = 0 (after reset): input port When DDR = 1: lower address output (A7 to A0) or PWM timer output (PW7 to PW0) Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as PWM timer output (PW7 to PW0) Port 1 * 8-bit I/O P17 to P10/ port A7 to A0/ PW7 to PW0 * Built-in MOS input pull-ups * LED drive capability 183 Table 8.1 H8S/2138 Series Port Functions (cont) Expanded Modes Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as PWM timer output (PW15 to PW8) and timer connection output (CBLANK) Port Port 2 Description Pins Mode 1 Mode 2, Mode 3 (EXPE = 1) * 8-bit I/O port P27/A15/PW15/ * Built-in MOS CBLANK input pull-ups P26/A14/PW14 * LED drive capability P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 Upper address When DDR = 0 output (after reset): input (A15 to A8) port or timer connection output (CBLANK) When DDR = 1: upper address output (A15 to A8), PWM timer output (PW15 to PW8), timer connection output (CBLANK), or output ports (P27 to P24) Data bus input/output (D7 to D0) Port 3 * 8-bit I/O port P37 to P30/ * Built-in MOS HDB7 to HDB0/ input pull-ups D7 to D0 * LED drive capability I/O port also functioning as host interface data bus input/output (HDB7 to HDB0) Port 4 * 8-bit I/O port P47/PWX1 P46/PWX0 P45/TMRI1/ HIRQ12/CSYNCI P44/TMO1/ HIRQ1/HSYNCO P43/TMCI1/ HIRQ11/HSYNCI P42/TMRI0/ SCK2/SDA1 P41/TMO0/ RxD2/IrRxD P40/TMCI0/ TxD2/IrTxD I/O port also functioning as 14-bit PWM timer output (PWX1, PWX0), 8-bit timer 0 and 1 input/output (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection input/output (HSYNCO, CSYNCI, HSYNCI), SCI2 input/output (TxD2, RxD2, SCK2), IrDA interface 2 input/output (IrTxD, IrRxD), and I C bus interface 1 (option) input/output (SDA1) I/O port also functioning as 14-bit PWM timer output (PWX1, PWX0), 8-bit timer 0 and 1 input/ output (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection input/output (HSYNCO, CSYNCI, HSYNCI), host interface host CPU interrupt request output (HIRQ12, HIRQ1, HIRQ11), SCI2 input/ output (TxD2, RxD2, SCK2), IrDA interface input/output 2 (IrTxD, IrRxD), and I C bus interface 1 (option) input/output (SDA1) 184 Table 8.1 H8S/2138 Series Port Functions (cont) Expanded Modes Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) Port Port 5 Description Pins Mode 1 Mode 2, Mode 3 (EXPE = 1) * 3-bit I/O port P52/SCK0/SCL0 P51/RxD0 P50/TxD0 I/O port also functioning as SCI0 input/output (TxD0, RxD0, SCK0) 2 and I C bus interface 0 (option) input/output (SCL0) Port 6 * 8-bit I/O port P67/,54/TMOX/ .,1/CIN7 P66/,54/FTOB/ .,1/CIN6 P65/FTID/.,1/ CIN5 P64/FTIC/.,1/ CIN4/CLAMPO P63/FTIB/.,1/ CIN3/VFBACKI P62/FTIA/TMIY/ I/O port also functioning as external interrupt input (,54, ,54), FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB), 8bit timer X and Y input/output (TMOX, TMIX, TMIY), timer connection input/output (CLAMPO, VFBACKI, VSYNCI, VSYNCO, HFBACKI), key-sense interrupt input (.,1 to .,1), and expansion A/D converter input (CIN7 to CIN0) .,1/CIN2/ VSYNCI P61/FTOA/.,1/CIN 1/VSYNCO P60/FTCI/TMIX/ .,1/CIN0/ HFBACKI Port 7 * 8-bit input port P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 Input port also functioning as A/D converter analog input (AN7 to AN0) and D/A converter analog output (DA1, DA0) 185 Table 8.1 H8S/2138 Series Port Functions (cont) Expanded Modes Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port also functioning as external interrupt input (,54, ,54, ,54), SCI1 input/output (TxD1, RxD1, SCK1), host interface control input/output (&6, 2 GA20, HA0, HIFSD), and I C bus interface 1 (option) input/output (SCL1) Port Port 8 Description Pins Mode 1 Mode 2, Mode 3 (EXPE = 1) * 7-bit I/O port P86/,54/SCK1/SC I/O port also functioning as external L1 interrupt input (,54, ,54, ,54), SCI1 input/ P85/,54/RxD1 output (TxD1, RxD1, SCK1), and 2 P84/,54/TxD1 I C bus interface 1 (option) input/output (SCL1) P83 P82/HIFSD P81/&6/GA20 P80/HA0 Port 9 * 8-bit I/O port P97/:$,7/SDA0 I/O port also functioning as expanded data bus control input 2 (:$,7) and I C bus interface 0 (option) input/output (SDA0) I/O port also functioning as 2 I C bus interface 0 (option) input/output (SDA0) P96/o/EXCL When DDR = When DDR = 0 (after reset): input port or EXCL 0: input port or input EXCL input When DDR = 1: o output When DDR = 1 (after reset): o output Expanded data bus control output ($6/,26, :5, 5') I/O port also functioning as host interface control input (&6, ,2:, ,25) P95/$6/,26/&6 P94/:5/,2: P93/5'/,25 P92/,54 P91/,54 P90/,54/ I/O port also functioning as external interrupt input (,54, ,54) $'75*/(&62 I/O port also functioning as external interrupt input (,54), and A/D converter external trigger input ($'75*) I/O port also functioning as external interrupt input (,54), A/D converter external trigger input ($'75*), and host interface control input ((&6) 186 Table 8.2 H8S/2134 Series Port Functions Expanded Modes Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port Port Port 1 Description Pins Mode 1 Mode 2, Mode 3 (EXPE = 1) * 8-bit I/O port P17 to P10/ * Built-in MOS A7 to A0 input pull-ups * LED drive capability * 8-bit I/O port P27 to P20/ * Built-in MOS A15 to A8 input pull-ups * LED drive capability Lower address When DDR = 0 output (A7 to (after reset): input A0) port When DDR = 1: lower address output (A7 to A0) Upper address When DDR = 0 output (A15 to (after reset): input A8) port When DDR = 1: upper address output (A15 to A8) or output port (P27 to P24) Data bus input/output (D7 to D0) Port 2 I/O port Port 3 * 8-bit I/O port P37 to P30/ * Built-in MOS D7 to D0 input pull-ups * LED drive capability I/O port Port 4 * 8-bit I/O port P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/ IrRxD P40/TMCI0/ TxD2/IrTxD I/O port also functioning as 14-bit PWM timer output (PWX1, PWX0), 8-bit timer 0 and 1 input/output (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), SCI2 input/output (TxD2, RxD2, SCK2), and IrDA interface input/output (IrTxD, IrRxD) Port 5 * 3-bit I/O port P52/SCK0 P51/RxD0 P50/TxD0 I/O port also functioning as SCI0 input/output (TxD0, RxD0, SCK0) 187 Table 8.2 H8S/2134 Series Port Functions (cont) Expanded Modes Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) Port Port 6 Description Pins Mode 1 Mode 2, Mode 3 (EXPE = 1) * 8-bit I/O port P67/,54/.,1/ CIN7 P66/,54/FTOB/ .,1/CIN6 P65/FTID/.,1/ CIN5 P64/FTIC/.,1/ CIN4 P63/FTIB/.,1/ CIN3 P62/FTIA/TMIY/ I/O port also functioning as external interrupt input (,54, ,54), FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB), 8bit timer Y input (TMIY), key-sense interrupt input (.,1 to .,1), and expansion A/D converter input (CIN7 to CIN0) .,1/CIN2 P61/FTOA/.,1/CIN 1 P60/FTCI/.,1/ CIN0 Port 7 * 8-bit input port P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 Port 8 * 7-bit I/O port P86/,54/SCK1 P85/,54/RxD1 P84/,54/TxD1 P83 P82 P81 P80 Input port also functioning as A/D converter analog input (AN7 to AN0) and D/A converter analog output (DA1, DA0) ,54) and SCI1 input/output (TxD1, RxD1, SCK1) I/O port also functioning as external interrupt input (,54, ,54, 188 Table 8.2 H8S/2134 Series Port Functions (cont) Expanded Modes Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O port Port Port 9 Description Pins Mode 1 Mode 2, Mode 3 (EXPE = 1) * 8-bit I/O port P97/:$,7 I/O port also functioning as expanded data bus control input (:$,7) P96/o/EXCL When DDR = When DDR = 0 (after reset): input port or EXCL 0: input port or input EXCL input When DDR = 1: o output When DDR = 1 (after reset): o output Expanded data bus control output($6/,26, :5, 5') I/O port P95/$6/,26 P94/:5 P93/5' P92/,54 P91/,54 P90/,54/ I/O port also functioning as external interrupt input (,54, ,54) $'75* I/O port also functioning as external interrupt input (,54), and A/D converter external trigger input ($'75*) I/O port also functioning as external interrupt input (,54) and A/D converter external trigger input ($'75*) 189 8.2 8.2.1 Port 1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as address bus output pins (A7 to A0), and as 8-bit PWM output pins (PW7 to PW0) (H8S/2138 Series only). Port 1 functions change according to the operating mode. Port 1 has a built-in MOS input pull-up function that can be controlled by software. Figure 8.1 shows the port 1 pin configuration. Port 1 pins P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 Port 1 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 Pin functions in mode 1 A7 (Output) A6 (Output) A5 (Output) A4 (Output) A3 (Output) A2 (Output) A1 (Output) A0 (Output) Pin functions in modes 2 and 3 (EXPE = 1) A7 (Output)/P17 (Input)/PW7 (Output) A6 (Output)/P16 (Input)/PW6 (Output) A5 (Output)/P15 (Input)/PW5 (Output) A4 (Output)/P14 (Input)/PW4 (Output) A3 (Output)/P13 (Input)/PW3 (Output) A2 (Output)/P12 (Input)/PW2 (Output) A1 (Output)/P11 (Input)/PW1 (Output) A0 (Output)/P10 (Input)/PW0 (Output) Pin functions in modes 2 and 3 (EXPE = 0) P17 (I/O)/PW7 (Output) P16 (I/O)/PW6 (Output) P15 (I/O)/PW5 (Output) P14 (I/O)/PW4 (Output) P13 (I/O)/PW3 (Output) P12 (I/O)/PW2 (Output) P11 (I/O)/PW1 (Output) P10 (I/O)/PW0 (Output) Figure 8.1 Port 1 Pin Functions 190 8.2.2 Register Configuration Table 8.3 shows the port 1 register configuration. Table 8.3 Name Port 1 data direction register Port 1 data register Port 1 MOS pull-up control register Port 1 Registers Abbreviation P1DDR P1DR P1PCR R/W W R/W R/W Initial Value H'00 H'00 H'00 Address* H'FFB0 H'FFB2 H'FFAC Note: * Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR) Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be returned. P1DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. The address output pins maintain their output state in a transition to software standby mode. * Mode 1 The corresponding port 1 pins are address outputs, regardless of the P1DDR setting. In hardware standby mode, the address outputs go to the high-impedance state. * Modes 2 and 3 (EXPE = 1) The corresponding port 1 pins are address outputs or PWM outputs when P1DDR bits are set to 1, and input ports when cleared to 0. * Modes 2 and 3 (EXPE = 0) The corresponding port 1 pins are output ports or PWM outputs when P1DDR bits are set to 1, and input ports when cleared to 0. 191 Port 1 Data Register (P1DR) Bit Initial value R/W 7 P17DR 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read, regardless of the actual pin states. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. P1DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 1 MOS Pull-Up Control Register (P1PCR) Bit Initial value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR P1PCR is an 8-bit readable/writable register that controls the port 1 built-in MOS input pull-ups on a bit-by-bit basis. In modes 2 and 3, the MOS input pull-up is turned on when a P1PCR bit is set to 1 while the corresponding P1DDR bit is cleared to 0 (input port setting). P1PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 192 8.2.3 Pin Functions in Each Mode Mode 1: In mode 1, port 1 pins automatically function as address outputs. The port 1 pin functions are shown in figure 8.2. A7 (Output) A6 (Output) A5 (Output) Port 1 A4 (Output) A3 (Output) A2 (Output) A1 (Output) A0 (Output) Figure 8.2 Port 1 Pin Functions (Mode 1) Modes 2 and 3 (EXPE = 1): In modes 2 and 3 (when EXPE = 1), port 1 pins function as address outputs, PWM outputs, or input ports, and input or output can be specified on a bit-by-bit basis. When a bit in P1DDR is set to 1, the corresponding pin functions as an address output or PWM output, and when cleared to 0, as an input port. The port 1 pin functions are shown in figure 8.3. When P1DDR = 1 and PWOERA = 0 A7 (Output) A6 (Output) A5 (Output) Port 1 A4 (Output) A3 (Output) A2 (Output) A1 (Output) A0 (Output) When P1DDR = 1 and PWOERA = 1 PW7 (Output) PW6 (Output) PW5 (Output) PW4 (Output) PW3 (Output) PW2 (Output) PW1 (Output) PW0 (Output) When P1DDR = 0 P17 (Input) P16 (Input) P15 (Input) P14 (Input) P13 (Input) P12 (Input) P11 (Input) P10 (Input) Figure 8.3 Port 1 Pin Functions (Modes 2 and 3 (EXPE = 1)) 193 Modes 2 and 3 (EXPE = 0): In modes 2 and 3 (when EXPE = 0), port 1 pins function as PWM outputs or I/O ports, and input or output can be specified on a bit-by-bit basis. When a bit in P1DDR is set to 1, the corresponding pin functions as a PWM output or output port, and when cleared to 0, as an input port. The port 1 pin functions are shown in figure 8.4. P1n: Input pin when P1DDR = 0, output pin when P1DDR = 1 and PWOERA = 0 P17 (I/O) P16 (I/O) P15 (I/O) Port 1 P14 (I/O) P13 (I/O) P12 (I/O) P11 (I/O) P10 (I/O) When P1DDR = 1 and PWOERA = 1 PW7 (Output) PW6 (Output) PW5 (Output) PW4 (Output) PW3 (Output) PW2 (Output) PW1 (Output) PW0 (Output) Figure 8.4 Port 1 Pin Functions (Modes 2 and 3 (EXPE = 0)) 194 8.2.4 MOS Input Pull-Up Function Port 1 has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bitby-bit basis. When a P1DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P1PCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.4 summarizes the MOS input pull-up states. Table 8.4 Mode 1 2, 3 MOS Input Pull-Up States (Port 1) Reset Off Off Hardware Standby Mode Off Off Software Standby Mode Off On/Off In Other Operations Off On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off. 8.3 8.3.1 Port 2 Overview Port 2 is an 8-bit I/O port. Port 2 pins also function as address bus output pins (A15 to A8), 8-bit PWM output pins (PW15 to PW8) (H8S/2138 Series only), and the timer connection output pin (CBLANK) (H8S/2138 Series only). Port 2 functions change according to the operating mode. Port 2 has a built-in MOS input pull-up function that can be controlled by software. Figure 8.5 shows the port 2 pin configuration. 195 Port 2 pins P27/A15/PW15/CBLANK P26/A14/PW14 P25/A13/PW13 Port 2 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 Pin functions in mode 1 A15 (Output) A14 (Output) A13 (Output) A12 (Output) A11 (Output) A10 (Output) A9 (Output) A8 (Output) Pin functions in modes 2 and 3 (EXPE = 1) A15 (Output)/P27 (I/O)/PW15 (Output)/CBLANK (Output) A14 (Output)/P26 (I/O)/PW14 (Output) A13 (Output)/P25 (I/O)/PW13 (Output) A12 (Output)/P24 (I/O)/PW12 (Output) A11 (Output)/P23 (Input)/PW11 (Output) A10 (Output)/P22 (Input)/PW10 (Output) A9 (Output)/P21 (Input)/PW9 (Output) A8 (Output)/P20 (Input)/PW8 (Output) Pin functions in modes 2 and 3 (EXPE = 0) P27 (I/O)/PW15 (Output)/CBLANK (Output) P26 (I/O)/PW14 (Output) P25 (I/O)/PW13 (Output) P24 (I/O)/PW12 (Output) P23 (I/O)/PW11 (Output) P22 (I/O)/PW10 (Output) P21 (I/O)/PW9 (Output) P20 (I/O)/PW8 (Output) Figure 8.5 Port 2 Pin Functions 196 8.3.2 Register Configuration Table 8.5 shows the port 2 register configuration. Table 8.5 Name Port 2 data direction register Port 2 data register Port 2 MOS pull-up control register Port 2 Registers Abbreviation P2DDR P2DR P2PCR R/W W R/W R/W Initial Value H'00 H'00 H'00 Address* H'FFB1 H'FFB3 H'FFAD Note: * Lower 16 bits of the address. Port 2 Data Direction Register (P2DDR) Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be returned. P2DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. The address output pins maintain their output state in a transition to software standby mode. * Mode 1 The corresponding port 2 pins are address outputs, regardless of the P2DDR setting. In hardware standby mode, the address outputs go to the high-impedance state. * Modes 2 and 3 (EXPE = 1) The corresponding port 2 pins are address outputs or PWM outputs when P2DDR bits are set to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output ports by setting the IOSE bit to 1. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting, but to ensure normal access to external space, P27 should not be set as an on-chip supporting module output pin when port 2 pins are used as address output pins. 197 * Modes 2 and 3 (EXPE = 0) The corresponding port 2 pins are output ports or PWM outputs when P2DDR bits are set to 1, and input ports when cleared to 0. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting. Port 2 Data Register (P2DR) Bit Initial value R/W 7 P27DR 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20). If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly, regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. P2DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 2 MOS Pull-Up Control Register (P2PCR) Bit Initial value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR P2PCR is an 8-bit readable/writable register that controls the port 2 built-in MOS input pull-ups on a bit-by-bit basis. In modes 2 and 3, the MOS input pull-up is turned on when a P2PCR bit is set to 1 while the corresponding P2DDR bit is cleared to 0 (input port setting). P2PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 198 8.3.3 Pin Functions in Each Mode Mode 1: In mode 1, port 2 pins automatically function as address outputs. The port 2 pin functions are shown in figure 8.6. A15 (Output) A14 (Output) A13 (Output) Port 2 A12 (Output) A11 (Output) A10 (Output) A9 (Output) A8 (Output) Figure 8.6 Port 2 Pin Functions (Mode 1) Modes 2 and 3 (EXPE = 1): In modes 2 and 3 (when EXPE = 1), port 2 pins function as address outputs, PWM outputs, or I/O ports, and input or output can be specified on a bit-by-bit basis. When a bit in P2DDR is set to 1, the corresponding pin functions as an address output or PWM output, and when cleared to 0, as an input port. P27 to P24 are switched from address outputs to output ports by setting the IOSE bit to 1. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting, but to ensure normal access to external space, P27 should not be set as an on-chip supporting module output pin when port 2 pins are used as address output pins. The port 2 pin functions are shown in figure 8.7. When P2DDR = 1 and PWOERB = 0 When P2DDR = 1 and PWOERB = 1 When P2DDR = 0 A15 (Output)/P27 (Output) P27 (Input)/CBLANK (Output) PW15 (Output)/CBLANK (Output) A14 (Output)/P26 (Output) P26 (Input) A13 (Output)/P25 (Output) P25 (Input) Port 2 A12 (Output)/P24 (Output) P24 (Input) A11 (Output) A10 (Output) A9 (Output) A8 (Output) P23 (Input) P22 (Input) P21 (Input) P20 (Input) PW14 (Output) PW13 (Output) PW12 (Output) PW11 (Output) PW10 (Output) PW9 (Output) PW8 (Output) Figure 8.7 Port 2 Pin Functions (Modes 2 and 3 (EXPE = 1)) 199 Modes 2 and 3 (EXPE = 0): In modes 2 and 3 (when EXPE = 0), port 2 pins function as PWM outputs (P27 can also function as the timer connection output (CBLANK)) or I/O ports, and input or output can be specified on a bit-by-bit basis. When a bit in P2DDR is set to 1, the corresponding pin functions as a PWM output or output port, and when cleared to 0, as an input port. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting. The port 2 pin functions are shown in figure 8.8. P2n: Input pin when P2DDR = 0, output pin when P2DDR = 1 and PWOERB = 0 P27 (I/O)/CBLANK (Output) P26 (I/O) P25 (I/O) Port 2 P24 (I/O) P23 (I/O) P22 (I/O) P21 (I/O) P20 (I/O) When P2DDR = 1 and PWOERB = 1 PW15 (Output)/CBLANK (Output) PW14 (Output) PW13 (Output) PW12 (Output) PW11 (Output) PW10 (Output) PW9 (Output) PW8 (Output) Figure 8.8 Port 2 Pin Functions (Modes 2 and 3 (EXPE = 0)) 200 8.3.4 MOS Input Pull-Up Function Port 2 has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bitby-bit basis. When a P2DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P2PCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.6 summarizes the MOS input pull-up states. Table 8.6 Mode 1 2, 3 MOS Input Pull-Up States (Port 2) Reset Off Off Hardware Standby Mode Off Off Software Standby Mode Off On/Off In Other Operations Off On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off. 201 8.4 8.4.1 Port 3 Overview Port 3 is an 8-bit I/O port. Port 3 pins also function as host data bus I/O pins (HDB7 to HDB0) (H8S/2138 Series only), and as data bus I/O pins. Port 3 functions change according to the operating mode. Port 3 has a built-in MOS input pull-up function that can be controlled by software. Figure 8.9 shows the port 3 pin configuration. Port 3 pins P37/D7/HDB7 P36/D6/HDB6 P35/D5/HDB5 Port 3 P34/D4/HDB4 P33/D3/HDB3 P32/D2/HDB2 P31/D1/HDB1 P30/D0/HDB0 Pin functions in modes 1, 2 and 3 (EXPE = 1) D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) Pin functions in modes 2 and 3 (EXPE = 0) P37 (I/O)/HDB7 (I/O) P36 (I/O)/HDB6 (I/O) P35 (I/O)/HDB5 (I/O) P34 (I/O)/HDB4 (I/O) P33 (I/O)/HDB3 (I/O) P32 (I/O)/HDB2 (I/O) P31 (I/O)/HDB1 (I/O) P30 (I/O)/HDB0 (I/O) Figure 8.9 Port 3 Pin Functions 202 8.4.2 Register Configuration Table 8.7 shows the port 3 register configuration. Table 8.7 Name Port 3 data direction register Port 3 data register Port 3 MOS pull-up control register Port 3 Registers Abbreviation P3DDR P3DR P3PCR R/W W R/W R/W Initial Value H'00 H'00 H'00 Address* H'FFB4 H'FFB6 H'FFAE Note: * Lower 16 bits of the address. Port 3 Data Direction Register (P3DDR) Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be returned. P3DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. * Modes 1, 2, and 3 (EXPE = 1) The input/output direction specified by P3DDR is ignored, and pins automatically function as data I/O pins. After a reset, and in hardware standby mode or software standby mode, the data I/O pins go to the high-impedance state. * Modes 2 and 3 (EXPE = 0) The corresponding port 3 pins are output ports when P3DDR bits are set to 1, and input ports when cleared to 0. 203 Port 3 Data Register (P3DR) Bit Initial value Read/Write 7 P37DR 0 R/W 6 P36DR 0 R/W 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P37 to P30). If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly, regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. P3DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 3 MOS Pull-Up Control Register (P3PCR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR P3PCR is an 8-bit readable/writable register that controls the port 3 built-in MOS input pull-ups on a bit-by-bit basis. In modes 2 and 3 (when EXPE = 0), the MOS input pull-up is turned on when a P3PCR bit is set to 1 while the corresponding P3DDR bit is cleared to 0 (input port setting). P3PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. The MOS input pull-up function cannot be used in slave mode (when the host interface is enabled). 204 8.4.3 Pin Functions in Each Mode Modes 1, 2, and 3 (EXPE = 1): In modes 1, 2, and 3 (when EXPE = 1), port 3 pins automatically function as data I/O pins. The port 3 pin functions are shown in figure 8.10. D7 (I/O) D6 (I/O) D5 (I/O) Port 3 D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) Figure 8.10 Port 3 Pin Functions (Modes 1, 2, and 3 (EXPE = 1)) Modes 2 and 3 (EXPE = 0): In modes 2 and 3 (when EXPE = 0), port 3 functions as host interface data bus I/O pins (HDB7 to HDB0) or as I/O ports. When the HI12E bit is set to 1 in SYSCR2 and a transition is made to slave mode, port 3 functions as the host interface data bus. In slave mode, P3DR and P3DDR should be cleared to H'00. When the HI12E bit is cleared to 0, port 3 functions as an I/O port, and input or output can be specified on a bit-by-bit basis. When a bit in P3DDR is set to 1, the corresponding pin functions as an output port, and when cleared to 0, as an input port. The port 3 pin functions are shown in figure 8.11. P37 (I/O)/HDB7 (I/O) P36 (I/O)/HDB6 (I/O) P35 (I/O)/HDB5 (I/O) Port 3 P34 (I/O)/HDB4 (I/O) P33 (I/O)/HDB3 (I/O) P32 (I/O)/HDB2 (I/O) P31 (I/O)/HDB1 (I/O) P30 (I/O)/HDB0 (I/O) Figure 8.11 Port 3 Pin Functions (Modes 2 and 3 (EXPE = 0)) 205 8.4.4 MOS Input Pull-Up Function Port 3 has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2 and 3 (when EXPE = 0), and can be specified as on or off on a bit-by-bit basis. When a P3DDR bit is cleared to 0 in mode 2 or 3 (when EXPE = 0), setting the corresponding P3PCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.8 summarizes the MOS input pull-up states. Table 8.8 Mode MOS Input Pull-Up States (Port 3) Reset Hardware Standby Mode Off Off Software Standby Mode Off On/Off In Other Operations Off On/Off 1, 2, 3 (EXPE = 1) Off 2, 3 (EXPE = 0) Off Legend: Off: MOS input pull-up is always off. On/Off: On when P3DDR = 0 and P3PCR = 1; otherwise off. 206 8.5 8.5.1 Port 4 Overview Port 4 is an 8-bit I/O port. Port 4 pins also function as 14-bit PWM output pins (PWX1, PWX0), 8-bit timer 0 and 1 (TMR0, TMR1) I/O pins (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection I/O pins (CSYNCI, HSYNCI, HSYNCO) (H8S/2138 Series only), SCI2 I/O pins (TxD2, RxD2, SCK2), IrDA interface I/O pins (IrTxD, IrRxD), host interface output pins (HIRQ12, HIRQ1, HIRQ11) (H8S/2138 Series only), and the IIC1 I/O pin (SDA1) (option in H8S/2138 Series only). Port 4 pin functions are the same in all operating modes. Figure 8.12 shows the port 4 pin configuration. Port 4 pins P47 (I/O)/PWX1 (Output) P46 (I/O)/PWX0 (Output) P45 (I/O)/TMRI1 (Input)/HIRQ12 (Output)/CSYNCI (Input) Port 4 P44 (I/O)/TMO1 (Output)/HIRQ1 (Output)/HSYNCO (Output) P43 (I/O)/TMCI1 (Input)/HIRQ11 (Output)/HCYNCI (Input) P42 (I/O)/TMRI0 (Input)/SCK2 (I/O)/SDA1 (I/O) P41 (I/O)/TMO0 (Output)/RxD2 (Input)/IrRxD (Input) P40 (I/O)/TMCI0 (Input)/TxD2 (Output)/IrTxD (Output) Figure 8.12 Port 4 Pin Functions 8.5.2 Register Configuration Table 8.9 shows the port 4 register configuration. Table 8.9 Name Port 4 data direction register Port 4 data register Port 4 Registers Abbreviation P4DDR P4DR R/W W R/W Initial Value H'00 H'00 Address* H'FFB5 H'FFB7 Note: * Lower 16 bits of the address. 207 Port 4 Data Direction Register (P4DDR) Bit 7 6 5 4 3 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W P4DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 4. P4DDR cannot be read; if it is, an undefined value will be returned. When a bit in P4DDR is set to 1, the corresponding pin functions as an output port, and when cleared to 0, as an input port. P4DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. As 14-bit PWM and SCI2 are initialized in software standby mode, the pin states are determined by the TMR0, TMR1, HIF, IIC1, P4DDR, and P4DR specifications. Port 4 Data Register (P4DR) Bit Initial value Read/Write 7 P47DR 0 R/W 6 P46DR 0 R/W 5 P45DR 0 R/W 4 P44DR 0 R/W 3 P43DR 0 R/W 2 P42DR 0 R/W 1 P41DR 0 R/W 0 P40DR 0 R/W P4DR is an 8-bit readable/writable register that stores output data for the port 4 pins (P47 to P40). If a port 4 read is performed while P4DDR bits are set to 1, the P4DR values are read directly, regardless of the actual pin states. If a port 4 read is performed while P4DDR bits are cleared to 0, the pin states are read. P4DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 208 8.5.3 Pin Functions Port 4 pins also function as 14-bit PWM output pins (PWX1, PWX0), 8-bit timer 0 and 1 (TMR0, TMR1) I/O pins (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection I/O pins (CSYNCI, HSYNCI, HSYNCO), SCI2 I/O pins (TxD2, RxD2, SCK2), IrDA interface I/O pins (IrTxD, IrRxD), host interface output pins (HIRQ12, HIRQ1, HIRQ11), and the IIC1 I/O pin (SDA1). The port 4 pin functions are shown in table 8.10. Table 8.10 Port 4 Pin Functions Pin P47/PWX1 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit OEB in DACR of 14-bit PWM, and bit P47DDR. OEB P47DDR Pin function P46/PWX0 0 P47 input pin 0 1 P47 output pin 1 -- PWX1 output pin The pin function is switched as shown below according to the combination of bit OEA in DACR of 14-bit PWM, and bit P46DDR. OEA P46DDR Pin function 0 P46 input pin 0 1 P46 output pin 1 -- PWX0 output pin P45/TMRI1/ HIRQ12/CSYNCI The pin function is switched as shown below according to the combination of the operating mode and bit P45DDR. P45DDR Operating mode Pin function 0 -- P45 input pin Not slave mode P45 output pin 1 Slave mode HIRQ12 output pin TMRI1 input pin, CSYNCI input pin When bits CCLR1 and CCLR0 in TCR1 of TMR1 are set to 1, this pin is used as the TMRI1 input pin. It can also be used as the CSYNCI input pin. P44/TMO1/ HIRQ1/HSYNCO The pin function is switched as shown below according to the combination of the operating mode, bits OS3 to OS0 in TCSR of TMR1, bit HOE in TCONRO of the timer connection function, and bit P44DDR. HOE OS3 to OS0 P44DDR Operating mode Pin function 0 -- P44 input pin Not slave mode P44 output pin All 0 1 Slave mode 0 Not all 0 -- -- 1 -- -- -- HSYNCO output pin HIRQ1 output TMO1 output pin pin 209 Table 8.10 Port 4 Pin Functions (cont) Pin P43/TMCI1/ HIRQ11/HSYNCI Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode and bit P43DDR. P43DDR Operating mode Pin function 0 -- P43 input pin Not slave mode P43 output pin 1 Slave mode HIRQ11 output pin TMCI1 input pin, HSYNCI input pin When an external clock is selected with bits CKS2 to CKS0 in TCR1 of TMR1, this pin is used as the TMCI1 input pin. It can also be used as the HSYNCI input pin. P42/TMRI0/ SCK2/SDA1 The pin function is switched as shown below according to the combination of bit ICE in ICCR of IIC1, bits CKE1 and CKE0 in SCR of SCI2, bit C/$ in SMR of SCI2, and bit P42DDR. ICE CKE1 C/$ CKE0 P42DDR Pin function 0 0 1 0 1 -- 0 1 -- -- 0 1 -- -- -- 1 0 0 0 -- SDA1 I/O pin P42 P42 SCK2 SCK2 SCK2 input pin output pin output pin output pin input pin TMRI0 input pin When this pin is used as the SDA1 I/O pin, bits CKE1 and CKE0 in SCR of SCI2 and bit C/$ in SMR of SCI2 must all be cleared to 0. SDA1 is an NMOSonly output, and has direct bus drive capability. When bits CCLR1 and CCLR0 in TCR0 of TMR0 are set to 1, this pin is used as the TMRI0 input pin. 210 Table 8.10 Port 4 Pin Functions (cont) Pin Selection Method and Pin Functions P41/TMO0/RxD2/ The pin function is switched as shown below according to the combination of IrRxD bits OS3 to OS0 in TCSR of TMR0, bit RE in SCR of SCI2 and bit P41DDR. OS3 to OS0 RE P41DDR Pin function 0 P41 input pin 0 1 P41 output pin All 0 1 -- RxD2/IrRxD input pin Not all 0 0 -- TMO0 output pin When this pin is used as the TMO0 output pin, bit RE in SCR of SCI2 must be cleared to 0. P40/TMCI0/TxD2/ The pin function is switched as shown below according to the combination of IrTxD bit TE in SCR of SCI2 and bit P40DDR. TE P40DDR Pin function 0 P40 input pin 0 1 P40 output pin TMCI0 input pin When an external clock is selected with bits CKS2 to CKS0 in TCR0 of TMR0, this pin is used as the TMCI0 input pin. 1 -- TxD2/IrTxD output pin 211 8.6 8.6.1 Port 5 Overview Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0), and the IIC0 I/O pin (SCL0) (option in H8S/2138 Series only). In the H8S/2138 Series, P52 and SCK0 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output. Port 5 pin functions are the same in all operating modes. Figure 8.13 shows the port 5 pin configuration. Port 5 pins P52 (I/O)/SCK0 (I/O)/SCL0 (I/O) Port 5 P51 (I/O)/RxD0 (Input) P50 (I/O)/TxD0 (Output) Figure 8.13 Port 5 Pin Functions 8.6.2 Register Configuration Table 8.11 shows the port 5 register configuration. Table 8.11 Port 5 Registers Name Port 5 data direction register Port 5 data register Abbreviation P5DDR P5DR R/W W R/W Initial Value H'F8 H'F8 Address* H'FFB8 H'FFBA Note: * Lower 16 bits of the address. 212 Port 5 Data Direction Register (P5DDR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 0 W 1 0 W 0 0 W P52DDR P51DDR P50DDR P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be returned. Bits 7 to 3 are reserved. Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P5DDR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in software standby mode. As SCI0 is initialized, the pin states are determined by the IIC0 ICCR, P5DDR, and P5DR specifications. Port 5 Data Register (P5DR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 P52DR 0 R/W 1 P51DR 0 R/W 0 P50DR 0 R/W P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P52 to P50). If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly, regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. Bits 7 to 3 are reserved; they cannot be modified and are always read as 1. P5DR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 213 8.6.3 Pin Functions Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0) and the IIC0 I/O pin (SCL0). The port 5 pin functions are shown in table 8.12. Table 8.12 Port 5 Pin Functions Pin P52/SCK0/SCL0 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bits CKE1 and CKE0 in SCR of SCI0, bit C/$ in SMR of SCI0, bit ICE in ICCR of IIC0, and bit P52DDR. ICE CKE1 C/$ CKE0 P52DDR Pin function 0 0 1 0 1 -- 0 1 -- -- 0 1 -- -- -- 1 0 0 0 -- SCL0 I/O pin P52 P52 SCK0 SCK0 SCK0 input pin output pin output pin output pin input pin When this pin is used as the SCL0 I/O pin, bits CKE1 and CKE0 in SCR of SCI0 and bit C/$ in SMR of SCI0 must all be cleared to 0. SCL0 is an NMOS open-drain output, and has direct bus drive capability. In the H8S/2138 Series, when set as the P52 output pin or SCK0 output pin, this pin is an NMOS push-pull output. P51/RxD0 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI0 and bit P51DDR. RE P51DDR Pin function P50/TxD0 0 P51 input pin 0 1 P51 output pin 1 -- RxD0 input pin The pin function is switched as shown below according to the combination of bit TE in SCR of SCI0 and bit P50DDR. TE P50DDR Pin function 0 P50 input pin 0 1 P50 output pin 1 -- TxD0 output pin 214 8.7 8.7.1 Port 6 Overview Port 6 is an 8-bit I/O port. Port 6 pins also function as the 16-bit free-running timer (FRT) I/O pins (FTOA, FTOB, FTIA to FTID, FTCI), timer X (TMRX) I/O pins (TMOX, TMIX) (H8S/2138 Series only), the timer Y (TMRY) input pin (TMIY), timer connection I/O pins (HFBACKI, VSYNCI, VSYNCO, VFBACKI, CLAMPO) (H8S/2138 Series only), key-sense interrupt input pins (.,1 to .,1), expansion A/D converter input pins (CIN7 to CIN0), and external interrupt input pins (,54, ,54). In the H8S/2138 Series, the port 6 input level can be switched in four stages. Port 6 pin functions are the same in all operating modes. Figure 8.14 shows the port 6 pin configuration. Port 6 pins P67 (I/O)/TMOX (Output)/KIN7 (Input)/CIN7 (Input)/IRQ7 (Input) P66 (I/O)/FTOB (Output)/KIN6 (Input)/CIN6 (Input)/IRQ6 (Input) P65 (I/O)/FTID (Input)/KIN5 (Input)/CIN5 (Input) Port 6 P64 (I/O)/FTIC (Input)/KIN4 (Input)/CIN4 (Input)/CLAMPO (Output) P63 (I/O)/FTIB (Input)/KIN3 (Input)/CIN3 (Input)/VFBACKI (Input) P62 (I/O)/FTIA (Input)/KIN2 (Input)/CIN2 (Input)/VSYNCI (Input)/TMIY (Input) P61 (I/O)/FTOA (Output)/KIN1 (Input)/CIN1 (Input)/VSYNCO (Output) P60 (I/O)/FTCI (Input)/KIN0 (Input)/CIN0 (Input)/HFBACKI (Input)/TMIX (Input) Figure 8.14 Port 6 Pin Functions 215 8.7.2 Register Configuration Table 8.13 shows the port 6 register configuration. Table 8.13 Port 6 Registers Name Port 6 data direction register Port 6 data register Abbreviation R/W P6DDR P6DR W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address*1 H'FFB9 H'FFBB H'FFF2* H'FF83 2 Port 6 MOS pull-up control register KMPCR System control register 2 SYSCR2 Notes: 1. Lower 16 bits of the address. 2. KMPCR has the same address as TICRR/TCORAY of TMRX/TMRY. To select KMPCR, set the HIF bit to 1 in SYSCR and clear the MSTP2 bit to 0 in MSTPCRL. Port 6 Data Direction Register (P6DDR) Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be returned. Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P6DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 216 Port 6 Data Register (P6DR) Bit Initial value Read/Write 7 P67DR 0 R/W 6 P66DR 0 R/W 5 P65DR 0 R/W 4 P64DR 0 R/W 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0 P60DR 0 R/W P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60). If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly, regardless of the actual pin states. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. P6DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 6 MOS Pull-Up Control Register (KMPCR) Bit 7 6 5 4 3 2 1 0 KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W KMPCR is an 8-bit readable/writable register that controls the port 6 built-in MOS input pullups on a bit-by-bit basis. The MOS input pull-up is turned on when a KMPCR bit is set to 1 while the corresponding P6DDR bit is cleared to 0 (input port setting). KMPCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 217 System Control Register 2 (SYSCR2) [H8S/2138 Series Only] Bit 7 6 5 P6PUE 0 R/W 4 -- 0 -- 3 SDE 0 R/W 2 CS4E 0 R/W 1 CS3E 0 R/W 0 HI12E 0 R/W KWUL1 KWUL0 Initial value Read/Write 0 R/W 0 R/W SYSCR2 is an 8-bit readable/writable register that controls port 6 input level selection and the operation of host interface functions. Only bits 7, 6, and 5 are described here. See section 17.2.2, System Control Register 2 (SYSCR2), for information on bits 4 to 0. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6--Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level setting can be changed by software, using these bits. The setting of these bits also changes the input level of the pin functions multiplexed with port 6. Bit 7 KWUL1 0 Bit 6 KWUL0 0 1 1 0 1 Description Standard input level is selected as port 6 input level Input level 1 is selected as port 6 input level Input level 2 is selected as port 6 input level Input level 3 is selected as port 6 input level (Initial value) Bit 5--Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for the port 6 MOS input pull-up function connected by means of KMPCR settings. Bit 5 P6PUE 0 1 Description Standard current specification is selected for port 6 MOS input pull-up function (Initial value) Current-limit specification is selected for port 6 MOS input pull-up function 218 8.7.3 Pin Functions Port 6 pins also function as the 16-bit free-running timer (FRT) I/O pins (FTOA, FTOB, FTIA to FTID, FTCI), timer X (TMRX) I/O pins (TMOX, TMIX), the timer Y (TMRY) input pin (TMIY), timer connection I/O pins (HFBACKI, VSYNCI, VSYNCO, VFBACKI, CLAMPO), key-sense interrupt input pins (.,1to .,1), expansion A/D converter input pins (CIN7 to CIN0), and external interrupt input pins (,54, ,54). In the H8S/2138 Series, the port 6 input level can be switched in four stages. The port 6 pin functions are shown in table 8.14. Table 8.14 Port 6 Pin Functions Pin Selection Method and Pin Functions .,1/CIN7 P67/TMOX/,54/ The pin function is switched as shown below according to the combination of bits OS3 to OS0 in TCSR of TMRX and bit P67DDR. OS3 to OS0 P67DDR Pin function 0 P67 input pin All 0 1 P67 output pin Not all 0 -- TMOX output pin ,54 input pin, .,1 input pin, CIN7 input pin This pin is used as the ,54 input pin when bit IRQ7E is set to 1 in IER. It can always be used as the .,1 or CIN7 input pin. P66/FTOB/,54/ The pin function is switched as shown below according to the combination of bit OEB in TOCR of the FRT and bit P66DDR. OEB P66DDR Pin function 0 P66 input pin 0 1 P66 output pin 1 -- FTOB output pin .,1/CIN6 ,54 input pin, .,1 input pin, CIN6 input pin This pin is used as the ,54 input pin when bit IRQ6E is set to 1 in IER. It can always be used as the .,1 or CIN6 input pin. P65/FTID/.,1/ CIN5 P65DDR Pin function 0 P65 input pin 1 P65 output pin FTID input pin, .,1 input pin, CIN5 input pin This pin can always be used as the FTID, .,1, or CIN5 input pin. 219 Table 8.14 Port 6 Pin Functions (cont) Pin P64/FTIC/.,1/ CIN4/CLAMPO Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit CLOE in TCONRO of the timer connection function and bit P64DDR. CLOE P64DDR Pin function 0 P64 input pin 0 1 P64 output pin 1 -- CLAMPO output pin FTIC input pin, .,1 input pin, CIN4 input pin This pin can always be used as the FTIC, .,1, or CIN4 input pin. P63/FTIB/.,1/ CIN3/VFBACKI P63DDR Pin function 0 P63 input pin 1 P63 output pin FTIB input pin, VFBACKI input pin, .,1 input pin, CIN3 input pin This pin can always be used as the FTIB, .,1, CIN3, or VFBACKI input pin. P62/FTIA/TMIY/ P62DDR Pin function 0 P62 input pin 1 P62 output pin .,1/CIN2/ VSYNCI FTIA input pin, VSYNCI input pin, TMIY input pin, .,1 input pin, CIN2 input pin This pin can always be used as the FTIA, TMIY, .,1, CIN2, or VSYNCI input pin. P61/FTOA/.,1/ CIN1/VSYNCO The pin function is switched as shown below according to the combination of bit OEA in TOCR of the FRT, bit VOE in TCONRO of the timer connection function, and bit P61DDR. VOE OEA P61DDR Pin function 0 P61 input pin 0 1 P61 output pin 0 1 -- FTOA output pin 1 0 -- VSYNCO output pin .,1 input pin, CIN1 input pin When this pin is used as the VSYNCO pin, bit OEA in TOCR of the FRT must be cleared to 0. This pin can always be used as the .,1 or CIN1 input pin. 220 Table 8.14 Port 6 Pin Functions (cont) Pin P60/FTCI/TMIX/ Selection Method and Pin Functions P60DDR Pin function 0 P60 input pin 1 P60 output pin .,1/CIN0/ HFBACKI FTCI input pin, HFBACKI input pin, TMIX input pin, .,1 input pin, CIN0 input pin This pin is used as the FTCI input pin when an external clock is selected with bits CKS1 and CKS0 in TCR of the FRT. It can always be used as the TMIX, .,1, CIN0, or HFBACKI input pin. 8.7.4 MOS Input Pull-Up Function Port 6 has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis. When a P6DDR bit is cleared to 0, setting the corresponding KMPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up current specification can be changed by means of the P6PUE bit. When a pin is designated as an on-chip supporting module output pin, the MOS input pull-up is always off. The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.15 summarizes the MOS input pull-up states. Table 8.15 MOS Input Pull-Up States (Port 6) Mode 1, 2, 3 Reset Off Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: MOS input pull-up is always off. On/Off: On when P6DDR = 0 and KMPCR = 1; otherwise off. 221 8.8 8.8.1 Port 7 Overview Port 7 is an 8-bit input port. Port 7 pins also function as the A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0, DA1). Port 7 functions are the same in all operating modes. Figure 8.15 shows the port 7 pin configuration. Port 7 pins P77 (Input)/AN7 (Input)/DA1 (Output) P76 (Input)/AN6 (Input)/DA0 (Output) P75 (Input)/AN5 (Input) Port 7 P74 (Input)/AN4 (Input) P73 (Input)/AN3 (Input) P72 (Input)/AN2 (Input) P71 (Input)/AN1 (Input) P70 (Input)/AN0 (Input) Figure 8.15 Port 7 Pin Functions 8.8.2 Register Configuration Table 8.16 shows the port 7 register configuration. Port 7 is an input-only port, and does not have a data direction register or data register. Table 8.16 Port 7 Registers Name Port 7 input data register Abbreviation P7PIN R/W R Initial Value Undefined Address* H'FFBE Note: * Lower 16 bits of the address. 222 Port 7 Input Data Register (P7PIN) Bit Initial value Read/Write 7 P77PIN --* R 6 --* R 5 --* R 4 --* R 3 --* R 2 --* R 1 --* R 0 --* R P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN Note: * Determined by the state of pins P77 to P70. When a P7PIN read is performed, the pin states are always read. 8.8.3 Pin Functions Port 7 pins also function as the A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0, DA1). 8.9 8.9.1 Port 8 Overview Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI1 I/O pins (TxD1, RxD1, SCK1), the IIC1 I/O pin (SCL1) (option in H8S/2138 Series only), HIF I/O pins (&6, GA20, HA0, HIFSD) (H8S/2138 Series only), and external interrupt input pins (,54 to ,54). Port 8 pin functions are the same in all operating modes. Figure 8.16 shows the port 8 pin configuration. Port 8 pins P86 (I/O)/IRQ5 (Input)/SCK1 (I/O)/SCL1 (I/O) P85 (I/O)/IRQ4 (Input)/RxD1 (Input) P84 (I/O)/IRQ3 (Input)/TxD1 (Output) Port 8 P83 (I/O) P82 (I/O)/HIFSD (Input) P81 (I/O)/CS2 (Input)/GA20 (Output) P80 (I/O)/HA0 (Input) Figure 8.16 Port 8 Pin Functions 223 8.9.2 Register Configuration Table 8.17 summarizes the port 8 registers. Table 8.17 Port 8 Registers Name Port 8 data direction register Port 8 data register Abbreviation P8DDR P8DR R/W W R/W Initial Value H'80 H'80 Address* H'FFBD H'FFBF Note: * Lower 16 bits of the address. Port 8 Data Direction Register (P8DDR) Bit 7 -- Initial value Read/Write 1 -- 6 5 4 3 2 1 0 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W P8DDR is a 7-bit write-only register, the individual bits of which specify input or output for the pins of port 8. Setting a P8DDR bit to 1 makes the corresponding port 8 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P8DDR is initialized to H'80 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 8 Data Register (P8DR) Bit 7 -- Initial value Read/Write 1 -- 6 P86DR 0 R/W 5 P85DR 0 R/W 4 P84DR 0 R/W 3 P83DR 0 R/W 2 P82DR 0 R/W 1 P81DR 0 R/W 0 P80DR 0 R/W P8DR is a 7-bit readable/writable register that stores output data for the port 8 pins (P86 to P80). If a port 8 read is performed while P8DDR bits are set to 1, the P8DR values are read directly, regardless of the actual pin states. If a port 8 read is performed while P8DDR bits are cleared to 0, the pin states are read. P8DR is initialized to H'80 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 224 8.9.3 Pin Functions Port 8 pins also function as SCI1 I/O pins (TxD1, RxD1, SCK1), the IIC1 I/O pin (SCL1), HIF I/O pins (&6, GA20, HA0, HIFSD), and external interrupt input pins (,54 to ,54). The port 8 pin functions are shown in table 8.18. Table 8.18 Port 8 Pin Functions Pin P86/,54/SCK1/ SCL1 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bits CKE1 and CKE0 in SCR of SCI1, bit C/$ in SMR of SCI1, bit ICE in ICCR of IIC1, and bit P86DDR. ICE CKE1 C/$ CKE0 P86DDR Pin function 0 0 1 0 1 -- 0 1 -- -- 0 1 -- -- -- 1 0 0 0 -- SCL1 I/O pin P86 P86 SCK1 SCK1 SCK1 input pin output pin output pin output pin input pin ,54 input pin When the IRQ5E bit in IER is set to 1, this pin is used as the ,54 input pin. When this pin is used as the SCL1 I/O pin, bits CKE1 and CKE0 in SCR of SCI1 and bit C/$ in SMR of SCI1 must all be cleared to 0. SCL1 is an NMOSonly output, and has direct bus drive capability. P85/,54/RxD1 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI1 and bit P85DDR. RE P85DDR Pin function 0 P85 input pin 0 1 P85 output pin 1 -- RxD1 input pin ,54 input pin When the IRQ4E bit in IER is set to 1, this pin is used as the ,54 input pin. 225 Table 8.18 Port 8 Pin Functions (cont) Pin P84/,54/TxD1 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit TE in SCR of SCI1 and bit P84DDR. TE P84DDR Pin function 0 P84 input pin 0 1 P84 output pin 1 -- TxD1 output pin ,54 input pin When the IRQ3E bit in IER is set to 1, this pin is used as the ,54 input pin. P83 The pin function is switched as shown below according to bit P83DDR. P83DDR Pin function P82/HIFSD 0 P83 input pin 1 P83 output pin The pin function is switched as shown below according to the combination of operating mode, bit SDE in SYSCR2 of the HIF, and bit P82DDR. Operating mode SDE P82DDR Pin function 0 P82 input pin Not slave mode -- 1 P82 output pin 0 P82 input pin Slave mode 0 1 P82 output pin 1 -- HIFSD input pin P81/GA20/&6 The pin function is switched as shown below according to the combination of operating mode, bit CS2E, bit FGA20E in HICR of the HIF, and bit P81DDR. Operating mode FGA20E CS2E P81DDR Pin function 0 P81 input pin Not slave mode -- -- 1 P81 output pin 0 P81 input pin 0 1 P81 output pin 0 1 -- 0 P81 input pin Slave mode 1 -- 1 GA20 output pin &6 input pin This pin should be used as the GA20 or &6 output pin only in mode 2 or 3 (EXPE = 0). 226 Table 8.18 Port 8 Pin Functions (cont) Pin P80/HA0 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of operating mode and bit P80DDR. Operating mode P80DDR Pin function 0 P80 input pin Not slave mode 1 P80 output pin Slave mode -- HA0 input pin 227 8.10 8.10.1 Port 9 Overview Port 9 is an 8-bit I/O port. Port 9 pins also function as external interrupt input pins (,54 to the A/D converter external trigger input pin ($'75*), host interface input pins ((&6, &6, ,2:, ,25) (H8S/2138 Series only), the IIC0 I/O pin (SDA0) (option in H8S/2138 Series only), the subclock input pin (EXCL), bus control signal I/O pins ($6/,26, 5', :5, :$,7), and the system clock (o) output pin. In the H8S/2138 Series, P97 is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. ,54), Figure 8.17 shows the port 9 pin configuration. Port 9 pins P97/WAIT/SDA0 P96/o/EXCL P95/AS/IOS/CS1 Port 9 P94/WR/IOW P93/RD/IOR P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG/ECS2 Pin functions in modes 1, 2 and 3 (EXPE = 1) WAIT (Input)/P97 (I/O)/SDA0 (I/O) o (Output)/P96 (Input)/EXCL (Input) AS (Output)/IOS (Output) WR (Output) RD (Output) P92 (I/O)/IRQ0 (Input) P91 (I/O)/IRQ1 (Input) P90 (I/O)/IRQ2 (Input)/ADTRG (Input) Pin functions in modes 2 and 3 (EXPE = 0) P97 (I/O)/SDA0 (I/O) P96 (Input)/o (Output)/EXCL (Input) P95 (I/O)/CS1 (Input) P94 (I/O)/IOW (Input) P93 (I/O)/IOR (Input) P92 (I/O)/IRQ0 (Input) P91 (I/O)/IRQ1 (Input) P90 (I/O)/IRQ2 (Input)/ADTRG (Input)/ECS2 (Input) Figure 8.17 Port 9 Pin Functions 228 8.10.2 Register Configuration Table 8.19 summarizes the port 9 registers. Table 8.19 Port 9 Registers Name Port 9 data direction register Port 9 data register Abbreviation P9DDR P9DR R/W W R/W Initial Value H'40/H'00* H'00 2 Address H'FFC0 H'FFC1 *1 Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode. Port 9 Data Direction Register (P9DDR) Bit 7 6 5 4 3 2 1 0 P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 W 0 W 0 W 0 W 0 W 0 W 0 W P9DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 9. P9DDR cannot be read; if it is, an undefined value will be returned. P9DDR is initialized to H'40 (mode 1) or H'00 (modes 2 and 3) by a reset and in hardware standby mode. It retains its prior state in software standby mode. * Modes 1, 2, and 3 (EXPE = 1) Pin P97 functions as a bus control input (:$,7), the IIC0 I/O pin (SDA0), or an I/O port, according to the wait mode setting. When P97 functions as an I/O port, it becomes an output port when P97DDR is set to 1, and an input port when P97DDR is cleared to 0. Pin P96 functions as the o output pin when P96DDR is set to 1, and as the subclock input (EXCL) or an input port when P96DDR is cleared to 0. Pins P95 to P93 automatically become bus control outputs ($6/,26, :5, 5'), regardless of the input/output direction indicated by P95DDR to P93DDR. Pins P92 and P90 become output ports when P92DDR and P90DDR are set to 1, and input ports when P92DDR and P91DDR are cleared to 0. 229 * Modes 2 and 3 (EXPE = 0) When the corresponding P9DDR bits are set to 1, pin P96 functions as the o output pin and pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the corresponding pins become input ports. Port 9 Data Register (P9DR) Bit 7 P97DR Initial value Read/Write 0 R/W 6 P96DR --* R 5 P95DR 0 R/W 4 P94DR 0 R/W 3 P93DR 0 R/W 2 P92DR 0 R/W 1 P91DR 0 R/W 0 P90DR 0 R/W Note: * Determined by the state of pin P96. P9DR is an 8-bit readable/writable register that stores output data for the port 9 pins (P97 to P90). With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR values are read directly, regardless of the actual pin states. If a port 9 read is performed while P9DDR bits are cleared to 0, the pin states are read. P9DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 230 8.10.3 Pin Functions Port 9 pins also function as external interrupt input pins (,54 to ,54), the A/D converter trigger input pin ($'75*), HIF input pins ((&6, &6, ,2:, ,25), the IIC0 I/O pin (SDA0), the subclock input pin (EXCL), bus control signal I/O pins ($6/,26, 5', :5, :$,7), and the system clock (o) output pin. The pin functions differ between the mode 1, 2, and 3 (EXPE = 1) expanded modes and the mode 2 and 3 (EXPE = 0) single-chip modes. The port 9 pin functions are shown in table 8.20. Table 8.20 Port 9 Pin Functions Pin P97/:$,7/SDA0 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of operating mode, bit WMS1 in WSCR, bit ICE in ICCR of IIC0, and bit P97DDR. Operating mode WMS1 ICE P97DDR Pin function 0 0 1 Modes 1, 2, 3 (EXPE = 1) 0 1 -- 1 -- -- 0 0 1 Modes 2, 3 (EXPE = 0) -- 1 -- P97 input P97 SDA0 I/O pin output pin pin :$,7 input pin P97 input P97 SDA0 I/O pin output pin pin In the H8S/2138 Series, when this pin is set as the P97 output pin, it is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. P96/o/EXCL The pin function is switched as shown below according to the combination of bit EXCLE in LPWRCR and bit P96DDR. P96DDR EXCLE Pin function 0 P96 input pin 0 1 EXCL input pin 1 0 o output pin When this pin is used as the EXCL input pin, P96DDR should be cleared to 0. P95/$6/,26/&6 The pin function is switched as shown below according to the combination of operating mode, bit IOSE in SYSCR, bit HI12E in SYSCR2, and bit P95DDR. Operating mode HI12E P95DDR IOSE Pin function 0 Modes 1, 2, 3 (EXPE = 1) -- -- 1 0 -- P95 input pin Modes 2, 3 (EXPE = 0) 0 1 -- P95 output pin 1 -- -- $6 output pin ,26 output pin &6 input pin 231 Table 8.20 Port 9 Pin Functions (cont) Pin P94/:5/,2: Selection Method and Pin Functions The pin function is switched as shown below according to the combination of operating mode, bit HI12E in SYSCR2, and bit P94DDR. Operating mode HI12E P94DDR Pin function Modes 1, 2, 3 (EXPE = 1) -- -- 0 P94 input pin Modes 2, 3 (EXPE = 0) 0 1 P94 output pin 1 -- :5 output pin ,2: input pin P93/5'/,25 The pin function is switched as shown below according to the combination of operating mode, bit HI12E in SYSCR2, and bit P93DDR. Operating mode HI12E P93DDR Modes 1, 2, 3 (EXPE = 1) -- -- 0 Modes 2, 3 (EXPE = 0) 0 1 1 -- Pin function 5' output pin P93 input pin P93 output pin ,25 input pin P92/,54 P92DDR Pin function 0 P92 input pin 1 P92 output pin ,54 input pin When bit IRQ0E in IER is set to 1, this pin is used as the ,54 input pin. P91/,54 P91DDR Pin function 0 P91 input pin 1 P91 output pin ,54 input pin When bit IRQ1E in IER is set to 1, this pin is used as the ,54 input pin. 232 Table 8.20 Port 9 Pin Functions (cont) Pin P90/,54/ Selection Method and Pin Functions The pin function is switched as shown below according to the combination of operating mode, bits HI12E and CS2E in SYSCR2, bit FGA20E in HICR, and bit P90DDR. Operating mode HI12E FGA20E CS2E P90DDR Pin function 0 P90 input pin Modes 1, 2, 3 (EXPE = 1) -- -- -- 1 P90 output pin 0 P90 input pin 1 P90 output pin Modes 2, 3 (EXPE = 0) Any one 0 1 1 1 -- $'75*/(&6 (&6 input pin ,54 input pin, $'75* input pin When the IRQ2E bit in IER is set to 1, this pin is used as the ,54 input pin. When TRGS1 and TRGS0 in ADCR of the A/D converter are both set to 1, this pin is used as the $'75* input pin. 233 234 Section 9 8-Bit PWM Timers [H8S/2138 Series] 9.1 Overview The H8/2138 Series has an on-chip pulse width modulation (PWM) timer module with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division. The PWM timer module has sixteen 8-bit PWM data registers (PWDRs), and an output pulse with a duty cycle of 0 to 100% can be obtained as specified by PWDR and the port data register (P1DR or P2DR). 9.1.1 Features The PWM timer module has the following features. * Operable at a maximum carrier frequency of 1.25 MHz using pulse division (at 20 MHz operation) * Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output) * Direct or inverted PWM output, and PWM output enable/disable control 235 9.1.2 Block Diagram Figure 9.1 shows a block diagram of the PWM timer module. P10/PW0 P11/PW1 P12/PW2 P13/PW3 P14/PW4 Comparator 0 Comparator 1 Comparator 2 Comparator 3 Comparator 4 PWDR0 PWDR1 PWDR2 PWDR3 PWDR4 PWDR5 PWDR6 PWDR7 PWDR8 PWDR9 PWDR10 PWDR11 PWDR12 PWDR13 PWDR14 PWDR15 Module data bus Port/PWM output control P15/PW5 P16/PW6 P17/PW7 P20/PW8 P21/PW9 P22/PW10 P23/PW11 P24/PW12 P25/PW13 P26/PW14 P27/PW15 Comparator 5 Comparator 6 Comparator 7 Comparator 8 Comparator 9 Comparator 10 Comparator 11 Comparator 12 Comparator 13 Comparator 14 Comparator 15 Bus interface Internal data bus PWDPRB PWOERB P2DDR P2DR PWDPRA PWOERA P1DDR P1DR TCNT Clock selection PWSL PCSR o/16 o/8 o/4 o/2 o Internal clock Legend: PWSL: PWDR: PWDPRA: PWDPRB: PWOERA: PWOERB: PCSR: P1DDR: P2DDR: P1DR: P2DR: PWM register select PWM data register PWM data polarity register A PWM data polarity register B PWM output enable register A PWM output enable register B Peripheral clock select register Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Figure 9.1 Block Diagram of PWM Timer Module 236 9.1.3 Pin Configuration Table 9.1 shows the PWM output pin. Table 9.1 Name PWM output pin 0 to 15 Pin Configuration Abbreviation PW0 to PW15 I/O Output Function PWM timer pulse output 0 to 15 9.1.4 Register Configuration Table 9.2 lists the registers of the PWM timer module. Table 9.2 Name PWM register select PWM data registers 0 to 15 PWM data polarity register A PWM data polarity register B PWM output enable register A PWM output enable register B Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Peripheral clock select register Module stop control register PWM Timer Module Registers Abbreviation PWSL PWDR0 to PWDR15 PWDPRA PWDPRB PWOERA PWOERB P1DDR P2DDR P1DR P2DR PCSR MSTPCRH MSTPCRL R/W R/W R/W R/W R/W R/W R/W W W R/W R/W R/W R/W R/W Initial Value H'20 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'FF Address* H'FFD6 H'FFD7 H'FFD5 H'FFD4 H'FFD3 H'FFD2 H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FF82 H'FF86 H'FF87 Note: * Lower 16 bits of the address. 237 9.2 9.2.1 Bit Register Descriptions PWM Register Select (PWSL) 7 0 R/W 6 0 R/W 5 -- 1 -- 4 -- 0 -- 3 RS3 0 R/W 2 RS2 0 R/W 1 RS1 0 R/W 0 RS0 0 R/W PWCKE PWCKS Initial value Read/Write PWSL is an 8-bit readable/writable register used to select the PWM timer input clock and the PWM data register. PWSL is initialized to H'20 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. Bits 7 and 6--PWM Clock Enable, PWM Clock Select (PWCKE, PWCKS): These bits, together with bits PWCKA and PWCKB in PCSR, select the internal clock input to TCNT in the PWM timer. PWSL Bit 7 PWCKE 0 1 Bit 6 PWCKS -- 0 1 Bit 2 PWCKB -- -- 0 PCSR Bit 1 PWCKA -- -- 0 1 1 0 1 Description Clock input is disabled o (system clock) is selected o/2 is selected o/4 is selected o/8 is selected o/16 is selected (Initial value) The PWM resolution, PWM conversion period, and carrier frequency depend on the selected internal clock, and can be found from the following equations. Resolution (minimum pulse width) = 1/internal clock frequency PWM conversion period = resolution x 256 Carrier frequency = 16/PWM conversion period Thus, with a 20 MHz system clock (o), the resolution, PWM conversion period, and carrier frequency are as shown below. 238 Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency when o = 20 MHz Resolution 50 ns 100 ns 200 ns 400 ns 800 ns PWM Conversion Period 12.8 s 25.6 s 51.2 s 102.4 s 204.8 s Carrier Frequency 1250 kHz 625 kHz 312.5 kHz 156.3 kHz 78.1 kHz Internal Clock Frequency o o/2 o/4 o/8 o/16 Bit 5--Reserved: This bit is always read as 1 and cannot be modified. Bit 4--Reserved: This bit is always read as 0 and cannot be modified. Bits 3 to 0--Register Select (RS3 to RS0): These bits select the PWM data register. Bit 3 RS3 0 Bit 2 RS2 0 Bit 1 RS1 0 Bit 0 RS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Register Selection PWDR0 selected PWDR1 selected PWDR2 selected PWDR3 selected PWDR4 selected PWDR5 selected PWDR6 selected PWDR7 selected PWDR8 selected PWDR9 selected PWDR10 selected PWDR11 selected PWDR12 selected PWDR13 selected PWDR14 selected PWDR15 selected 239 9.2.2 Bit PWM Data Registers (PWDR0 to PWDR15) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value Read/Write Each PWDR is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper 4 bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The lower 4 bits specify how many extra pulses are to be added within the conversion period comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios within the conversion period. For 256/256 (100%) output, port output should be used. PWDR is initialized to H'00 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. 240 9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB) PWDPRA Bit Initial value Read/Write PWDPRB Bit Initial value Read/Write 7 OS15 0 R/W 6 OS14 0 R/W 5 OS13 0 R/W 4 OS12 0 R/W 3 OS11 0 R/W 2 OS10 0 R/W 1 OS9 0 R/W 0 OS8 0 R/W 7 OS7 0 R/W 6 OS6 0 R/W 5 OS5 0 R/W 4 OS4 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Each PWDPR is an 8-bit readable/writable register that controls the polarity of the PWM output. Bits OS0 to OS15 correspond to outputs PW0 to PW15. PWDPR is initialized to H'00 by a reset and in hardware standby mode. OS 0 1 Description PWM direct output (PWDR value corresponds to high width of output) (Initial value) PWM inverted output (PWDR value corresponds to low width of output) 241 9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) PWOERA Bit Initial value Read/Write PWOERB Bit Initial value Read/Write 7 OE15 0 R/W 6 OE14 0 R/W 5 OE13 0 R/W 4 OE12 0 R/W 3 OE11 0 R/W 2 OE10 0 R/W 1 OE9 0 R/W 0 OE8 0 R/W 7 OE7 0 R/W 6 OE6 0 R/W 5 OE5 0 R/W 4 OE4 0 R/W 3 OE3 0 R/W 2 OE2 0 R/W 1 OE1 0 R/W 0 OE0 0 R/W Each PWOER is an 8-bit readable/writable register that switches between PWM output and port output. Bits OE15 to OE0 correspond to outputs PW15 to PW0. To set a pin in the output state, a setting in the port direction register is also necessary. Bits P17DDR to P10DDR correspond to outputs PW7 to PW0, and bits P27DDR to P20DDR correspond to outputs PW15 to PW8. PWOER is initialized to H'00 by a reset and in hardware standby mode. DDR 0 OE 0 1 1 0 1 Description Port input Port input Port output or PWM 256/256 output PWM output (0 to 255/256 output) (Initial value) 242 9.2.5 Bit Peripheral Clock Select Register (PCSR) 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 0 R/W 1 0 R/W 0 -- 0 -- PWCKB PWCKA Initial value Read/Write PCSR is an 8-bit readable/writable register that selects the PWM timer input clock. PCSR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 0. Bits 2 and 1--PWM Clock Select (PWCKB, PWCKA): Together with bits PWCKE and PWCKS in PWSL, these bits select the internal clock input to TCNT in the PWM timer. For details, see section 9.2.1, PWM Register Select (PWSL). Bit 0--Reserved: Do not set this bit to 1. 243 9.2.6 Bit Port 1 Data Direction Register (P1DDR) 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value Read/Write P1DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for each pin of port 1 on a bit-by-bit basis. Port 1 pins are multiplexed with pins PW0 to PW7. The bit corresponding to a pin to be used for PWM output should be set to 1. For details on P1DDR, see section 8.2, Port 1. 244 9.2.7 Bit Port 2 Data Direction Register (P2DDR) 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value Read/Write P2DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for each pin of port J on a bit-by-bit basis. Port 2 pins are multiplexed with pins PW8 to PW15. The bit corresponding to a pin to be used for PWM output should be set to 1. For details on P2DDR, see section 8.3, Port 2. 245 9.2.8 Bit Port 1 Data Register (P1DR) 7 P17DR 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W Initial value Read/Write P1DR is an 8-bit readable/writable register used to fix PWM output at 1 (when OS = 0) or 0 (when OS = 1). For details on P1DR, see section 8.2, Port 1. 246 9.2.9 Bit Port 2 Data Register (P2DR) 7 P27DR 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W Initial value Read/Write P2DR is an 8-bit readable/writable register used to fix PWM output at 1 (when OS = 0) or 0 (when OS = 1). For details on P2DR, see section 8.3, Port 2. 247 9.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 Bit Initial value Read/Write 7 6 5 4 3 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. When the MSTP11 bit is set to 1, 8-bit PWM timer operation is halted and a transition is made to module stop mode. For details, see section 23.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 3--Module Stop (MSTP11): Specifies PWM module stop mode. MSTPCRH Bit 3 MSTP11 0 1 Description PWM module stop mode is cleared PWM module stop mode is set (Initial value) 248 9.3 9.3.1 Operation Correspondence between PWM Data Register Contents and Output Waveform The upper 4 bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16, as shown in table 9.4. Table 9.4 Upper 6 Bits 000000 000001 000010 000011 000100 000101 000110 000111 Duty Cycle of Basic Pulse Basic Pulse Waveform (Internal) 0 1 2 3 4 5 6 7 8 9 A BC D E F 0 . . . 111000 111001 111010 111011 111100 111101 111110 111111 249 The lower 4 bits of PWDR specify the position of pulses added to the 16 basic pulses, as shown in table 9.5. An additional pulse consists of a high period (when OS = 0) with a width equal to the resolution, added before the rising edge of a basic pulse. When the upper 4 bits of PWDR are 0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. Table 9.5 Position of Pulses Added to Basic Pulses Basic Pulse No. Lower 4 Bits 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No additional pulse Resolution width Additional pulse provided Additional pulse Figure 9.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = 1000) 250 Section 10 14-Bit PWM D/A 10.1 Overview The H8S/2138 Series and H8S/2134 Series have an on-chip 14-bit pulse-width modulator (PWM) with two output channels. Each channel can be connected to an external low-pass filter to operate as a 14-bit D/A converter. Both channels share the same counter (DACNT) and control register (DACR). 10.1.1 Features The features of the 14-bit PWM D/A are listed below. * The pulse is subdivided into multiple base cycles to reduce ripple. * Two resolution settings and two base cycle settings are available The resolution can be set equal to one or two system clock cycles. The base cycle can be set equal to T x 64 or T x 256, where T is the resolution. * Four operating rates The two resolution settings and two base cycle settings combine to give a selection of four operating rates. 251 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the PWM D/A module. Internal clock o o/2 Clock selection Clock Basic cycle compare-match A PWX0 PWX1 Fine-adjustment pulse addition A Basic cycle compare-match B Fine-adjustment pulse addition B Control logic Comparator B DADRB Comparator A DADRA Bus interface Internal data bus Basic cycle overflow DACNT DACR Module data bus Legend: DACR: DADRA: DADRB: DACNT: PWM D/A control register ( 6 bits) PWM D/A data register A (15 bits) PWM D/A data register B (15 bits) PWM D/A counter (14 bits) Figure 10.1 PWM D/A Block Diagram 10.1.3 Pin Configuration Table 10.1 lists the pins used by the PWM D/A module. Table 10.1 Input and Output Pins Channel A B Name PWM output pin 0 PWM output pin 1 Abbr. PWX0 PWX1 I/O Output Output Function PWM output, channel A PWM output, channel B 252 10.1.4 Register Configuration Table 10.2 lists the registers of the PWM D/A module. Table 10.2 Register Configuration Name PWM D/A control register PWM D/A data register A high PWM D/A data register A low PWM D/A data register B high PWM D/A data register B low PWM D/A counter high PWM D/A counter low Module stop control register Abbreviation DACR DADRAH DADRAL DADRBH DADRBL DACNTH DACNTL MSTPCRH MSTPCRL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value H'30 H'FF H'FF H'FF H'FF H'00 H'03 H'3F H'FF Address*1 H'FFA0* H'FFA0* H'FFA1* H'FFA6* H'FFA7* H'FFA6* H'FFA7* H'FF86 H'FF87 2 2 2 2 2 2 2 Notes: 1. Lower 16 bits of the address. 2. The same addresses are shared by DADRAH and DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or DADRB. 253 10.2 10.2.1 Register Descriptions PWM D/A Counter (DACNT) DACNTH DACNTL 10 2 9 1 8 0 7 8 6 9 5 10 4 11 3 12 2 13 1 -- 0 -- Bit (CPU) BIT (Counter) Initial value Read/Write 15 7 14 6 13 5 12 4 11 3 -- REGS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 -- 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse. The input clock is selected by the clock select bit (CKS) in DACR. The CPU can read and write the DACNT value, but since DACNT is a 16-bit register, data transfers between it and the CPU are performed using a temporary register (TEMP). See section 10.3, Bus Master Interface, for details. DACNT functions as the time base for both PWM D/A channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12-bit precision, it uses the lower 12 (counter) bits and ignores the upper two (counter) bits. DACNT is initialized to H'0003 by a reset, in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode, and by the PWME bit. Bit 1 of DACNTL (CPU) is not used, and is always read as 1. DACNTL Bit 0--Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS bit can be accessed regardless of whether DADRB or DACNT is selected. Bit 0 REGS 0 1 Description DADRA and DADRB can be accessed DACR and DACNT can be accessed (Initial value) 254 10.2.2 D/A Data Registers A and B (DADRA and DADRB) DADRH DADRL 10 8 9 7 8 6 7 5 6 4 5 3 4 2 3 1 2 0 1 -- 0 -- -- 1 -- Bit (CPU) Bit (Data) DADRA Initial value Read/Write DADRB Initial value Read/Write 15 13 14 12 13 11 12 10 11 9 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DADRA corresponds to PWM D/A channel A, and DADRB to PWM D/A channel B. The CPU can read and write the PWM D/A data register values, but since DADRA and DADRB are 16-bit registers, data transfers between them and the CPU are performed using a temporary register (TEMP). See section 10.3, Bus Master Interface, for details. The least significant (CPU) bit of DADRA is not used and is always read as 1. DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. 255 Bits 15 to 3--PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an analog value is set in the upper 14 bits of the PWM D/A data register. In each base cycle, the DACNT value is continually compared with these upper 14 bits to determine the duty cycle of the output waveform, and to decide whether to output a fineadjustment pulse equal in width to the resolution. To enable this operation, the data register must be set within a range that depends on the carrier frequency select bit (CFS). If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA0 and DA1) cleared to 0 and writing the data to be converted in the upper 12 bits. The two lowest data bits correspond to the two highest counter (DACNT) bits. Bit 1--Carrier Frequency Select (CFS) 0 1 Base cycle = resolution (T) x 64 DADR range = H'0401 to H'FFFD Base cycle = resolution (T) x 256 DADR range = H'0103 to H'FFFFF (Initial value) DADRA Bit 0--Reserved: This bit cannot be modified and is always read as 1. DADRB Bit 0--Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS bit can be accessed regardless of whether DADRB or DACNT is selected. 0 1 DADRA and DADRB can be accessed DACR and DACNT can be accessed (Initial value) 256 10.2.3 Bit PWM D/A Control Register (DACR) 7 TEST 0 R/W 6 PWME 0 R/W 5 -- 1 -- 4 -- 1 -- 3 OEB 0 R/W 2 OEA 0 R/W 1 OS 0 R/W 0 CKS 0 R/W Initial value Read/Write DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and selects the output phase and operating speed. DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7--Test Mode (TEST): Selects test mode, which is used in testing the chip. Normally this bit should be cleared to 0. 0 1 PWM (D/A) in user state: normal operation PWM (D/A) in test state: correct conversion results unobtainable (Initial value) Bit 6--PWM Enable (PWME): Starts or stops the PWM D/A counter (DACNT). 0 1 DACNT operates as a 14-bit up-counter DACNT halts at H'0003 (Initial value) Bits 5 and 4--Reserved: These bits cannot be modified and are always read as 1. Bit 3--Output Enable B (OEB): Enables or disables output on PWM D/A channel B. 0 1 PWM (D/A) channel B output (at the PWX1 pin) is disabled PWM (D/A) channel B output (at the PWX1 pin) is enabled (Initial value) 257 Bit 2--Output Enable A (OEA): Enables or disables output on PWM D/A channel A. Bit 2 OEA 0 1 Description PWM (D/A) channel A output (at the PWX0 pin) is disabled PWM (D/A) channel A output (at the PWX0 pin) is enabled (Initial value) Bit 1--Output Select (OS): Selects the phase of the PWM D/A output. Bit 1 OS 0 1 Description Direct PWM output Inverted PWM output (Initial value) Bit 0--Clock Select (CKS): Selects the PWM D/A resolution. If the system clock (o) frequency is 10 MHz, resolutions of 100 ns and 200 ns can be selected. Bit 0 CKS 0 1 Description Operates at resolution (T) = system clock cycle time (tcyc) Operates at resolution (T) = system clock cycle time (tcyc) x 2 (Initial value) 258 10.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 Bit Initial value Read/Write 7 6 5 4 3 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. When the MSTP11 bit is set to 1, 14-bit PWM timer operation is halted and a transition is made to module stop mode. For details, see section 23.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 3--Module Stop (MSTP11): Specifies PWMX module stop mode. MSTPCRH Bit 3 MSTP11 0 1 Description PWMX module stop mode is cleared PWMX module stop mode is set (Initial value) 259 10.3 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written and read as follows (taking the example of the CPU interface). * Write When the upper byte is written, the upper-byte write data is stored in TEMP. Next, when the lower byte is written, the lower-byte write data and TEMP value are combined, and the combined 16-bit value is written in the register. * Read When the upper byte is read, the upper-byte value is transferred to the CPU and the lowerbyte value is transferred to TEMP. Next, when the lower byte is read, the lower-byte value in TEMP is transferred to the CPU. These registers should always be accessed 16 bits at a time using an MOV instruction (by word access or two consecutive byte accesses), and the upper byte should always be accessed before the lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction cannot be used to access these registers. Figure 10.2 shows the data flow for access to DACNT. The other registers are accessed similarly. Example 1: Write to DACNT MOV.W R0, @DACNT ; Write R0 contents to DACNT Example 2: Read DADRA MOV.W @DADRA, R0 ; Copy contents of DADRA to R0 Table 10.3 Read and Write Access Methods for 16-Bit Registers Read Register Name DADRA and DADRB DACNT Word Yes Yes Byte Yes x Word Yes Yes Write Byte x x Notes: Yes: Permitted type of access. Word access includes successive byte accesses to the upper byte (first) and lower byte (second). x: This type of access may give incorrect results. 260 Upper-Byte Write Bus interface Module data bus CPU (H'AA) Upper byte TEMP (H'AA) DACNTH ( ) DACNTL ( ) Lower-Byte Write Bus interface Module data bus CPU (H'57) Lower byte TEMP (H'AA) DACNTH (H'AA) DACNTL (H'57) Figure 10.2 (a) Access to DACNT (CPU Writes H'AA57 to DACNT) 261 Upper-Byte Read Bus interface Module data bus CPU (H'AA) Upper byte TEMP (H'57) DACNTH (H'AA) DACNTL (H'57) Lower-Byte Read Bus interface Module data bus CPU (H'57) Lower byte TEMP (H'57) DACNTH ( ) DACNTL ( ) Figure 10.2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT) 262 10.4 Operation A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. When OS = 0, the value in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output waveform is inverted and the DADR value corresponds to the total width (TH) of the high (1) output pulses. Figure 10.4 shows the types of waveform output available. 1 conversion cycle (T x 214 (= 16384)) tf Basic cycle (T x 64 or T x 256) tL T: Resolution TL = tLn (when OS = 0) n=1 m (When CFS = 0, m = 256; when CFS = 1, m = 64) Figure 10.3 PWM D/A Operation Table 10.4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution, base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a certain minimum value. Table 10.4 indicates the range of DADR settings that give an output waveform like the one in figure 10.3, and lists the conversion cycle length when low-order DADR bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits. 263 Table 10.4 Settings and Operation (Examples when o = 10 MHz) Fixed DADR Bits Bit Data Resolution Base CycleConversion TL (if OS = 0) CKS T (s) CFS (s) Cycle (s) TH (if OS = 1) 0 0.1 0 6.4 1638.4 Precision Conversion (Bits) 3 2 1 0 Cycle* (s) 1638.4 1. Always low (or high) 14 (DADR = H'0001 to H'03FD) 2. (Data value) x T (DADR = H'0401 to H'FFFD) 10 12 0 0 409.6 0 0 0 0 102.4 1638.4 1 25.6 1638.4 1. Always low (or high) 14 (DADR = H'0003 to H'00FF) 2. (Data value) x T (DADR = H'0103 to H'FFFF) 10 12 0 0 409.6 0 0 0 0 102.4 3276.8 1 0.2 0 12.8 3276.8 1. Always low (or high) 14 (DADR = H'0001 to H'03FD) 2. (Data value) x T (DADR = H'0401 to H'FFFD) 10 12 0 0 819.2 0 0 0 0 204.8 3276.8 1 51.2 3276.8 1. Always low (or high) 14 (DADR = H'0003 to H'00FF) 2. (Data value) x T (DADR = H'0103 to H'FFFF) 10 12 0 0 819.2 0 0 0 0 204.8 Note: * This column indicates the conversion cycle when specific DADR bits are fixed. 264 1. OS = 0 (DADR corresponds to TL) a. CFS = 0 [base cycle = resolution (T) x 64] 1 conversion cycle tf1 tf2 tf255 tf256 tL1 tL2 tL3 tL255 tL256 tf1 = tf2 = tf3 = * * * = tf255 = tf256 = T x 64 tL1 + tL2 + tL3 + * * * + tL255 + tL256 = TL Figure 10.4 (1) Output Waveform b. CFS = 1 [base cycle = resolution (T) x 256] 1 conversion cycle tf1 tf2 tf63 tf64 tL1 tL2 tL3 tL63 tL64 tf1 = tf2 = tf3 = * * * = tf63 = tf64 = T x 256 tL1 + tL2 + tL3 + * * * + tL63 + tL64 = TL Figure 10.4 (2) Output Waveform 265 2. OS = 1 (DADR corresponds to TH) a. CFS = 0 [base cycle = resolution (T) x 64] 1 conversion cycle tf1 tf2 tf255 tf256 tH1 tH2 tH3 tH255 tH256 tf1 = tf2 = tf3 = * * * = tf255 = tf256 = T x 64 tH1 + tH2 + tH3 + * * * + tH255 + tH256 = TH Figure 10.4 (3) Output Waveform b. CFS = 1 [base cycle = resolution (T) x 256] 1 conversion cycle tf1 tf2 tf63 tf64 tH1 tH2 tH3 tH63 tH64 tf1 = tf2 = tf3 = * * * = tf63 = tf64 = T x 256 tH1 + tH2 + tH3 + * * * + tH63 + tH64 = TH Figure 10.4 (4) Output Waveform 266 Section 11 16-Bit Free-Running Timer 11.1 Overview The H8S/2138 Series and H8S/2134 Series have a single-channel on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 11.1.1 Features The features of the free-running timer module are listed below. * Selection of four clock sources The free-running counter can be driven by an internal clock source (o/2, o/8, or o/32), or an external clock input (enabling use as an external event counter). * Two independent comparators Each comparator can generate an independent waveform. * Four input capture channels The current count can be captured on the rising or falling edge (selectable) of an input signal. The four input capture registers can be used separately, or in a buffer mode. * Counter can be cleared under program control The free-running counters can be cleared on compare-match A. * Seven independent interrupts Two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. * Special functions provided by automatic addition function The contents of OCRAR and OCRAF can be added to the contents of OCRA automatically, enabling a periodic waveform to be generated without software intervention. The contents of ICRD can be added automatically to the contents of OCRDM x 2, enabling input capture operations in this interval to be restricted. 267 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the free-running timer. External clock source Internal clock sources o/2 o/8 o/32 Clock select Clock Comparematch A FTOA FTOB Overflow Clear Comparator B Module data bus Bus interface OCRA R/F (H/L) FTCI + OCRA (H/L) Comparator A FRC (H/L) Internal data bus Comparematch B OCRB (H/L) Control logic FTIA FTIB FTIC FTID Comparator M Compare-match M OCRDM L TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Legend: OCRA, B: FRC: ICRA, B, C, D: TCSR: Input capture ICRA (H/L) ICRB (H/L) ICRC (H/L) ICRD (H/L) + x1 x2 Interrupt signals Output compare register A, B (16 bits) Free-running counter (16 bits) Input capture register A, B, C, D (16 bits) Timer control/status register (8 bits) TIER: Timer interrupt enable register (8 bits) TCR: Timer control register (8 bits) TOCR: Timer output compare control register (8 bits) Figure 11.1 Block Diagram of 16-Bit Free-Running Timer 268 11.1.3 Input and Output Pins Table 11.1 lists the input and output pins of the free-running timer module. Table 11.1 Input and Output Pins of Free-Running Timer Module Name Counter clock input Output compare A Output compare B Input capture A Input capture B Input capture C Input capture D Abbreviation FTCI FTOA FTOB FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function FRC counter clock input Output compare A output Output compare B output Input capture A input Input capture B input Input capture C input Input capture D input 269 11.1.4 Register Configuration Table 11.2 lists the registers of the free-running timer module. Table 11.2 Register Configuration Name Timer interrupt enable register Timer control/status register Free-running counter Output compare register A Output compare register B Timer control register Timer output compare control register Input capture register A Input capture register B Input capture register C Input capture register D Output compare register AR Output compare register AF Output compare register DM Module stop control register Abbreviation TIER TCSR FRC OCRA OCRB TCR TOCR ICRA ICRB ICRC ICRD OCRAR OCRAF OCRDM MSTPCRH MSTPCRL R/W R/W R/(W)* R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W 2 Initial Value H'01 H'00 H'0000 H'FFFF H'FFFF H'00 H'00 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'0000 H'3F H'FF Address*1 H'FF90 H'FF91 H'FF92 H'FF94* H'FF94* H'FF96 H'FF97 H'FF98* 4 3 3 H'FF9A* 4 H'FF9C* H'FF9E H'FF98* 4 4 H'FF9A* 4 H'FF9C* H'FF86 H'FF87 4 Notes: 1. Lower 16 bits of the address. 2. Bits 7 to 1 are read-only; only 0 can be written to clear the flags. Bit 0 is readable/writable. 3. OCRA and OCRB share the same address. Access is controlled by the OCRS bit in TOCR. 4. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and OCRDM. Access is controlled by the ICRS bit in TOCR. 270 11.2 11.2.1 Bit Register Descriptions Free-Running Counter (FRC) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can also be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in TCSR is set to 1. FRC is initialized to H'0000 by a reset and in hardware standby mode. 271 11.2.2 Bit Output Compare Registers A and B (OCRA, OCRB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC. When a match is detected, the corresponding output compare flags (OCFA or OCFB) is set in TCSR. In addition, if the output enable bit (OEA or OEB) in TOCR is set to 1, when OCR and FRC values match, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCR is initialized to H'FFFF by a reset and in hardware standby mode. 272 11.2.3 Bit Input Capture Registers A to D (ICRA to ICRD) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R There are four input capture registers, A to D, each of which is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is detected, the current FRC value is copied to the corresponding input capture register (ICRA to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to 1. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR. ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, and made to perform buffer operations, by means of buffer enable bits A and B (BUFEA, BUFEB) in TCR. Figure 11.2 shows the connections when ICRC is specified as the ICRA buffer register (BUFEA = 1). When ICRC is used as the ICRA buffer, both rising and falling edges can be specified as transitions of the external input signal by setting IEDGA _ IEDGC. When IEDGA = IEDGC, either the rising or falling edge is designated. See table 11.3. Note: The FRC contents are transferred to the input capture register regardless of the value of the input capture flag (ICF). IEDGA BUFEA IEDGC FTIA Edge detect and capture signal generating circuit ICRC ICRA FRC Figure 11.2 Input Capture Buffering (Example) 273 Table 11.3 Buffered Input Capture Edge Selection (Example) IEDGA 0 IEDGC 0 1 1 0 1 Captured on rising edge of input capture A (FTIA) Description Captured on falling edge of input capture A (FTIA) (Initial value) Captured on both rising and falling edges of input capture A (FTIA) To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock periods (1.5o). When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods. ICR is initialized to H'0000 by a reset and in hardware standby mode. 11.2.4 Bit Initial value Output Compare Registers AR and AF (OCRAR, OCRAF) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the first compare-match A after the OCRAMS bit is set to 1, OCRAF is added. The operation due to compare-match A varies according to whether the compare-match follows addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a compare-match A following addition of OCRAF, while 0 is output on a comparematch A following addition of OCRAR. When the OCRA automatically addition function is used, do not set internal clock o/2 as the FRC counter input clock together with an OCRAR (or OCRAF) value of H'0001 or less. OCRAR and OCRAF are initialized to H'FFFF by a reset and in hardware standby mode. 274 11.2.5 Bit Output Compare Register DM (OCRDM) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00. When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, the operation of ICRD is changed to include the use of OCRDM. The point at which input capture D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to the contents of ICRD, and the result is compared with the FRC value. The point at which the values match is taken as the end of the mask interval. New input capture D events are disabled during the mask interval. A mask interval is not generated when the ICRDMS bit is set to 1 and the contents of OCRDM are H'0000. OCRDM is initialized to H'0000 by a reset and in hardware standby mode. 11.2.6 Bit Initial value Read/Write Timer Interrupt Enable Register (TIER) 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 OCIAE 0 R/W 2 OCIBE 0 R/W 1 OVIE 0 R/W 0 -- 1 -- TIER is an 8-bit readable/writable register that enables and disables interrupts. TIER is initialized to H'01 by a reset and in hardware standby mode. Bit 7--Input Capture Interrupt A Enable (ICIAE): Selects whether to request input capture interrupt A (ICIA) when input capture flag A (ICFA) in TCSR is set to 1. Bit 7 ICIAE 0 1 Description Input capture interrupt request A (ICIA) is disabled Input capture interrupt request A (ICIA) is enabled (Initial value) 275 Bit 6--Input Capture Interrupt B Enable (ICIBE): Selects whether to request input capture interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1. Bit 6 ICIBE 0 1 Description Input capture interrupt request B (ICIB) is disabled Input capture interrupt request B (ICIB) is enabled (Initial value) Bit 5--Input Capture Interrupt C Enable (ICICE): Selects whether to request input capture interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1. Bit 5 ICICE 0 1 Description Input capture interrupt request C (ICIC) is disabled Input capture interrupt request C (ICIC) is enabled (Initial value) Bit 4--Input Capture Interrupt D Enable (ICIDE): Selects whether to request input capture interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1. Bit 4 ICIDE 0 1 Description Input capture interrupt request D (ICID) is disabled Input capture interrupt request D (ICID) is enabled (Initial value) 276 Bit 3--Output Compare Interrupt A Enable (OCIAE): Selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. Bit 3 OCIAE 0 1 Description Output compare interrupt request A (OCIA) is disabled Output compare interrupt request A (OCIA) is enabled (Initial value) Bit 2--Output Compare Interrupt B Enable (OCIBE): Selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. Bit 2 OCIBE 0 1 Description Output compare interrupt request B (OCIB) is disabled Output compare interrupt request B (OCIB) is enabled (Initial value) Bit 1--Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. Bit 1 OVIE 0 1 Description Timer overflow interrupt request (FOVI) is disabled Timer overflow interrupt request (FOVI) is enabled (Initial value) Bit 0--Reserved: This bit cannot be modified and is always read as 1. 277 11.2.7 Bit Timer Control/Status Register (TCSR) 7 ICFA 0 R/(W)* 6 ICFB 0 R/(W)* 5 ICFC 0 R/(W)* 4 ICFD 0 R/(W)* 3 OCFA 0 R/(W)* 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* 0 CCLRA 0 R/W Initial value Read/Write Note: * Only 0 can be written in bits 7 to 1 to clear these flags. TCSR is an 8-bit register used for counter clear selection and control of interrupt request signals. TCSR is initialized to H'00 by a reset and in hardware standby mode. Timing is described in section 11.3, Operation. Bit 7--Input Capture Flag A (ICFA): This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been transferred to ICRA. ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 7 ICFA 0 1 Description [Clearing condition] Read ICFA when ICFA = 1, then write 0 in ICFA [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRA (Initial value) 278 Bit 6--Input Capture Flag B (ICFB): This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB. ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 6 ICFB 0 1 Description [Clearing condition] Read ICFB when ICFB = 1, then write 0 in ICFB [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRB (Initial value) Bit 5--Input Capture Flag C (ICFC): This status flag indicates that the FRC value has been transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of the signal transition in FTIC (input capture signal) specified by the IEDGC bit, ICFC is set but data is not transferred to ICRC. Therefore, in buffer operation, ICFC can be used as an external interrupt signal (by setting the ICICE bit to 1). ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 5 ICFC 0 1 Description [Clearing condition] Read ICFC when ICFC = 1, then write 0 in ICFC [Setting condition] When an input capture signal is received (Initial value) 279 Bit 4--Input Capture Flag D (ICFD): This status flag indicates that the FRC value has been transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of the signal transition in FTID (input capture signal) specified by the IEDGD bit, ICFD is set but data is not transferred to ICRD. Therefore, in buffer operation, ICFD can be used as an external interrupt by setting the ICIDE bit to 1. ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 4 ICFD 0 1 Description [Clearing condition] Read ICFD when ICFD = 1, then write 0 in ICFD [Setting condition] When an input capture signal is received (Initial value) Bit 3--Output Compare Flag A (OCFA): This status flag indicates that the FRC value matches the OCRA value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 3 OCFA 0 1 Description [Clearing condition] Read OCFA when OCFA = 1, then write 0 in OCFA [Setting condition] When FRC = OCRA (Initial value) Bit 2--Output Compare Flag B (OCFB): This status flag indicates that the FRC value matches the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 2 OCFB 0 1 Description [Clearing condition] Read OCFB when OCFB = 1, then write 0 in OCFB [Setting condition] When FRC = OCRB (Initial value) 280 Bit 1--Timer Overflow Flag (OVF): This status flag indicates that the FRC has overflowed (changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 1 OVF 0 1 Description [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] When FRC changes from H'FFFF to H'0000 (Initial value) Bit 0--Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at compare-match A (when the FRC and OCRA values match). Bit 0 CCLRA 0 1 Description FRC clearing is disabled FRC is cleared at compare-match A (Initial value) 281 11.2.8 Bit Timer Control Register (TCR) 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value Read/Write TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. TCR is initialized to H'00 by a reset and in hardware standby mode Bit 7--Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A signal (FTIA). Bit 7 IEDGA 0 1 Description Capture on the falling edge of FTIA Capture on the rising edge of FTIA (Initial value) Bit 6--Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B signal (FTIB). Bit 6 IEDGB 0 1 Description Capture on the falling edge of FTIB Capture on the rising edge of FTIB (Initial value) Bit 5--Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C signal (FTIC). Bit 5 IEDGC 0 1 Description Capture on the falling edge of FTIC Capture on the rising edge of FTIC (Initial value) 282 Bit 4--Input Edge Select D (IEDGD): Selects the rising or falling edge of the input capture D signal (FTID). Bit 4 IEDGD 0 1 Description Capture on the falling edge of FTID Capture on the rising edge of FTID (Initial value) Bit 3--Buffer Enable A (BUFEA): Selects whether ICRC is to be used as a buffer register for ICRA. Bit 3 BUFEA 0 1 Description ICRC is not used as a buffer register for input capture A ICRC is used as a buffer register for input capture A (Initial value) Bit 2--Buffer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for ICRB. Bit 2 BUFEB 0 1 Description ICRD is not used as a buffer register for input capture B ICRD is used as a buffer register for input capture B (Initial value) Bits 1 and 0--Clock Select (CKS1, CKS0): Select external clock input or one of three internal clock sources for the FRC. External clock pulses are counted on the rising edge of signals input to the external clock input pin (FTCI). Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description o/2 internal clock source o/8 internal clock source o/32 internal clock source External clock source (rising edge) (Initial value) 283 11.2.9 Bit Timer Output Compare Control Register (TOCR) 7 0 R/W 6 0 R/W 5 ICRS 0 R/W 4 OCRS 0 R/W 3 OEA 0 R/W 2 OEB 0 R/W 1 OLVLA 0 R/W 0 OLVLB 0 R/W ICRDMS OCRAMS Initial value Read/Write TOCR is an 8-bit readable/writable register that enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, controls the ICRD and OCRA operating mode, and switches access to input capture registers A, B, and C. TOCR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--Input Capture D Mode Select (ICRDMS): Specifies whether ICRD is used in the normal operating mode or in the operating mode using OCRDM. 0 1 The normal operating mode is specified for ICRD The operating mode using OCRDM is specified for ICRD (Initial value) Bit 6--Output Compare A Mode Select (OCRAMS): Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF. 0 1 The normal operating mode is specified for OCRA The operating mode using OCRAR and OCRAF is specified for OCRA (Initial value) Bit 5--Input Capture Register Select (ICRS): The same addresses are shared by ICRA and OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which registers are selected when the shared addresses are read or written to. The operation of ICRA, ICRB, and ICRC is not affected. 0 1 The ICRA, ICRB, and ICRC registers are selected The OCRAR, OCRAF, and OCRDM registers are selected (Initial value) 284 Bit 4--Output Compare Register Select (OCRS): OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. This bit does not affect the operation of OCRA or OCRB. Bit 4 OCRS 0 1 Description The OCRA register is selected The OCRB register is selected (Initial value) Bit 3--Output Enable A (OEA): Enables or disables output of the output compare A signal (FTOA). Bit 3 OEA 0 1 Description Output compare A output is disabled Output compare A output is enabled (Initial value) Bit 2--Output Enable B (OEB): Enables or disables output of the output compare B signal (FTOB). Bit 2 OEB 0 1 Description Output compare B output is disabled Output compare B output is enabled (Initial value) Bit 1--Output Level A (OLVLA): Selects the logic level to be output at the FTOA pin in response to compare-match A (signal indicating a match between the FRC and OCRA values). When the OCRAMS bit is 1, this bit is ignored. Bit 1 OLVLA 0 1 Description 0 output at compare-match A 1 output at compare-match A (Initial value) Bit 0--Output Level B (OLVLB): Selects the logic level to be output at the FTOB pin in response to compare-match B (signal indicating a match between the FRC and OCRB values). Bit 0 OLVLB 0 1 Description 0 output at compare-match B 1 output at compare-match B (Initial value) 285 11.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit Initial value Read/Write 7 6 5 4 3 2 1 0 7 6 5 MSTPCRL 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP13 bit is set to 1, FRT operation is stopped at the end of the bus cycle, and module stop mode is entered. For details, see section 23.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 5--Module Stop (MSTP13): Specifies the FRT module stop mode. Bit 5 MSTPCRH 0 1 Description FRT module stop mode is cleared FRT module stop mode is set (Initial value) 286 11.3 11.3.1 Operation FRC Increment Timing FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock: Any of three internal clocks (o/2, o/8, or o/32) created by division of the system clock (o) can be selected by making the appropriate setting in bits CKS1 and CKS0 in TCR. Figure 11.3 shows the increment timing. o Internal clock FRC input clock FRC N-1 N N+1 Figure 11.3 Increment Timing with Internal Clock Source External Clock: If external clock input is selected by bits CKS1 and CKS0 in TCR, FRC increments on the rising edge of the external clock signal. The pulse width of the external clock signal must be at least 1.5 system clock (o) periods. The counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. Figure 11.4 shows the increment timing. o External clock input pin FRC input clock FRC N N+1 Figure 11.4 Increment Timing with External Clock Source 287 11.3.2 Output Compare Output Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A. o FRC N N+1 N N+1 OCRA Compare-match A signal N N Clear* OLVLA Output compare A output pin FTOA Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 11.5 Timing of Output Compare A Output 288 11.3.3 FRC Clear Timing FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this operation. o Compare-match A signal FRC N H'0000 Figure 11.6 Clearing of FRC by Compare-Match A 11.3.4 Input Capture Input Timing Input Capture Input Timing: An internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin, as selected by the corresponding IEDGx (x = A to D) bit in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is selected (IEDGx = 1). o Input capture input pin Input capture signal Figure 11.7 Input Capture Signal Timing (Usual Case) If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (o) period. Figure 11.8 shows the timing for this case. 289 ICRA/B/C/D read cycle T1 o T2 Input capture input pin Input capture signal Figure 11.8 Input Capture Signal Timing (Input Capture Input when ICRA/B/C/D is Read) Buffered Input Capture Input Timing: ICRC and ICRD can operate as buffers for ICRA and ICRB. Figure 11.9 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. o FTIA Input capture signal FRC n n+1 N N+1 ICRA M n n N ICRC m M M n Figure 11.9 Buffered Input Capture Timing (Usual Case) 290 When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if the upper byte of either of the two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives, input capture is delayed by one system clock (o) period. Figure 11.10 shows the timing when BUFEA = 1. Read cycle: CPU reads ICRA or ICRC T1 o FTIA T2 Input capture signal Figure 11.10 Buffered Input Capture Timing (Input Capture Input when ICRA or ICRC is Read) 11.3.5 Timing of Input Capture Flag (ICF) Setting The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRx). Figure 11.11 shows the timing of this operation. o Input capture signal ICFA/B/C/D FRC N ICRA/B/C/D N Figure 11.11 Setting of Input Capture Flag (ICFA/B/C/D) 291 11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB) The output compare flags are set to 1 by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 11.12 shows the timing of the setting of OCFA and OCFB. o FRC N N+1 OCRA or OCRB N Compare-match signal OCFA or OCFB Figure 11.12 Setting of Output Compare Flag (OCFA, OCFB) 292 11.3.7 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 11.13 shows the timing of this operation. o FRC H'FFFF H'0000 Overflow signal OVF Figure 11.13 Setting of Overflow Flag (OVF) 293 11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. The OCRA write timing is shown in figure 11.14. o FRC N N+1 OCRA N N+A OCRAR, F Compare-match signal A Figure 11.14 OCRA Automatic Addition Timing 294 11.3.9 ICRD and OCRDM Mask Signal Generation When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture function is generated. The mask signal is set by the input capture signal. The mask signal setting timing is shown in figure 11.15. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match. The mask signal clearing timing is shown in figure 11.16. o Input capture signal Input capture mask signal Figure 11.15 Input Capture Mask Signal Setting Timing o FRC N N+1 ICRD + OCRDM x 2 Compare-match signal Input capture mask signal N Figure 11.16 Input Capture Mask Signal Clearing Timing 295 11.4 Interrupts The free-running timer can request seven interrupts (three types): input capture A to D (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 11.4 lists information about these interrupts. Table 11.4 Free-Running Timer Interrupts Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI Description Requested by ICFA Requested by ICFB Requested by ICFC Requested by ICFD Requested by OCFA Requested by OCFB Requested by OVF DTC Activation Possible Possible Not possible Not possible Possible Possible Not possible Low Priority High 11.5 Sample Application In the example below, the free-running timer is used to generate pulse outputs with a 50% duty cycle and arbitrary phase relationship. The programming is as follows: * The CCLRA bit in TCSR is set to 1. * Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in TOCR (OLVLA or OLVLB). FRC H'FFFF OCRA OCRB H'0000 FTOA Counter clear FTOB Figure 11.17 Pulse Output (Example) 296 11.6 Usage Notes Application programmers should note that the following types of contention can occur in the free-running timer. Contention between FRC Write and Clear: If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.18 shows this type of contention. FRC write cycle T1 T2 o Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 11.18 FRC Write-Clear Contention 297 Contention between FRC Write and Increment: If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.19 shows this type of contention. FRC write cycle T1 T2 o Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 11.19 FRC Write-Increment Contention 298 Contention between OCR Write and Compare-Match: If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is inhibited. Figure 11.20 shows this type of contention. If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is inhibited. Consequently, the result of the automatic addition is not written to OCRA. OCRA or OCRB write cycle T1 T2 o Address OCR address Internal write signal FRC N N+1 OCR N M Write data Compare-match signal Inhibited Figure 11.20 Contention between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) 299 Switching of Internal Clock and FRC Operation: When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 11.5. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (o). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 11.5, the changeover is regarded as a falling edge that triggers the FRC increment clock pulse. Switching between an internal and external clock can also cause FRC to increment. Table 11.5 Switching of Internal Clock and FRC Operation Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low to low No. 1 FRC Operation Clock before switchover Clock after switchover FRC clock N+1 CKS bit rewrite FRC N 2 Switching from low to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite 300 Table 11.5 Switching of Internal Clock and FRC Operation (cont) Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to low No. 3 FRC Operation Clock before switchover Clock after switchover * FRC clock FRC N N+1 CKS bit rewrite N+2 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. 301 302 Section 12 8-Bit Timers 12.1 Overview The H8S/2138 Series and H8S/2134 Series include an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect comparematches. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of a rectangular-wave output with an arbitrary duty cycle. The H8S/2138 Series also has two similar 8-bit timer channels (TMRX and TMRY), and the H8S/2134 Series has one (TMRY). These channels can be used in a connected configuration using the timer connection function. TMRX and TMRY have greater input/output and interrupt function related restrictions than TMR0 and TMR1. 12.1.1 Features * Selection of clock sources TMR0, TMR1: The counter input clock can be selected from six internal clocks and an external clock (enabling use as an external event counter). TMRX, TMRY: The counter input clock can be selected from three internal clocks and an external clock (enabling use as an external event counter). * Selection of three ways to clear the counters The counters can be cleared on compare-match A or B, or by an external reset signal. * Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. (Note: TMRY does not have a timer output pin.) * Cascading of the two channels (TMR0, TMR1) Operation as a 16-bit timer can be performed using channel 0 as the upper half and channel 1 as the lower half (16-bit count mode). Channel 1 can be used to count channel 0 compare-match occurrences (compare-match count mode). * Multiple interrupt sources for each channel TMR0, TMR1, TMRY: Two compare-match interrupts and one overflow interrupt can be requested independently. TMRX: One input capture source is available. 303 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the 8-bit timer module (TMR0 and TMR1). TMRX and TMRY have a similar configuration, but cannot be cascaded. TMRX also has an input capture function. For details, see section 13, Timer Connection. External clock sources TMCI0 TMCI1 Internal clock sources TMR0 o/8, o/2 o/64, o/32 o/1024, o/256 TMR1 o/8, o/2 o/64, o/128 o/1024, o/2048 TMRX o o/2 o/4 TMRY o/4 o/256 o/2048 Clock 1 Clock 0 Clock select TCORA0 Compare-match A1 Compare-match A0 Comparator A0 Overflow 1 Overflow 0 Clear 0 Clear 1 Compare-match B1 Compare-match B0 Comparator B0 TMO1 TMRI1 Control logic TCORB0 TCORB1 Comparator B1 TCORA1 Comparator A1 TMO0 TMRI0 TCNT0 TCNT1 Internal bus TCSR0 TCSR1 TCR0 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals TCR1 Figure 12.1 Block Diagram of 8-Bit Timer Module 304 12.1.3 Pin Configuration Table 12.1 summarizes the input and output pins of the 8-bit timer module. Table 12.1 8-Bit Timer Input and Output Pins Channel 0 Name Timer output Timer clock input Timer reset input 1 Timer output Timer clock input Timer reset input X Timer output Timer clock/ reset input Y Timer clock/reset input Symbol* TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 TMOX I/O Output Input Input Output Input Input Output Function Output controlled by compare-match External clock input for the counter External reset input for the counter Output controlled by compare-match External clock input for the counter External reset input for the counter Output controlled by compare-match External clock/reset input for the counter External clock/reset input for the counter HFBACKI/TMIX Input (TMCIX/TMRIX) VSYNCI/TMIY Input (TMCIY/TMRIY) Note: * The abbreviations TMO, TMCI, and TMRI are used in the text, omitting the channel number. Channel X and Y I/O pins have the same internal configuration as channels 0 and 1, and therefore the same abbreviations are used. 305 12.1.4 Register Configuration Table 12.2 summarizes the registers of the 8-bit timer module. Table 12.2 8-Bit Timer Registers Channel 0 Name Abbreviation*3 R/W Initial value Timer control register 0 TCR0 R/W H'00 2 Timer control/status register 0 TCSR0 R/(W)* H'00 Time constant register A0 Time constant register B0 Time counter 0 1 Timer control register 1 Timer control/status register 1 Time constant register A1 Time constant register B1 Timer counter 1 Serial/timer control register Module stop control register Timer connection register S Timer control register X Timer control/status register X Time constant register AX Time constant register BX Timer counter X Time constant register C Input capture register R Input capture register F Y TCORA0 TCORB0 TCNT0 TCR1 TCSR1 TCORA1 TCORB1 TCNT1 STCR MSTPCRH MSTPCRL TCONRS TCRX TCSRX TCORAX TCORBX TCNTX TCORC TICRR TICRF R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R R 2 2 Address*1 H'FFC8 H'FFCA H'FFCC H'FFCE H'FFD0 H'FFC9 H'FFCB H'FFCD H'FFCF H'FFD1 H'FFC3 H'FF86 H'FF87 H'FFFE H'FFF0 H'FFF1 H'FFF6 H'FFF7 H'FFF4 H'FFF5 H'FFF2 H'FFF3 H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FF H'FF H'00 H'00 H'10 H'FF H'FF H'00 H'00 H'3F H'FF H'00 H'00 H'00 H'FF H'FF H'00 H'FF H'00 H'00 Common X Timer control register Y TCRY Timer control/status register Y TCSRY Time constant register AY Time constant register BY Timer counter Y TCORAY TCORBY TCNTY R/W H'00 2 R/(W)* H'00 R/W R/W R/W H'FF H'FF H'00 Timer input select register TISR R/W H'FE H'FFF5 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written in bits 7 to 5, to clear these flags. 3. The abbreviations TCR, TCSR, TCORA, TCORB, and TCNT are used in the text, omitting the channel designation (0, 1, X, or Y). 306 Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access. (Access is not divided into two 8-bit accesses.) Certain of the channel X and channel Y registers are assigned to the same address. The TMRX/Y bit in TCONRS determines which register is accessed. 12.2 12.2.1 Register Descriptions Timer Counter (TCNT) TCNT0 TCNT1 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNTX,TCNTY Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Each TCNT is an 8-bit readable/writable up-counter. TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word access. TCNT increments on pulses generated from an internal or external clock source. This clock source is selected by clock select bits CKS2 to CKS0 in TCR. TCNT can be cleared by an external reset input signal or compare-match signal. Counter clear bits CCLR1 and CCLR0 in TCR select the method of clearing. When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCSR is set to 1. The timer counters are initialized to H'00 by a reset and in hardware standby mode. 307 12.2.2 Time Constant Register A (TCORA) TCORA0 TCORA1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORAX, TCORAY Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TCORA is an 8-bit readable/writable register. TCORA0 and TCORA1 comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORA write cycle. The timer output can be freely controlled by these compare-match signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF by a reset and in hardware standby mode. 308 12.2.3 Time Constant Register B (TCORB) TCORB0 TCORB1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORBX, TCORBY Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TCORB is an 8-bit readable/writable register. TCORB0 and TCORB1 comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORB write cycle. The timer output can be freely controlled by these compare-match signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF by a reset and in hardware standby mode. 309 12.2.4 Bit Timer Control Register (TCR) 7 IEDGA 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3 BUFEA 0 R/W 2 BUFEB 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value Read/Write TCR is an 8-bit readable/writable register that selects the clock source and the time at which TCNT is cleared, and enables interrupts. TCR is initialized to H'00 by a reset and in hardware standby mode. For details of the timing, see section 12.3, Operation. Bit 7--Compare-Match Interrupt Enable B (CMIEB): Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. Note that a CMIB interrupt is not requested by TMRX, regardless of the CMIEB value. Bit 7 CMIEB 0 1 Description CMFB interrupt request (CMIB) is disabled CMFB interrupt request (CMIB) is enabled (Initial value) Bit 6--Compare-Match Interrupt Enable A (CMIEA): Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. Note that a CMIA interrupt is not requested by TMRX, regardless of the CMIEA value. Bit 6 CMIEA 0 1 Description CMFA interrupt request (CMIA) is disabled CMFA interrupt request (CMIA) is enabled (Initial value) 310 Bit 5--Timer Overflow Interrupt Enable (OVIE): Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. Note that an OVI interrupt is not requested by TMRX, regardless of the OVIE value. Bit 5 OVIE 0 1 Description OVF interrupt request (OVI) is disabled OVF interrupt request (OVI) is enabled (Initial value) Bits 4 and 3--Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select the method by which the timer counter is cleared: by compare-match A or B, or by an external reset input. Bit 4 CCLR1 0 Bit 3 CCLR0 0 1 1 0 1 Description Clearing is disabled Cleared on compare-match A Cleared on compare-match B Cleared on rising edge of external reset input (Initial value) 311 Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to TCNT is an internal or external clock. The input clock can be selected from either six or three clocks, all divided from the system clock (o). The falling edge of the selected internal clock triggers the count. When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. Some functions differ between channel 0 and channel 1, because of the cascading function. TCR STCR Bit 0 Bit 2 Bit 1 Bit 0 Bit 1 Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- Clock input disabled (Initial value) o/8 internal clock source, counted on the falling edge o/2 internal clock source, counted on the falling edge o/64 internal clock source, counted on the falling edge o/32 internal clock source, counted on the falling edge o/1024 internal clock source, counted on the falling edge o/256 internal clock source, counted on the falling edge Counted on TCNT1 overflow signal* Clock input disabled (Initial value) o/8 internal clock source, counted on the falling edge o/2 internal clock source, counted on the falling edge o/64 internal clock source, counted on the falling edge o/128 internal clock source, counted on the falling edge o/1024 internal clock source, counted on the falling edge o/2048 internal clock source, counted on the falling edge Counted on TCNT0 compare-match A* 312 TCR STCR Bit 0 Bit 2 Bit 1 Bit 0 Bit 1 Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description X 0 0 0 0 1 Y 0 0 0 0 1 Common 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Clock input disabled Counted on o internal clock source o/2 internal clock source, counted on the falling edge o/4 internal clock source, counted on the falling edge Clock input disabled Clock input disabled (Initial value) (Initial value) o/4 internal clock source, counted on the falling edge o/256 internal clock source, counted on the falling edge o/2048 internal clock source, counted on the falling edge Clock input disabled External clock source, counted at rising edge External clock source, counted at falling edge External clock source, counted at both rising and falling edges Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare-match signal, no incrementing clock will be generated. Do not use this setting. 313 12.2.5 TCSR0 Bit Timer Control/Status Register (TCSR) 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Initial value Read/Write TCSR1 Bit Initial value Read/Write TCSRX Bit Initial value Read/Write TCSRY Bit Initial value Read/Write 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICF 0 R/(W)* 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICIE 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Note: * Only 0 can be written in bits 7 to 5, and in bit 4 in TCSRX, to clear these flags. TCSR is an 8-bit register that indicates compare-match and overflow statuses (and input capture status in TMRX only), and controls compare-match output. TCSR0, TCSRX, and TCSRY are initialized to H'00, and TCSR1 is initialized to H'10, by a reset and in hardware standby mode. 314 Bit 7--Compare-Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match. Bit 7 CMFB 0 Description [Clearing conditions] * * 1 Read CMFB when CMFB = 1, then write 0 in CMFB When the DTC is activated by a CMIB interrupt (Initial value) [Setting condition] When TCNT = TCORB Bit 6--Compare-match Flag A (CMFA): Status flag indicating whether the values of TCNT and TCORA match. Bit 6 CMFA 0 Description [Clearing conditions] * * 1 Read CMFA when CMFA = 1, then write 0 in CMFA When the DTC is activated by a CMIA interrupt (Initial value) [Setting condition] When TCNT = TCORA Bit 5 --Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed from H'FF to H'00). Bit 5 OVF 0 1 Description [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] When TCNT overflows from H'FF to H'00 (Initial value) 315 TCSR0 Bit 4--A/D Trigger Enable (ADTE): Enables or disables A/D converter start requests by compare-match A. Bit 4 ADTE 0 1 Description A/D converter start requests by compare-match A are disabled A/D converter start requests by compare-match A are enabled (Initial value) TCSR1 Bit 4--Reserved: This bit cannot be modified and is always read as 1. TCSRX Bit 4--Input Capture Flag (ICF): Status flag that indicates detection of a rising edge followed by a falling edge in the external reset signal after the ICST bit in TCONRI has been set to 1. Bit 4 ICF 0 1 Description [Clearing condition] Read ICF when ICF = 1, then write 0 in ICF [Setting condition] When a rising edge followed by a falling edge is detected in the external reset signal after the ICST bit in TCONRI has been set to 1 (Initial value) TCSRY Bit 4--Input Capture Interrupt Enable (ICIE): Selects enabling or disabling of the interrupt request by ICF (ICIX) when the ICF bit in TCSRX is set to 1. Bit 4 ICIE 0 1 Description Interrupt request by ICF (ICIX) is disabled Interrupt request by ICF (ICIX) is enabled (Initial value) 316 Bits 3 to 0--Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is to be changed by a compare-match of TCOR and TCNT. OS3 and OS2 select the effect of compare-match B on the output level, OS1 and OS0 select the effect of compare-match A on the output level, and both of them can be controlled independently. Note, however, that priorities are set such that: trigger output > 1 output > 0 output. If comparematches occur simultaneously, the output changes according to the compare-match with the higher priority. Timer output is disabled when bits OS3 to OS0 are all 0. After a reset, the timer output is 0 until the first compare-match occurs. Bit 3 OS3 0 Bit 2 OS2 0 1 1 0 1 Bit 1 OS1 0 Bit 0 OS0 0 1 1 0 1 Description No change when compare-match A occurs 0 is output when compare-match A occurs 1 is output when compare-match A occurs Output is inverted when compare-match A occurs (toggle output) (Initial value) Description No change when compare-match B occurs 0 is output when compare-match B occurs 1 is output when compare-match B occurs Output is inverted when compare-match B occurs (toggle output) (Initial value) 317 12.2.6 Bit Serial/Timer Control Register (STCR) 7 IICS 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W 3 FLSHE 0 R/W 2 -- 0 R/W 1 ICKS1 0 R/W 0 ICKS0 0 R/W Initial value Read/Write STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), and on-chip flash memory (in F-ZTAT versions), and also selects the TCNT input clock. For details on functions not related to the 8-bit timers, see section 3.2.4, Serial/Timer Control Register (STCR), and the descriptions of the relevant modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4--I C Control (IICS, IICX1, IICX0, IICE): These bits control the operation of the 2 2 I C bus interface when the IIC option is included on-chip. See section 16, I C Bus Interface, for details. Bit 3--Flash Memory Control Register Enable (FLSHE): Controls the operation of the flash memory in F-ZTAT versions. See section 21, ROM, for details. Bit 2--Reserved: Do not write 1 to this bit. Bits 1 and 0--Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12.2.4, Timer Control Register. 2 318 12.2.7 Bit System Control Register (SYSCR) 7 CS2E 0 R/W 6 IOSE 0 R/W 5 INTM1 0 R 4 INTM0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W Initial value Read/Write Only bit 1 is described here. For details on functions not related to the 8-bit timers, see sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules. Bit 1--Host Interface Enable (HIE): Controls CPU access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers. Bit 1 HIE 0 1 Description CPU access to 8-bit timer (channel X and Y) data registers and control (Initial value) registers, and timer connection control registers, is enabled CPU access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers, is disabled 319 12.2.8 Bit Timer Connection Register S (TCONRS) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W TMRX/Y ISGENE HOMOD1HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0 Initial value Read/Write TCONRS is an 8-bit readable/writable register that controls access to the TMRX and TMRY registers and timer connection operation. TCONRS is initialized to H'00 by a reset and in hardware standby mode. Bit 7--TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be accessed when the HIE bit in SYSCR is cleared to 0. In the H8S/2138 Series, some of the TMRX registers and the TMRY registers are assigned to the same memory space addresses (H'FFF0 to H'FFF5), and the TMRX/Y bit determines which registers are accessed. In the H8S/2134 Series, there is no control of TMRY register access by this bit. Bit 7 TMRX/Y Accessible Registers H'FFF0 H'FFF1 TMRX TCSRX TMRY TCSRY H'FFF2 TMRX TICRR TMRY H'FFF3 TMRX TICRF TMRY H'FFF4 TMRX TCNTX TMRY H'FFF5 TMRX TCORC TMRY TISR H'FFF6 TMRX H'FFF7 TMRX 0 TMRX (Initial value) TCRX 1 TMRY TCRY TCORAX TCORBX TCORAY TCORBY TCNTY 320 12.2.9 Bit Input Capture Register (TICR) [TMRX Additional Function] 7 0 -- 6 0 -- 5 0 -- 4 0 -- 3 0 -- 2 0 -- 1 0 -- 0 0 -- Initial value Read/Write TICR is an 8-bit internal register to which the contents of TCNT are transferred on the falling edge of external reset input. The CPU cannot read or write to TICR directly. The TICR function is used in timer connection. For details, see section 13, Timer Connection. 12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function] Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TCORC is an 8-bit readable/writable register. The sum of the contents of TCORC and TICR is continually compared with the value in TCNT. When a match is detected, a compare-match C signal is generated. Note, however, that comparison is disabled during the T2 state of a TCORC write cycle and a TICR input capture cycle. TCORC is initialized to H'FF by a reset and in hardware standby mode. The TCORC function is used in timer connection. For details, see section 13, Timer Connection. 12.2.11 Input Capture Registers R and F (TICRR, TICRF) [TMRX Additional Functions] Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R TICRR and TICRF are 8-bit read-only registers. When the ICST bit in TCONRI is set to 1, TICRR and TICRF capture the contents of TCNT successively on the rise and fall of the external reset input. When one capture operation ends, the ICST bit is cleared to 0. TICRR and TICRF are each initialized to H'00 by a reset and in hardware standby mode. 321 The TICRR and TICRF functions are used in timer connection. For details, see section 13, Timer Connection. 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function] Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 IS 0 R/W TISR is an 8-bit readable/writable register that selects the external clock/reset signal source for the counter. TISR is initialized to H'FE by a reset and in hardware standby mode. Bits 7 to 1--Reserved: Do not write 0 to these bits. Bit 0--Input Select (IS): Selects the internal synchronization signal (IVG signal) or the timer clock/reset input pin (VSYNCI/TMIY (TMCIY/TMRIY)) as the external clock/reset signal source for the counter. Bit 0 IS 0 1 Description IVG signal is selected (H8S/2138 Series) External clock/reset input is disabled (H8S/2134 Series) VSYNCI/TMIY (TMCIY/TMRIY) is selected (Initial value) 322 12.2.13 Module Stop Control Register (MSTPCR) MSTPCRH Bit Initial value Read/Write 7 6 5 4 3 2 1 0 7 6 5 MSTPCRL 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. When the MSTP12 bit or MSTP8 bit is set to 1, 8-bit timer operation is halted on channels 0 and 1 or channels X and Y, respectively, and a transition is made to module stop mode. For details, see section 23.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 4--Module Stop (MSTP12): Specifies 8-bit timer (channel 0/1) module stop mode. MSTPCRH Bit 4 MSTP12 0 1 Description 8-bit timer (channel 0/1) module stop mode is cleared 8-bit timer (channel 0/1) module stop mode is set (Initial value) MSTPCRH Bit 0--Module Stop (MSTP8): Specifies 8-bit timer (channel X/Y) and timer connection module stop mode. MSTPCRH Bit 0 MSTP8 0 1 Description 8-bit timer (channel X/Y) and timer connection module stop mode is cleared 8-bit timer (channel X/Y) and timer connection module stop mode is set (Initial value) 323 12.3 12.3.1 Operation TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: An internal clock created by dividing the system clock (o) can be selected by setting bits CKS2 to CKS0 in TCR. Figure 12.2 shows the count timing. o Internal clock TCNT input clock TCNT N-1 N N+1 Figure 12.2 Count Timing for Internal Clock Input External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising edge, the falling edge, and both rising and falling edges. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Figure 12.3 shows the timing of incrementation at both edges of an external clock signal. o External clock input pin TCNT input clock TCNT N-1 N N+1 Figure 12.3 Count Timing for External Clock Input 324 12.3.2 Compare-Match Timing Setting of Compare-Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match. The compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare-match signal is not generated until the next incrementation clock input. Figure 12.4 shows this timing. o TCNT N N+1 TCOR Compare-match signal N CMF Figure 12.4 Timing of CMF Setting Timer Output Timing: When compare-match A or B occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Depending on these bits, the output can remain the same, be set to 0, be set to 1, or toggle. Figure 12.5 shows the timing when the output is set to toggle at compare-match A. o Compare-match A signal Timer output pin Figure 12.5 Timing of Timer Output 325 Timing of Compare-Match Clear: TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.6 shows the timing of this operation. o Compare-match signal TCNT N H'00 Figure 12.6 Timing of Compare-Match Clear 12.3.3 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 12.7 shows the timing of this operation. o External reset input pin Clear signal TCNT N-1 N H'00 Figure 12.7 Timing of Clearing by External Reset Input 326 12.3.4 Timing of Overflow Flag (OVF) Setting OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 12.8 shows the timing of this operation. o TCNT H'FF H'00 Overflow signal OVF Figure 12.8 Timing of OVF Setting 12.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer mode) or compare-matches of 8-bit channel 0 can be counted by the timer of channel 1 (compare-match count mode). In this case, the timer operates as described below. 16-Bit Count Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. * Setting of compare-match flags The CMF flag in TCSR0 is set to 1 when a 16-bit compare-match occurs. The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare-match occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at comparematch, the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare-match occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has also been set. The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot be cleared independently. * Pin output Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the 16-bit compare-match conditions. 327 Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the lower 8-bit compare-match conditions. Compare-Match Count Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare-match A's for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel. Usage Note: If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. 12.4 Interrupt Sources The TMR0, TMR1, and TMRY 8-bit timers can generate three types of interrupt: comparematch A and B (CMIA and CMIB), and overflow (OVI). TMRX can generate only an ICIX interrupt. An interrupt is requested when the corresponding interrupt enable bit is set in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. It is also possible to activate the DTC by means of CMIA and CMIB interrupts from TMR0, TMR1 and TMRY. An overview of 8-bit timer interrupt sources is given in tables 12.3 to 12.5. Table 12.3 TMR0 and TMR1 8-Bit Timer Interrupt Sources Interrupt source CMIA CMIB OVI Description Requested by CMFA Requested by CMFB Requested by OVF DTC Activation Possible Possible Not possible Low Interrupt Priority High Table 12.4 TMRX 8-Bit Timer Interrupt Source Interrupt source ICIX Description Requested by ICF DTC Activation Not possible 328 Table 12.5 TMRY 8-Bit Timer Interrupt Sources Interrupt source CMIA CMIB OVI Description Requested by CMFA Requested by CMFB Requested by OVF DTC Activation Possible Possible Not possible Low Interrupt Priority High 12.5 8-Bit Timer Application Example In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12.9. The control bits are set as follows: * In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared by a TCORA compare-match. * In TCSR, bits OS3 to OS0 are set to B'0110, causing 1 output at a TCORA compare-match and 0 output at a TCORB compare-match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF TCORA TCORB H'00 TMO Counter clear Figure 12.9 Pulse Output (Example) 329 12.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8bit timer module. 12.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.10 shows this operation. TCNT write cycle by CPU T1 T2 o Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 12.10 Contention between TCNT Write and Clear 330 12.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12.11 shows this operation. TCNT write cycle by CPU T1 T2 o Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.11 Contention between TCNT Write and Increment 331 12.6.3 Contention between TCOR Write and Compare-Match During the T2 state of a TCOR write cycle, the TCOR write has priority even if a comparematch occurs and the compare-match signal is disabled. Figure 12.12 shows this operation. With TMRX, an ICR input capture contends with a compare-match in the same way as with a write to TCORC. In this case, the input capture has priority and the compare-match signal is inhibited. TCOR write cycle by CPU T1 T2 o Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare-match signal Inhibited Figure 12.12 Contention between TCOR Write and Compare-Match 332 12.6.4 Contention between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 12.6. Table 12.6 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High 12.6.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12.7 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 12.7, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. Erroneous incrementation can also happen when switching between internal and external clocks. 333 Table 12.7 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low 1 to low* No. 1 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N CKS bit rewrite N+1 2 Switching from low 2 to high* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite 334 Table 12.7 Switching of Internal Clock and TCNT Operation (cont) Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high 3 to low* No. 3 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock *4 TCNT N N+1 CKS bit rewrite N+2 4 Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 335 336 Section 13 Timer Connection [H8S/2138 Series] Provided in the H8S/2138 Series; not provided in the H8S/2134 Series. 13.1 Overview The H8S/2138 Series allows interconnection between a combination of input signals, the input/output of the single free-running timer (FRT) channel and the three 8-bit timer channels (TMR1, TMRX, and TMRY). This capability can be used to implement complex functions such as PWM decoding and clamp waveform output. All the timers are initially set for independent operation. 13.1.1 Features The features of the timer connection facility are as follows. * Five input pins and four output pins, all of which can be designated for phase inversion. Positive logic is assumed for all signals used within the timer connection facility. * An edge-detection circuit is connected to the input pins, simplifying signal input detection. * TMRX can be used for PWM input signal decoding and clamp waveform generation. * An external clock signal divided by TMR1 can be used as the FRT capture input signal. * An internal synchronization signal can be generated using the FRT and TMRY. * A signal generated/modified using an input signal and timer connection can be selected and output. 337 338 VSYNCI/ FTIA/TMIY VFBACKI/ FTIB SET sync RES VSYNC modify FRT output selection VSYNCO/ FTOA SET IVG signal FTIA 16-bit FRT FTOA Phase inversion Edge detection Phase inversion IVI signal selection IVO signal selection IVI signal Edge detection Phase inversion READ flag FTIC FTID FRT input selection FTIB OCRA +VR, +VF CMA(R) FTIC ICRD +1M, +2M CMA(F) compare match FTOB FTID CM1M CM2M RES VSYNC generation SET RES 2f H mask generation 2f H mask/flag IVO signal TMIY signal selection TMRI/TMCI 8-bit TMRY TMO phase inversion IHG signal CBLANK waveform generation CBLANK IHO signal selection CMB TMCI 8-bit TMR1 TMO TMRI PDC signal PWM decoding HSYNCI/ TMCI1 IHI signal TMCI TMRI CM1C 8-bit TMRX ICR ICR +1C compare match CMB TMO CMA CL signal selection READ flag CLAMP waveform generation CL1 signal CL2 signal CL3 signal CL4 signal IHI signal selection Edge detection Edge detection Phase inversion Edge detection Phase inversion CSYNCI/ TMRI1 HFBACKI/ FTCI/TMIX Phase inversion CL4 generation TMOX phase inversion TMO1 output selection TMR1 input selection HSYNCO/ TMO1 Phase inversion CLAMPO/ FTIC 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the timer connection facility. Figure 13.1 Block Diagram of Timer Connection Facility 13.1.3 Input and Output Pins Table 13.1 lists the timer connection input and output pins. Table 13.1 Timer Connection Input and Output Pins Name Vertical synchronization signal input pin Horizontal synchronization signal input pin Composite synchronization signal input pin Spare vertical synchronization signal input pin Spare horizontal synchronization signal input pin Vertical synchronization signal output pin Horizontal synchronization signal output pin Clamp waveform output pin Blanking waveform output pin Abbreviation VSYNCI Input/ Output Input Function Vertical synchronization signal input pin or FTIA input pin/TMIY input pin Horizontal synchronization signal input pin or TMCI1 input pin Composite synchronization signal input pin or TMRI1 input pin Spare vertical synchronization signal input pin or FTIB input pin Spare horizontal synchronization signal input pin or FTCI input pin/TMIX input pin Vertical synchronization signal output pin or FTOA output pin Horizontal synchronization signal output pin or TMO1 output pin Clamp waveform output pin or FTIC input pin Blanking waveform output pin HSYNCI CSYNCI VFBACKI Input Input Input HFBACKI Input VSYNCO HSYNCO CLAMPO CBLANK Output Output Output Output 339 13.1.4 Register Configuration Table 13.2 lists the timer connection registers. Timer connection registers can only be accessed when the HIE bit in SYSCR is 0. Table 13.2 Register Configuration Name Timer connection register I Timer connection register O Timer connection register S Edge sense register Module stop control register Abbreviation TCONRI TCONRO TCONRS SEDGR MSTPRH MSTPRL R/W R/W R/W R/W R/(W)* R/W R/W 2 Initial Value H'00 H'00 H'00 H'00* H'3F H'FF 3 Address*1 H'FFFC H'FFFD H'FFFE H'FFFF H'FF86 H'FF87 Notes: 1. Lower 16 bits of the address. 2. Bits 7 to 2: Only 0 can be written to clear the flags. 3. Bits 1 and 0: Undefined (reflect the pin states). 13.2 13.2.1 Bit Register Descriptions Timer Connection Register I (TCONRI) 7 0 R/W 6 0 R/W 5 0 R/W 4 ICST 0 R/W 3 HFINV 0 R/W 2 VFINV 0 R/W 1 HIINV 0 R/W 0 VIINV 0 R/W SIMOD1 SIMOD0 SCONE Initial value Read/Write TCONRI is an 8-bit readable/writable register that controls connection between timers, the signal source for synchronization signal input, phase inversion, etc. TCONR1 is initialized to H'00 by a reset and in hardware standby mode. 340 Bits 7 and 6--Input Synchronization Mode Select 1 and 0 (SIMOD1, SIMOD0): These bits select the signal source of the IHI and IVI signals. Bit 7 SIMOD1 0 Bit 6 SIMOD0 0 1 1 0 1 Mode No signal S-on-G mode Composite mode Separate mode Description IHI Signal (Initial value) HFBACKI input CSYNCI input HSYNCI input HSYNCI input IVI Signal VFBACKI input PDC input PDC input VSYNCI input Bit 5--Synchronization Signal Connection Enable (SCONE): Selects the signal source of the FRT FTI input and the TMR1 TMCI1/TMRI1 input. Bit 5 SCONE 0 1 Mode Description FTIA FTIB FTIB input TMO1 signal FTIC FTIC input FTID FTID input TMCI1 TMRI1 TMCI1 TMRI1 input input IHI signal IVI inverse signal Normal connection (Initial value) FTIA input Synchronization signal connection mode IVI signal VFBACKI IHI input signal Bit 4--Input Capture Start Bit (ICST): The TMRX external reset input (TMRIX) is connected to the IHI signal. TMRX has input capture registers (TICR, TICRR, and TICRF). TICRR and TICRF can measure the width of a short pulse by means of a single capture operation under the control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF, respectively, and the ICST bit is cleared to 0. Bit 4 ICST 0 Description The TICRR and TICRF input capture functions are stopped [Clearing condition] When a rising edge followed by a falling edge is detected on TMRIX 1 The TICRR and TICRF input capture functions are operating (Waiting for detection of a rising edge followed by a falling edge on TMRIX) [Setting condition] When 1 is written in ICST after reading ICST = 0 (Initial value) 341 Bits 3 to 0--Input Synchronization Signal Inversion (HFINV, VFINV, HIINV, VIINV): These bits select inversion of the input phase of the spare horizontal synchronization signal (HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal synchronization signal and composite synchronization signal (HSYNCI, CSYNCI), and the vertical synchronization signal (VSYNCI). Bit 3 HFINV 0 1 Bit 2 VFINV 0 1 Bit 1 HIINV 0 1 Description The HSYNCI and CSYNCI pin states are used directly as the HSYNCI and CSYNCI inputs (Initial value) The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and CSYNCI inputs Description The VFBACKI pin state is used directly as the VFBACKI input The VFBACKI pin state is inverted before use as the VFBACKI input (Initial value) Description The HFBACKI pin state is used directly as the HFBACKI input The HFBACKI pin state is inverted before use as the HFBACKI input (Initial value) Bit 0 VIINV 0 1 Description The VSYNCI pin state is used directly as the VSYNCI input The VSYNCI pin state is inverted before use as the VSYNCI input (Initial value) 342 13.2.2 Bit Timer Connection Register O (TCONRO) 7 HOE 0 R/W 6 VOE 0 R/W 5 CLOE 0 R/W 4 CBOE 0 R/W 3 HOINV 0 R/W 2 VOINV 0 R/W 1 0 R/W 0 0 R/W CLOINV CBOINV Initial value Read/Write TCONRO is an 8-bit readable/writable register that controls output signal output, phase inversion, etc. TCONRO is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 4--Output Enable (HOE, VOE, CLOE, CBOE): These bits control enabling/disabling of horizontal synchronization signal (HSYNCO), vertical synchronization signal (VSYNCO), clamp waveform (CLAMPO), and blanking waveform (CBLANK) output. When output is disabled, the state of the relevant pin is determined by the port DR and DDR, FRT, TMR, and PWM settings. Output enabling/disabling control does not affect the port, FRT, or TMR input functions, but some FRT and TMR input signal sources are determined by the SCONE bit in TCONRI. Bit 7 HOE 0 1 Bit 6 VOE 0 1 Bit 5 CLOE 0 1 Description The P64/FTIC/.,1/CIN4/CLAMPO pin functions as the P64/FTIC/.,1/CIN4 pin The P64/FTIC/.,1/CIN4/CLAMPO pin functions as the CLAMPO pin (Initial value) Description The P61/FTOA/.,1/CIN1/VSYNCO pin functions as the P61/FTOA/ .,1/CIN1 pin The P61/FTOA/.,1/CIN1/VSYNCO pin functions as the VSYNCO pin (Initial value) Description The P44/TMO1/HIRQ1/HSYNCO pin functions as the P44/TMO1/ HIRQ1 pin The P44/TMO1/HIRQ1/HSYNCO pin functions as the HSYNCO pin (Initial value) 343 Bit 4 CBOE 0 1 Description The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin In mode 1 (expanded mode with on-chip ROM disabled): The P27/A15/PW15/CBLANK pin functions as the A15 pin In modes 2 and 3 (modes with on-chip ROM enabled): The P27/A15/PW15/CBLANK pin functions as the CBLANK pin (Initial value) Bits 3 to 0--Output Synchronization Signal Inversion (HOINV, VOINV, CLOINV, CBOINV): These bits select inversion of the output phase of the horizontal synchronization signal (HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO), and the blank waveform (CBLANK). Bit 3 HOINV 0 1 Bit 2 VOINV 0 1 Bit 1 CLOINV 0 1 Description The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the (Initial value) CLAMPO output The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as the CLAMPO output Description The IVO signal is used directly as the VSYNCO output The IVO signal is inverted before use as the VSYNCO output (Initial value) Description The IHO signal is used directly as the HSYNCO output The IHO signal is inverted before use as the HSYNCO output (Initial value) Bit 0 CBOINV 0 1 Description The CBLANK signal is used directly as the CBLANK output The CBLANK signal is inverted before use as the CBLANK output (Initial value) 344 13.2.3 Bit Timer Connection Register S (TCONRS) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W TMRX/Y ISGENE HOMOD1 HOMOD0VOMOD1 VOMOD0 CLMOD1 CLMOD0 Initial value Read/Write TCONRS is an 8-bit readable/writable register that selects 8-bit timer TMRX/TMRY access and the synchronization signal output signal source and generation method. TCONRS is initialized to H'00 by a reset and in hardware standby mode. Bit 7--TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be accessed when the HIE bit in SYSCR is cleared to 0. In the H8S/2138 Series, some of the TMRX registers and the TMRY registers are assigned to the same memory space addresses (H'FFF0 to H'FFF5), and the TMRX/Y bit determines which registers are accessed. In the H8S/2134 Series, there is no control of TMRY register access by this bit. Bit 7 TMRX/Y 0 1 Description The TMRX registers are accessed at addresses H'FFF0 to H'FFF5 The TMRY registers are accessed at addresses H'FFF0 to H'FFF5 (Initial value) 345 Bit 6--Internal Synchronization Signal Select (ISGENE): Selects internal synchronization signals (IHG, IVG, and CL4 signals) as the signal sources for the IHO, IVO, and CLO signals. Bits 5 and 4--Horizontal Synchronization Output Mode Select 1 and 0 (HOMOD1, HOMOD0): These bits select the signal source and generation method for the IHO signal. Bit 6 ISGENE 0 Bit 5 VOMOD1 0 Bit 4 VOMOD0 0 1 1 0 1 1 0 0 1 1 0 1 The IHG signal is selected Description The IHI signal (without 2fH modification) is selected (Initial value) The IHI signal (with 2fH modification) is selected The CL1 signal is selected Bits 3 and 2--Vertical Synchronization Output Mode Select 1 and 0 (VOMOD1, VOMOD0): These bits select the signal source and generation method for the IVO signal. Bit 6 ISGENE 0 Bit 3 VOMOD1 0 Bit 2 VOMOD0 0 1 1 0 1 1 0 0 1 1 0 1 Description The IVI signal (without fall modification or IHI synchronization) is selected (Initial value) The IVI signal (without fall modification, with IHI synchronization) is selected The IVI signal (with fall modification, without IHI synchronization) is selected The IVI signal (with fall modification and IHI synchronization) is selected The IVG signal is selected 346 Bits 1 and 0--Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits select the signal source for the CLO signal (clamp waveform). Bit 6 ISGENE 0 Bit 1 CLMOD1 0 Bit 0 CLMOD2 0 1 1 0 1 1 0 0 1 1 0 1 The CL4 signal is selected Description The CL1 signal is selected The CL2 signal is selected The CL3 signal is selected (Initial value) 13.2.4 Bit Edge Sense Register (SEDGR) 7 VEDG 0 R/(W) *1 6 HEDG 0 R/(W) *1 5 CEDG 0 R/(W) *1 4 0 R/(W) *1 3 0 R/(W) *1 2 0 R/(W) *1 1 IHI --*2 R 0 IVI --*2 R HFEDG VFEDG PREQF Initial value Read/Write Notes: 1. Only 0 can be written, to clear the flags. 2. The initial value is undefined since it depends on the pin states. SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection input pins and the occurrence of 2fH modification, and to determine the phase of the IVI and IHI signals. The upper 6 bits of SEDGR are initialized to 0 by a reset and in hardware standby mode. The initial value of the lower 2 bits is undefined, since it depends on the pin states. Bit 7--VSYNCI Edge (VEDG): Detects a rising edge on the VSYNCI pin. Bit 7 VEDG 0 1 Description [Clearing condition] When 0 is written in VEDG after reading VEDG = 1 [Setting condition] When a rising edge is detected on the VSYNCI pin (Initial value) 347 Bit 6--HSYNCI Edge (HEDG): Detects a rising edge on the HSYNCI pin. Bit 6 HEDG 0 1 Description [Clearing condition] When 0 is written in HEDG after reading HEDG = 1 [Setting condition] When a rising edge is detected on the HSYNCI pin (Initial value) Bit 5--CSYNCI Edge (CEDG): Detects a rising edge on the CSYNCI pin. Bit 5 CEDG 0 1 Description [Clearing condition] When 0 is written in CEDG after reading CEDG = 1 [Setting condition] When a rising edge is detected on the CSYNCI pin (Initial value) Bit 4--HFBACKI Edge (HFEDG): Detects a rising edge on the HFBACKI pin. Bit 4 HFEDG 0 1 Description [Clearing condition] When 0 is written in HFEDG after reading HFEDG = 1 [Setting condition] When a rising edge is detected on the HFBACKI pin (Initial value) Bit 3--VFBACKI Edge (VFEDG): Detects a rising edge on the VFBACKI pin. Bit 3 VFEDG 0 1 Description [Clearing condition] When 0 is written in VFEDG after reading VFEDG = 1 [Setting condition] When a rising edge is detected on the VFBACKI pin (Initial value) 348 Bit 2--Pre-Equalization Flag (PREQF): Detects the occurrence of an IHI signal 2fH modification condition. The generation of a falling/rising edge in the IHI signal during a mask interval is expressed as the occurrence of a 2fH modification condition. For details, see section 13.3.4, IHI Signal 2fH Modification. Bit 2 PREQF 0 1 Description [Clearing condition] When 0 is written in PREQF after reading PREQF = 1 [Setting condition] When an IHI signal 2fH modification condition is detected (Initial value) Bit 1--IHI Signal Level (IHI): Indicates the current level of the IHI signal. Signal source and phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IHI signal at positive phase by modifying TCONRI. Bit 1 IHI 0 1 Description The IHI signal is low The IHI signal is high Bit 0--IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IVI signal at positive phase by modifying TCONRI. Bit 0 IVI 0 1 Description The IVI signal is low The IVI signal is high 349 13.2.5 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 Bit Initial value Read/Write 7 6 5 4 3 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP13, MSTP12, and MSTP8 bits are set to 1, the 16-bit free-running timer, 8-bit timer channels 0 and 1, and 8-bit timer channels X and Y and timer connection, respectively, halt and enter module stop mode. See section 23.5., Module Stop Mode, for details. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 5--Module Stop (MSTP13): Specifies FRT module stop mode. MSTPCRH Bit 5 MSTP13 0 1 Description FRT module stop mode is cleared FRT module stop mode is set (Initial value) MSTPCRH Bit 4--Module Stop (MSTP12): Specifies 8-bit timer channel 0 and 1 module stop mode. MSTPCRH Bit 4 MSTP12 0 1 Description 8-bit timer channel 0 and 1 module stop mode is cleared 8-bit timer channel 0 and 1 module stop mode is set (Initial value) 350 MSTPCRH Bit 0--Module Stop (MSTP8): Specifies 8-bit timer channel X and Y and timer connection module stop mode. MSTPCRH Bit 0 MSTP8 0 1 Description 8-bit timer channel X and Y and timer connection module stop mode is cleared 8-bit timer channel X and Y and timer connection module stop mode is (Initial value) set 13.3 13.3.1 Operation PWM Decoding (PDC Signal Generation) The timer connection facility and TMRX can be used to decode a PWM signal in which 0 and 1 are represented by the pulse width. To do this, a signal in which a rising edge is generated at regular intervals must be selected as the IHI signal. The timer counter (TCNT) in TMRX is set to count the internal clock pulses and to be cleared on the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI signal (the result of the pulse width decision) at the compare-match signal B timing after TCNT is reset by the rise of the IHI signal is output as the PDC signal. The pulse width setting using TICRR and TICRF of TMRX can be used to determine the pulse width decision threshold. Examples of TCR and TCORB settings are shown in tables 13.3 and 13.4, and the timing chart is shown in figure 13.2. Table 13.3 Examples of TCR Settings Bit(s) 7 6 5 4 and 3 2 to 0 Abbreviation CMIEB CMIEA OVIE CCLR1, CCLR0 CKS2 to CKS0 Contents 0 0 0 11 001 TCNT is cleared by the rising edge of the external reset signal (IHI signal) Incremented on internal clock: o Description Interrupts due to compare-match and overflow are disabled 351 Table 13.4 Examples of TCORB (Pulse Width Threshold) Settings o:10 MHz H'07 H'0F H'1F H'3F H'7F 0.8 s 1.6 s 3.2 s 6.4 s 12.8 s o: 12 MHz 0.67 s 1.33 s 2.67 s 5.33 s 10.67 s o: 16 MHz 0.5 s 1 s 2 s 4 s 8 s o: 20 MHz 0.4 s 0.8 s 1.6 s 3.2 s 6.4 s IHI signal PDC signal TCNT TCORB (threshold) Figure 13.2 Timing Chart for PWM Decoding 13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) The timer connection facility and TMRX can be used to generate signals with different duty cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal). Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the CL4 signal can be generated using TMRY. The CL1 signal rises simultaneously with the rise of the IHI signal, and when the CL1 signal is high, the CL2 signal rises simultaneously with the fall of the IHI signal. The fall of both the CL1 and the CL2 signal can be specified by TCORA. The rise of the CL3 signal can be specified as simultaneous with the sampling of the fall of the IHI signal using the system clock, and the fall of the CL3 signal can be specified by TCORC. The CL3 signal can also fall when the IHI signal rises. TCNT in TMRX is set to count internal clock pulses and to be cleared on the rising edge of the external reset signal (IHI signal). 352 The value to be used as the CL1 signal pulse width is written in TCORA. Write a value of H'02 or more in TCORA when internal clock o is selected as the TMRX counter clock, and a value or H'01 or more when o/2 is selected. When internal clock o is selected, the CL1 signal pulse width is (TCORA set value + 3 0.5). When the CL2 signal is used, the setting must be made so that this pulse width is greater than the IHI signal pulse width. The value to be used as the CL3 signal pulse width is written in TCORC. The TICR register in TMRX captures the value of TCNT at the inverse of the external reset signal edge (in this case, the falling edge of the IHI signal). The timing of the fall of the CL3 signal is determined by the sum of the contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes the fall timing set by the contents of TCORC, since the IHI signal will cause the CL3 signal to fall. Examples of TMRX TCR settings are the same as those in table 13.3. The clamp waveform timing charts are shown in figures 13.3 and 13.4. Since the rise of the CL1 and CL2 signals is synchronized with the edge of the IHI signal, and their fall is synchronized with the system clock, the pulse width variation is equivalent to the resolution of the system clock. Both the rise and the fall of the CL3 signal are synchronized with the system clock and the pulse width is fixed, but there is a variation in the phase relationship with the IHI signal equivalent to the resolution of the system clock. IHI signal CL1 signal CL2 signal TCNT TCORA Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals) 353 IHI signal CL3 signal TCNT TICR+TCORC TICR Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal) 13.3.3 Measurement of 8-Bit Timer Divided Waveform Period The timer connection facility, TMR1, and the free-running timer (FRT) can be used to measure the period of an IHI signal divided waveform. Since TMR1 can be cleared by a rising edge of the IVI signal, the rise and fall of the IHI signal divided waveform can be virtually synchronized with the IVI signal. This enables period measurement to be carried out efficiently. To measure the period of an IHI signal divided waveform, TCNT in TMR1 is set to count the external clock (IHI signal) pulses and to be cleared on the rising edge of the external reset signal (IVI signal). The value to be used as the division factor is written in TCORA, and the TMO output method is specified by the OS bits in TCSR. Examples of TCR and TCSR settings are shown in table 13.5, and the timing chart for measurement of the IVI signal and IHI signal divided waveform periods is shown in figure 13.5. The period of the IHI signal divided waveform is given by (ICRD(3) - ICRD(2)) x the resolution. 354 Table 13.5 Examples of TCR and TCSR Settings Register TCR in TMR1 Bit(s) 7 6 5 Abbreviation CMIEB CMIEA OVIE Contents 0 0 0 11 TCNT is cleared by the rising edge of the external reset signal (IVI signal) TCNT is incremented on the rising edge of the external clock (IHI signal) Not changed by compare-match B; output inverted by compare-match A (toggle output): division by 512 or when TCORB < TCORA, 1 output on compare-match B, and 0 output on compare-match A: division by 256 0: FRC value is transferred to ICRB on falling edge of input capture input B (IHI divided signal waveform) 1: FRC value is transferred to ICRB on rising edge of input capture input B (IHI divided signal waveform) 1 and 0 CKS1, CKS0 TCSR in FRT 0 CCLRA 01 0 FRC is incremented on internal clock: o/8 FRC clearing is disabled Description Interrupts due to compare-match and overflow are disabled 4 and 3 CCLR1, CCLR0 2 to 0 CKS2 to CKS0 101 TCSR in TMR1 3 to 0 OS3 to OS0 0011 1001 TCR in FRT 6 IEDGB 0/1 355 IVI signal IHI signal divided waveform ICRB(4) ICRB(3) ICRB(2) ICRB(1) FRC ICRB Figure 13.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods 13.3.4 IHI Signal and 2fH Modification By using the timer connection FRT, even if there is a part of the IHI signal with twice the frequency, this can be eliminated. In order for this function to operate properly, the duty cycle of the IHI signal must be approximately 30% or less, or approximately 70% or above. The 8-bit OCRDM contents or twice the OCRDM contents can be added automatically to the data captured in ICRD in the FRT, and compare-matches generated at these points. The interval between the two compare-matches is called a mask interval. A value equivalent to approximately 1/3 the IHI signal period is written in OCRDM. ICRD is set so that capture is performed on the rise of the IHI signal. Since the IHI signal supplied to the IHO signal selection circuit is normally set on the rise of the IHI signal and reset on the fall, its waveform is the same as that of the original IHI signal. When 2fH modification is selected, IHI signal edge detection is disabled during mask intervals. Capture is also disabled during these intervals. Examples of FRT TCR settings are shown in table 13.6, and the 2fH modification timing chart is shown in figure 13.6. 356 Table 13.6 Examples of TCR, TCSR, TCOR, and OCRDM Settings Register TCR in FRT Bit(s) 4 Abbreviation IEDGD Contents 1 Description FRC value is transferred to ICRD on the rising edge of input capture input D (IHI signal) FRC is incremented on internal clock: o/8 FRC clearing is disabled ICRD is set to the operating mode in which OCRDM is used 1 and 0 TCSR in FRT TCOR in FRT 0 7 CKS1, CKS0 CCLRA ICRDMS OCRDM7 to 0 01 0 1 OCRDM in FRT 7 to 0 H'01 to H'FF Specifies the period during which ICRD operation is masked IHI signal (without 2fH modification) IHI signal (with 2fH modification) Mask interval ICRD + OCRDM x 2 ICRD + OCRDM FRC ICRD Figure 13.6 2fH Modification Timing Chart 357 13.3.5 IVI Signal Fall Modification and IHI Synchronization By using the timer connection TMR1, the fall of the IVI signal can be shifted backward by the specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized with the rise of the IHI signal. To perform 8-bit timer divided waveform period measurement, TCNT in TMR1 is set to count external clock (IHI signal) pulses, and to be cleared on the rising edge of the external reset signal (inverse of the IVI signal). The number of IHI signal pulses until the fall of the IVI signal is written in TCORB. Since the IVI signal supplied to the IVO signal selection circuit is normally set on the rise of the IVI signal and reset on the fall, its waveform is the same as that of the original IVI signal. When fall modification is selected, a reset is performed on a TMR1 TCORB compare-match. The fall of the waveform generated in this way can be synchronized with the rise of the IHI signal, regardless of whether or not fall modification is selected. Examples of TMR1 TCORB, TCR, and TCSR settings are shown in table 13.7, and the fall modification/IHI synchronization timing chart is shown in figure 13.7. Table 13.7 Examples of TCORB, TCR, and TCSR Settings Register TCR in TMR1 Bit(s) 7 6 5 4 and 3 Abbreviation CMIEB CMIEA OVIE CCLR1, CCLR0 CKS2 to CKS0 OS3 to OS0 Contents 0 0 0 11 TCNT is cleared by the rising edge of the external reset signal (inverse of the IVI signal) TCNT is incremented on the rising edge of the external clock (IHI signal) Not changed by compare-match B; output inverted by compare-match A (toggle output) or when TCORB TCORA, 1 output on compare-match B, 0 output on comparematch A Compare-match on the 4th (example) rise of the IHI signal after the rise of the inverse of the IVI signal Description Interrupts due to compare-match and overflow are disabled 2 to 0 TCSR in TMR1 3 to 0 101 0011 1001 TOCRB in TMR1 H'03 (example) 358 IHI signal IVI signal (PDC signal) IVO signal (without fall modification, with IHI synchronization) IVO signal (with fall modification, without IHI synchronization) IVO signal (with fall modification and IHI synchronization) TCNT 0 1 2 3 4 5 TCNT = TCORB (3) Figure 13.7 Fall Modification/IHI Synchronization Timing Chart 13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) By using the timer connection FRT and TMRY, it is possible to automatically generate internal signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the IVG signal period in order to keep it constant. In addition, the CL4 signal can be generated in synchronization with the IHG signal. The contents of OCRA in the FRT are updated by the automatic addition of the contents of OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the 0 interval of the IVG signal is written in OCRAR, and a value corresponding to the 1 interval of the IVG signal is written in OCRAF. The IVG signal is set by a compare-match after an OCRAR addition, and reset by a compare-match after an OCRAF addition. The IHG signal is the TMRY 8-bit timer output. TMRY is set to count internal clock pulses, and to be cleared on TCORA compare-match, to fix the period and set the timer output. TCORB is set so as to reset the timer output. The IVG signal is connected as the TMRY reset input (TMRI), and the rise of the IVG signal can be treated in the same way as a TCORA comparematch. The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG signal, and has a 1 interval of 6 system clock periods. Examples of settings of TCORA, TCORB, TCR, and TCSR in TMRY, and OCRAR, OCRAF, and TCR in the FRT, are shown in table 13.8, and the IHG signal/IVG signal timing chart is shown in figure 13.8. 359 Table 13.8 Examples of OCRAR, OCRAF, TOCR, TCORA, TCORB, TCR, and TCSR Settings Register TCR in TMRY Bit(s) 7 6 5 4 and 3 2 to 0 TCSR in TMRY TOCRA in TMRY TOCRB in TMRY TCR in FRT OCRAR in FRT 1 and 0 CKS1, CKS0 3 to 0 Abbreviation CMIEB CMIEA OVIE CCLR1, CCLR0 Contents 0 0 0 01 TCNT is cleared by compare-match A TCNT is incremented on internal clock: o/4 0 output on compare-match B 1 output on compare-match A IHG signal period = o x 256 IHG signal 1 interval = o x 16 FRC is incremented on internal clock: o/8 IVG signal 0 interval = o x 262016 IVG signal 1 interval = o x 128 OCRA is set to the operating mode in which OCRAR and OCRAF are used IVG signal period = o x 262144 (1024 times IHG signal) Description Interrupts due to compare-match and overflow are disabled CKS2 to CKS0 001 OS3 to OS0 0110 H'3F (example) H'03 (example) 01 H'7FEF (example) H'000F (example) OCRAF in FRT TOCR in FRT 6 OCRAMS 1 360 IVG signal OCRA (1) = OCRA (0) + OCRAF OCRA FRC OCRA (2) = OCRA (1) + OCRAR OCRA (3) = OCRA (2) + OCRAF OCRA (4) = OCRA (3) + OCRAR 6 system clocks CL4 signal IHG signal TCORA TCORB TCNT 6 system clocks 6 system clocks Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart 361 13.3.7 HSYNCO Output With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IHI signal source and the waveform required by external circuitry. The meaning of the HSYNCO output in each mode is shown in table 13.9. Table 13.9 Meaning of HSYNCO Output in Each Mode Mode No signal IHI Signal HFBACKI input IHO Signal IHI signal (without 2fH modification) Meaning of IHO Signal HFBACKI input is output directly IHI signal (with 2fH Meaningless unless there is a double-frequency modification) part in the HFBACKI input CL1 signal IHG signal S-on-G mode CSYNCI input IHI signal (without 2fH modification) HFBACKI input 1 interval is changed before output Internal synchronization signal is output CSYNCI input (composite synchronization signal) is output directly IHI signal (with 2fH Double-frequency part of CSYNCI input modification) (composite synchronization signal) is eliminated before output CL1 signal CSYNCI input (composite synchronization signal) horizontal synchronization signal part is separated before output Internal synchronization signal is output HSYNCI input (composite synchronization signal) is output directly IHG signal Composite HSYNCI mode input IHI signal (without 2fH modification) IHI signal (with 2fH Double-frequency part of HSYNCI input modification) (composite synchronization signal) is eliminated before output CL1 signal HSYNCI input (composite synchronization signal) horizontal synchronization signal part is separated before output Internal synchronization signal is output HSYNCI input (horizontal synchronization signal) is output directly IHG signal Separate mode HSYNCI input IHI signal (without 2fH modification) IHI signal (with 2fH Meaningless unless there is a double-frequency modification) part in the HSYNCI input (horizontal synchronization signal) CL1 signal IHG signal HSYNCI input (horizontal synchronization signal) 1 interval is changed before output Internal synchronization signal is output 362 13.3.8 VSYNCO Output With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IVI signal source and the waveform required by external circuitry. The meaning of the VSYNCO output in each mode is shown in table 13.10. Table 13.10 Meaning of VSYNCO Output in Each Mode Mode No signal IVI Signal VFBACKI input IVO Signal IVI signal (without fall modification or IHI synchronization) IVI signal (without fall modification, with IHI synchronization) Meaning of IVO Signal VFBACKI input is output directly Meaningless unless VFBACKI input is synchronized with HFBACKI input IVI signal (with fall VFBACKI input fall is modified before output modification, without IHI synchronization) IVI signal (with fall modification and IHI synchronization) IVG signal S-on-G PDC signal mode or composite mode IVI signal (without fall modification or IHI synchronization) IVI signal (without fall modification, with IHI synchronization) VFBACKI input fall is modified and signal is synchronized with HFBACKI input before output Internal synchronization signal is output CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated before output CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, and signal is synchronized with CSYNCI/HSYNCI input before output IVI signal (with fall CSYNCI/HSYNCI input (composite modification, without IHI synchronization signal) vertical synchronization) synchronization signal part is separated, and fall is modified before output IVI signal (with fall modification and IHI synchronization) CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, fall is modified, and signal is synchronized with CSYNCI/HSYNCI input before output Internal synchronization signal is output IVG signal 363 Table 13.10 Meaning of VSYNCO Output in Each Mode (cont) Mode Separate mode IVI Signal VSYNCI input IVO Signal IVI signal (without fall modification or IHI synchronization) IVI signal (without fall modification, with IHI synchronization) Meaning of IVO Signal VSYNCI input (vertical synchronization signal) is output directly Meaningless unless VSYNCI input (vertical synchronization signal) is synchronized with HSYNCI input (horizontal synchronization signal) IVI signal (with fall VSYNCI input (vertical synchronization modification, without IHI signal) fall is modified before output synchronization) IVI signal (with fall modification and IHI synchronization) IVG signal VSYNCI input (vertical synchronization signal) fall is modified and signal is synchronized with HSYNCI input (horizontal synchronization signal) before output Internal synchronization signal is output 13.3.9 CBLANK Output Using the signals generated/selected with timer connection, it is possible to generate a waveform based on the composite synchronization signal (blanking waveform). One kind of blanking waveform is generated by combining HFBACKI and VFBACKI inputs, with the phase polarity made positive by means of bits HFINV and VFINV in TCONRI, with the IVO signal. The composition logic is shown in figure 13.9. HFBACKI input (positive) VFBACKI input (positive) Falling edge sensing Rising edge sensing IVO signal (positive) Reset Q Set CBLANK signal (positive) Figure 13.9 CBLANK Output Waveform Generation 364 Section 14 Watchdog Timer (WDT) 14.1 Overview The H8S/2138 Series and H8S/2134 Series have an on-chip watchdog timer with two channels (WDT0, WDT1) for monitoring system operation. The WDT outputs an overflow signal if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal or internal NMI interrupt signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer mode, an interval timer interrupt is generated each time the counter overflows. 14.1.1 Features WDT features are listed below. * Switchable between watchdog timer mode and interval timer mode WOVI interrupt generation in interval timer mode * Internal reset or internal interrupt generated when the timer counter overflows Choice of internal reset or NMI interrupt generation in watchdog timer mode * Choice of 8 (WDT0) or 16 (WDT1) counter input clocks Maximum WDT interval: system clock period x 131072 x 256 Subclock can be selected for the WDT1 input counter Maximum interval when the subclock is selected: subclock period x 256 x 256 365 14.1.2 Block Diagram Figures 14.1 (a) and (b) show block diagrams of WDT0 and WDT1. WOVI (interrupt request signal) Internal NMI interrupt request signal*2 Internal reset signal*1 Interrupt control Reset control Overflow Clock Clock select o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Internal clock source Internal bus TCNT TCSR Module bus Bus interface WDT Legend: TCSR: Timer control/status register TCNT: Timer counter Notes: 1. For the internal reset signal, the reset of the WDT that overflowed first has priority. 2. The internal NMI interrupt request signal can be output independently by either WDT0 or WDT1. The interrupt controller does not distinguish between NMI interrupt requests from WDT0 and WDT1. Figure 14.1 (a) Block Diagram of WDT0 366 WOVI (interrupt request signal) Internal NMI (interrupt request signal)*2 Internal reset signal*1 Interrupt control Reset control Overflow Clock Clock select o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Internal clock source oSUB/2 oSUB/4 oSUB/8 oSUB/16 oSUB/32 oSUB/64 oSUB/128 oSUB/256 TCNT TCSR Module bus Bus interface WDT Legend: TCSR: Timer control/status register TCNT: Timer counter Notes: 1. For the internal reset signal, the reset of the WDT that overflowed first has priority. 2. The internal NMI interrupt request signal can be output independently by either WDT0 or WDT1. The interrupt controller does not distinguish between NMI interrupt requests from WDT0 and WDT1. Figure 14.1 (b) Block Diagram of WDT1 14.1.3 Pin Configuration Table 14.1 describes the WDT input pin. Table 14.1 WDT Pin Name External subclock input pin Symbol EXCL I/O Input Function WDT1 prescaler counter input clock 367 Internal bus 14.1.4 Register Configuration The WDT has four registers, as summarized in table 14.2. These registers control clock selection, WDT mode switching, the reset signal, etc. Table 14.2 WDT Registers Address*1 Channel 0 Name Timer control/status register 0 Timer counter 0 1 Timer control/status register 1 Timer counter 1 Common System control register Abbreviation R/W TCSR0 TCNT0 TCSR1 TCNT1 SYSCR R/(W)* R/W R/(W)* R/W R/W 3 3 Initial Value H'00 H'00 H'00 H'00 H'09 Write*2 H'FFA8 H'FFA8 H'FFEA H'FFEA H'FFC4 Read H'FFA8 H'FFA9 H'FFEA H'FFEB H'FFC4 Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 14.2.4, Notes on Register Access. 3. Only 0 can be written in bit 7, to clear the flag. 14.2 14.2.1 Bit Register Descriptions Timer Counter (TCNT) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value Read/Write TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the TCNT value overflows (changes from H'FF to H'00), the OVF flag in TCSR is set to 1, and an internal reset, NMI interrupt, interval timer interrupt (WOVI), etc., can be generated, according to the mode selected by the WT/,7 bit and RST/10, bit. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. 368 Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 14.2.4, Notes on Register Access. 14.2.2 Timer Control/Status Register (TCSR) * TCSR0 Bit Initial value Read/Write 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 0 R/W 3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W RSTS RST/NMI Note: * Only 0 can be written, to clear the flag. * TCSR1 Bit Initial value Read/Write 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Only 0 can be written, to clear the flag. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 14.2.4, Notes on Register Access. 369 Bit 7--Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF to H'00. Bit 7 OVF 0 Description [Clearing conditions] * * 1 Write 0 in the TME bit Read TCSR when OVF = 1, then write 0 in OVFA (Initial value) [Setting condition] When TCNT overflows (changes from H'FF to H'00) (When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.) Bit 6--Timer Mode Select (WT/,7 Selects whether the WDT is used as a watchdog timer or ,7): interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI interrupt when TCNT overflows. Bit 6 WT/,7 ,7 0 1 Description Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer: Generates a reset or NMI interrupt when TCNT overflows (Initial value) Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT counts (Initial value) 370 TCSR0 Bit 4--Reset Select (RSTS): Reserved. This bit should not be set to 1. TCSR1 Bit 4--Prescaler Select (PSS): Selects the input clock source for TCNT in WDT1. For details, see the description of the CKS2 to CKS0 bits below. WDT1 TCSR Bit 4 PSS 0 1 Description TCNT counts o-based prescaler (PSM) divided clock pulses TCNT counts oSUB-based prescaler (PSS) divided clock pulses (Initial value) Bit 3--Reset or NMI (RST/10, Specifies whether an internal reset or NMI interrupt is 10,): requested on TCNT overflow in watchdog timer mode. Bit 3 RST/10, 10, 0 1 Description An NMI interrupt is requested An internal reset is requested (Initial value) Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source, obtained by dividing the system clock (o), or subclock (oSUB) for input to TCNT. * WDT0 input clock selection Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Clock o/2 (Initial value) o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Description Overflow Period* (when o = 20 MHz) 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. 371 * WDT1 input clock selection Bit 4 PSS 0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Description Overflow Period* (when o = 20 MHz and oSUB = 32.768 kHz) 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 15.6 ms 31.3 ms 62.5 ms 125 ms 250 ms 500 ms 1s 2s o/2 (Initial value) 25.6 s o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 oSUB/2 oSUB/4 oSUB/8 oSUB/16 oSUB/32 oSUB/64 oSUB/128 oSUB/256 Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. 372 14.2.3 Bit System Control Register (SYSCR) 7 CS2E 0 R/W 6 IOSE 0 R/W 5 INTM1 0 R 4 INTM0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W Initial value Read/Write Only bit 3 is described here. For details on functions not related to the watchdog timer, see sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules. Bit 3--External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a read-only bit. It is set to 1 by an external reset, and when the RST/10, bit is 1, is cleared to 0 by an internal reset due to watchdog timer overflow. Bit 3 XRST 0 1 Description Reset is generated by watchdog timer overflow Reset is generated by external reset input (Initial value) 373 14.2.4 Notes on Register Access The watchdog timer's TCNT and TCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR (Example of WDT0): These registers must be written to by a word transfer instruction. They cannot be written to with byte transfer instructions. Figure 14.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. TCNT write 15 Address: H'FFA8 H'5A 87 Write data 0 TCSR write 15 Address: H'FFA8 H'A5 87 Write data 0 Figure 14.2 Format of Data Written to TCNT and TCSR (Example of WDT0) Reading TCNT and TCSR (Example of WDT0): These registers are read in the same way as other registers. The read addresses are H'FFA8 for TCSR, and H'FFA9 for TCNT. 374 14.3 14.3.1 Operation Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/,7 and TME bits in TCSR to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before overflow occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, an internal reset or NMI interrupt request is generated. When the RST/10, bit is set to 1, the chip is reset for 518 system clock periods (518 o) by a counter overflow. This is illustrated in figure 14.3. When the RST/10, bit cleared to 0, an NMI interrupt request is generated by a counter overflow. An internal reset request from the watchdog timer and reset input from the 5(6 pin are handled via the same vector. The reset source can be identified from the value of the XRST bit in SYSCR. If a reset caused by an input signal from the 5(6 pin and a reset caused by WDT overflow occur simultaneously, the 5(6 pin reset has priority, and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are handled via the same vector. Simultaneous handling of a watchdog timer NMI interrupt request and an NMI pin interrupt request must therefore be avoided. TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 H'00 written to TCNT OVF = 1* WT/IT = 1 H'00 written TME = 1 to TCNT Time Internal reset signal 518 system clock periods WT/IT: Timer mode select bit TME: Timer enable bit OVF: Overflow flag Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0. Figure 14.3 Operation in Watchdog Timer Mode 375 14.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/,7 bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 14.4. This function can be used to generate interrupt requests at regular intervals. TCNT count H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Interval timer interrupt request generation Figure 14.4 Operation in Interval Timer Mode 14.3.3 Timing of Setting of Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 14.5. If NMI request generation is selected in watchdog timer mode, when TCNT overflows the OVF bit in TCSR is set to 1 and at the same time an NMI interrupt is requested. o TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 14.5 Timing of OVF Setting 376 14.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in watchdog timer mode, an overflow generates an NMI interrupt request. 14.5 14.5.1 Usage Notes Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.6 shows this operation. TCNT write cycle T1 T2 o Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.6 Contention between TCNT Write and Increment 377 14.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 14.5.4 Counter Value in Transitions between High-Speed Mode, Subactive Mode, and Watch Mode If the mode is switched between high-speed mode and subactive mode or between high-speed mode and watch mode when WDT1 is used as a realtime clock counter, an error will occur in the counter value when the internal clock is switched. When the mode is switched from high-speed mode to subactive mode or watch mode, the increment timing is delayed by approximately 2 or 3 clock cycles when the WDT1 control clock is switched from the main clock to the subclock. Also, since the main clock oscillator is halted during subclock operation, when the mode is switched from watch mode or subactive mode to high-speed mode, the clock is not supplied until internal oscillation stabilizes. As a result, after oscillation is started, counter incrementing is halted during the oscillation stabilization time set by bits STS2 to STS0 in SBYCR, and there is a corresponding discrepancy in the counter value. Caution is therefore required when using WDT1 as the realtime clock counter. No error occurs in the counter value while WDT1 is operating in the same mode. 378 Section 15 Serial Communication Interface (SCI, IrDA) 15.1 Overview The H8S/2138 Series and H8S/2134 Series are equipped with a 3-channel serial communication interface (SCI). The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). One of the three SCI channels can transmit and receive IrDA communication waveforms based on IrDA specification version 1.0. 15.1.1 Features SCI features are listed below. * Choice of asynchronous or synchronous serial communication mode Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error Synchronous mode Serial data communication is synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function One serial data transfer format Data length: 8 bits Receive error detection: Overrun errors detected 379 * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data * LSB-first or MSB-first transfer can be selected This selection can be made regardless of the communication mode (with the exception of 7-bit data transfer in asynchronous mode)* Note: * LSB-first transfer is used in the examples in this section. * Built-in baud rate generator allows any bit rate to be selected * Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin * Four interrupt sources Four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive error) that can issue requests independently The transmit-data-empty interrupt and receive-data-full interrupt can activate the data transfer controller (DTC) to execute data transfer 380 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR o Baud rate generator o/4 o/16 o/64 Clock TxD Parity generation Parity check SCK External clock TEI TXI RXI ERI Legend: RSR: RDR: TSR: TDR: SMR: SCR: SSR: SCMR: BRR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Serial interface mode register Bit rate register Figure 15.1 Block Diagram of SCI 381 15.1.3 Pin Configuration Table 15.1 shows the serial pins used by the SCI. Table 15.1 SCI Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol* SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2/IrRxD TxD2/IrTxD I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input (normal/IrDA) SCI2 transmit data output (normal/IrDA) Note: * The abbreviations SCK, RxD, and TxD are used in the text, omitting the channel number. 382 15.1.4 Register Configuration The SCI has the internal registers shown in table 15.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. Table 15.2 SCI Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W 2 2 2 Initial Value Address*1 3 H'00 H'FFD8* H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'3F H'FF H'FFD9* H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE* H'FF88* H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E* H'FFA0* H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6* H'FEE4 H'FF86 H'FF87 3 3 3 3 3 3 3 3 Receive data register 0 RDR0 Serial interface mode register 0 SCMR0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 SMR1 BRR1 SCR1 TDR1 SSR1 H'FF89* Receive data register 1 RDR1 Serial interface mode register 1 SCMR1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 SMR2 BRR2 SCR2 TDR2 SSR2 H'FFA1* Receive data register 2 RDR2 Serial interface mode register 2 SCMR2 Keyboard comparator control register Module stop control register KBCOMP MSTPCRH MSTPCRL Common Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, to clear flags. 3. Some serial communication interface registers are assigned to the same addresses as other registers. In this case, register selection is performed by the IICE bit in the serial timer control register (STCR). 383 15.2 15.2.1 Bit Register Descriptions Receive Shift Register (RSR) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- Read/Write RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 15.2.2 Bit Initial value Read/Write Receive Data Register (RDR) 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receiveenabled. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. 384 15.2.3 Bit Transmit Shift Register (TSR) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- Read/Write TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 15.2.4 Bit Initial value Read/Write Transmit Data Register (TDR) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. 385 15.2.5 Bit Serial Mode Register (SMR) 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value Read/Write SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7--Communication Mode (C/): Selects asynchronous mode or synchronous mode as the SCI operating mode. Bit 7 C/ 0 1 Description Asynchronous mode Synchronous mode (Initial value) Bit 6--Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and LSB-first/MSBfirst selection is not available. 386 Bit 5--Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE 0 1 Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/ bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/ bit. Bit 4--Parity Mode (O/): Selects either even or odd parity for use in parity addition and checking. The O/ bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/ bit setting is invalid in synchronous mode, when parity bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. Bit 4 O/ 0 1 Description Even parity* Odd parity* 2 1 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 387 Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 stop bit* 1 (Initial value) 2 2 stop bits* Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/ bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) 388 Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from o, o/4, o/16, and o/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.8, Bit Rate Register. Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description o clock o/4 clock o/16 clock o/64 clock (Initial value) 15.2.6 Bit Serial Control Register (SCR) 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value Read/Write SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE 0 1 Description Transmit-data-empty interrupt (TXI) request disabled* Transmit-data-empty interrupt (TXI) request enabled (Initial value) Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. 389 Bit 6--Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE 0 1 Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled* (Initial value) Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE 0 1 Description Transmission disabled* Transmission enabled* 1 (Initial value) 2 Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmission format before setting the TE bit to 1. Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE 0 1 Description Reception disabled* Reception enabled* 1 (Initial value) 2 Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR setting must be performed to decide the reception format before setting the RE bit to 1. 390 Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] * * 1 When the MPIE bit is cleared to 0 When data with MPB = 1 is received (Initial value) Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data with MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Bit 2--Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt (TEI) request generation if there is no valid transmit data in TDR when the MSB is transmitted. Bit 2 TEIE 0 1 Description Transmit-end interrupt (TEI) request disabled* Transmit-end interrupt (TEI) request enabled* (Initial value) Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. 391 Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of external clock operation (CKE1 = 1). The setting of bits CKE1 and CKE0 must be carried out before the SCI's operating mode is determined using SMR. For details of clock source selection, see table 15.9 in section 15.3, Operation. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as I/O port* 1 Internal clock/SCK pin functions as serial clock 1 output* Internal clock/SCK pin functions as clock output* Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input* External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input* External clock/SCK pin functions as serial clock input 3 3 2 Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. 392 15.2.7 Bit Serial Status Register (SSR) 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value Read/Write Note: Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7--Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 Description [Clearing conditions] * When 0 is written in TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR (Initial value) [Setting conditions] * When the TE bit in SCR is 0 * 1 When data is transferred from TDR to TSR and data can be written to TDR 393 Bit 6--Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF 0 Description [Clearing conditions] * When 0 is written in RDRF after reading RDRF = 1 * (Initial value) When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Bit 5--Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER 0 1 Description [Clearing condition] When 0 is written in ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1* 2 1 (Initial value)* Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. 394 Bit 4--Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 1 Description [Clearing condition] When 0 is written in FER after reading FER = 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception 2 ends, and the stop bit is 0 * Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. (Initial value)* 1 Bit 3--Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 1 Description [Clearing condition] When 0 is written in PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does 2 not match the parity setting (even or odd) specified by the O/ bit in SMR* Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. (Initial value)* 1 395 Bit 2--Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND 0 Description [Clearing conditions] * * 1 * * When 0 is written in TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and writes data to TDR (Initial value) When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Setting conditions] Bit 1--Multiprocessor Bit (MPB): When reception is performed using a multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB 0 1 Description [Clearing condition] When data with a 0 multiprocessor bit is received (Initial value)* [Setting condition] When data with a 1 multiprocessor bit is received Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Bit 0--Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting, and in synchronous mode. Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) 396 15.2.8 Bit Bit Rate Register (BRR) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value Read/Write BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 15.3 shows sample BRR settings in asynchronous mode, and table 15.4 shows sample BRR settings in synchronous mode. 397 Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency o (MHz) o = 2 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- o = 2.097152 MHz Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- -- o = 2.4576 MHz Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 o = 3 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- n 1 1 0 0 0 0 0 0 -- -- -- N 148 108 217 108 54 26 13 6 -- -- -- n 1 1 0 0 0 0 0 0 0 -- 0 N 174 127 255 127 63 31 15 7 3 -- 1 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- Operating Frequency o (MHz) o = 3.6864 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 o = 4 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- o = 4.9152 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 o = 5 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 398 Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (cont) Operating Frequency o (MHz) o = 6 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 o = 6.144 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 o = 7.3728 MHz Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 o = 8 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 n 2 2 1 1 0 0 0 0 0 -- 0 N 130 95 191 95 191 95 47 23 11 -- 5 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- Operating Frequency o (MHz) o = 9.8304 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 o = 10 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 o = 12 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 o = 12.288 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 399 Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (cont) Operating Frequency o (MHz) o = 14 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 -- o = 14.7456 MHz Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 o = 16 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 o = 17.2032 MHz Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 Operating Frequency o (MHz) o = 18 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 o = 19.6608 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 o = 20 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 n 3 2 2 1 1 0 0 0 0 0 0 N 86 255 127 255 127 255 127 63 31 19 15 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 400 Table 15.4 BRR Settings for Various Bit Rates (Synchronous Mode) Operating Frequency o (MHz) Bit Rate (bits/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M n 3 2 1 1 0 0 0 0 0 0 0 0 o = 2 MHz N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 o = 4 MHz N -- 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* -- -- -- 1 1 0 0 0 0 0 0 -- -- -- 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* n o = 8 MHz N n o = 10 MHz N n o = 16 MHz N n o = 20 MHz N Note: As far as possible, the setting should be made so that the error is no more than 1%. Legend: Blank: Cannot be set. --: Can be set, but there will be a degree of error. *: Continuous transfer is not possible. 401 The BRR setting is found from the following equations. Asynchronous mode: N= x 106 - 1 64 x 22n-1 x B Synchronous mode: N= x 106 - 1 8 x 22n-1 x B Where B: N: o: n: Bit rate (bits/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n 0 1 2 3 Clock o o/4 o/16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following equation: x 106 Error (%) = - 1 x 100 2n-1 (N + 1) x B x 64 x 2 402 Table 15.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) o (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 403 Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) o (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bits/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 404 Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) o (MHz) 2 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bits/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 15.2.9 Bit Serial Interface Mode Register (SCMR) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Initial value Read/Write SCMR is an 8-bit readable/writable register used to select SCI functions. SCMR is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Bit 3--Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) 405 Bit 2--Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/ bit in SMR. Bit 2 SINV 0 1 Description TDR contents are transmitted without modification Receive data is stored in RDR without modification TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form (Initial value) Bit 1--Reserved: This bit cannot be modified and is always read as 1. Bit 0--Serial Communication Interface Mode Select (SMIF): Reserved bit. 1 should not be written in this bit. Bit 0 SMIF 0 1 Description Normal SCI mode Reserved mode (Initial value) 15.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit Initial value Read/Write 7 6 5 4 3 2 1 0 7 6 5 MSTPCRL 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When bit MSTP7, MSTP6, or MSTP5 is set to 1, SCI0, SCI1, or SCI2 operation, respectively, stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 23.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. 406 Bit 7--Module Stop (MSTP7): Specifies the SCI0 module stop mode. MSTPCRL Bit 7 MSTP7 0 1 Description SCI0 module stop mode is cleared SCI0 module stop mode is set (Initial value) Bit 6--Module Stop (MSTP6): Specifies the SCI1 module stop mode. MSTPCRL Bit 6 MSTP6 0 1 Description SCI1 module stop mode is cleared SCI1 module stop mode is set (Initial value) Bit 5--Module Stop (MSTP5): Specifies the SCI2 module stop mode. MSTPCRL Bit 5 MSTP5 0 1 Description SCI2 module stop mode is cleared SCI2 module stop mode is set (Initial value) 407 15.2.11 Keyboard Comparator Control Register (KBCOMP) Bit Initial value Read/Write 7 IrE 0 R/W 6 IrCKS2 0 R/W 5 IrCKS1 0 R/W 4 IrCKS0 0 R/W 3 KBADE 0 R/W 2 KBCH2 0 R/W 1 KBCH1 0 R/W 0 KBCH0 0 R/W KBCOMP is an 8-bit readable/writable register that selects the functions of SCI2 and the A/D converter. KBCOMP is initialized to H'00 by a reset and in hardware standby mode. Bit 7--IrDA Enable (IrE): Specifies normal SCI operation or IrDA operation for SCI2 input/output. Bit 7 IrE 0 1 Description The TxD2/IrTxD and RxD2/IrRxD pins function as TxD2 and RxD2 The TxD2/IrTxD and RxD2/IrRxD pins function as IrTxD and IrRxD (Initial value) Bits 6 to 4--IrDA Clock Select 2 to 0 (IrCKS2 to IrCKS0): These bits specify the high pulse width in IrTxD output pulse encoding when the IrDA function is enabled. Bit 6 IrCKS2 0 Bit 5 IrCKS1 0 Bit 4 IrCKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description B x 3/16 (3/16 of the bit rate) o/2 o/4 o/8 o/16 o/32 o/64 o/128 (Initial value) Bits 3 to 0--Keyboard Comparator Control: See the description in section 20, A/D converter. 408 15.3 15.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 15.8. The SCI clock is determined by a combination of the C/ bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 15.9. Asynchronous Mode * Data length: Choice of 7 or 8 bits * Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing, parity, and overrun errors, and breaks, during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate generator is not used) Synchronous Mode * Transfer format: Fixed 8-bit data * Detection of overrun errors during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip When external clock is selected: The built-in baud rate generator is not used, and the SCI operates on the input serial clock 409 Table 15.8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 C/ 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 -- -- 1 -- -- 1 -- -- -- 0 1 0 1 -- Synchronous mode 8-bit data No Asynchronous mode (multiprocessor format) 7-bit data 8-bit data Yes No Yes 7-bit data No Mode Asynchronous mode Yes SCI Transfer Format Multiprocessor Bit No Data Length 8-bit data Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Table 15.9 SMR and SCR Settings and SCI Clock Source Selection SMR Bit 7 C/ 0 SCR Setting Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Synchronous mode Internal Mode Asynchronous mode Clock Source Internal SCI Transfer Clock SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Outputs serial clock External Inputs serial clock 410 15.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 1 1 1 Transmit/receive data 7 or 8 bits Parity Stop bit(s) bit 1 bit, or none 1 or 2 bits One unit of transfer data (character or frame) Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 411 Data Transfer Format: Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected by settings in SMR. Table 15.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 -- -- -- -- 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 S S S S S S S S S S S 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP STOP P STOP P STOP STOP STOP STOP STOP P P STOP STOP STOP MPB STOP MPB STOP STOP MPB STOP MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit 412 Clock: Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/ bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 15.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. 413 Figure 15.4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. This is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 15.4 Sample SCI Initialization Flowchart 414 Serial Data Transmission (Asynchronous Mode): Figure 15.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, one frame of 1s is output and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 15.5 Sample Serial Transmission Flowchart 415 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. 416 Figure 15.6 shows an example of the operation for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated request generated TDRE flag cleared to 0 in TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) 417 Serial Data Reception (Asynchronous Mode): Figure 15.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Initialization Start reception [1] [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes handling, ensure that the ORER, PERFERORER= 1? PER, and FER flags are all [3] cleared to 0. Reception cannot No Error handling be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF= 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] No All data received? Yes Clear RE bit in SCR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by an RXI interrupt and the RDR value is read. Figure 15.7 Sample Serial Reception Data Flowchart 418 [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes No Break? Yes Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 15.7 Sample Serial Reception Data Flowchart (cont) 419 In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in RSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. a. Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/ bit in SMR. b. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. c. Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 15.11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. 4. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated. 420 Table 15.11 Receive Errors and Conditions for Occurrence Receive Error Overrun error Abbreviation ORER Occurrence Condition Data Transfer When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 RDR When the stop bit is 0 When the received data differs from the parity (even or odd) set in SMR Receive data is transferred from RSR to RDR Receive data is transferred from RSR to RDR Framing error Parity error FER PER Figure 15.8 shows an example of the operation for reception in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ERI interrupt request generated by framing error 1 frame Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) 421 15.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 15.9 shows an example of inter-processor communication using a multiprocessor format. Data Transfer Format: There are four data transfer formats. When a multiprocessor format is specified, the parity bit specification is invalid. For details, see table 15.10. 422 Clock: See the section on asynchronous mode. Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle: receiving station specification H'AA (MPB = 0) Data transmission cycle: data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 423 Data Transfer Operations Multiprocessor Serial Data Transmission: Figure 15.10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. Initialization Start transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, one frame of 1s is output and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmitdata-empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 15.10 Sample Multiprocessor Serial Transmission Flowchart 424 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Multiprocessor bit One multiprocessor bit (MPBT value) is output. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 425 Figure 15.11 shows an example of SCI operation for transmission using a multiprocessor format. Multiprocessor Stop bit bit D7 0/1 1 1 Start bit 0 D0 D1 Data Start bit 0 D0 D1 Data D7 Multiproces- Stop 1 sor bit bit 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 15.11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) 426 Multiprocessor Serial Data Reception: Figure 15.12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error handling and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Read MPIE bit in SCR Read ORER and FER flags in SSR [2] Yes FERORER = 1? No Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes FERORER = 1? No Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error handling (Continued on next page) Figure 15.12 Sample Multiprocessor Serial Reception Flowchart 427 [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.12 Sample Multiprocessor Serial Reception Flowchart (cont) 428 Figure 15.13 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID1 If not this station's ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station's ID 1 Start bit 0 D0 D1 Data (ID2) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data2) MPB D1 D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt handling routine Data2 MPIE bit set to 1 again (b) Data matches station's ID Figure 15.13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) 429 15.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.14 shows the general format for synchronous serial communication. One unit of transfer data (character or frame) * Serial clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 15.14 Data Format in Synchronous Communication In synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In synchronous serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. 430 Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/ bit in SMR and the CKE1 and CKE0 bits in SCR. For details on SCI clock source selection, see table 15.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive operations in units of one character, select an external clock as the clock source. Data Transfer Operations SCI Initialization (Synchronous Mode): Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the settings of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 15.15 shows a sample SCI initialization flowchart. 431 Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] [3] Write a value corresponding to the bit rate to BRR. This is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Figure 15.15 Sample SCI Initialization Flowchart 432 Serial Data Transmission (Synchronous Mode): Figure 15.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit-data-empty interrupt (TXI) request and data is written to TDR. Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes Clear TE bit in SCR to 0 Figure 15.16 Sample Serial Transmission Flowchart 433 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). 3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. After completion of serial transmission, the SCK pin is held in a constant state. Figure 15.17 shows an example of SCI operation in transmission. Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated TXI interrupt Data written to TDR request generated and TDRE flag cleared to 0 in TXI interrupt handling routine 1 frame TEI interrupt request generated Figure 15.17 Example of SCI Operation in Transmission 434 Serial Data Reception (Synchronous Mode): Figure 15.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. 435 Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER= 1? No [2] [3] Error handling (Continued below) [2] [3] Receive error handling: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by a receive-data-full interrupt (RXI) request and the RDR value is read. Read RDRF flag in SSR [4] No RDRF= 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Error handling Overrun error handling Clear ORER flag in SSR to 0 Figure 15.18 Sample Serial Reception Flowchart 436 In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 15.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. 3. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive-error interrupt (ERI) request is generated. Figure 15.19 shows an example of SCI operation in reception. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 15.19 Example of SCI Operation in Reception Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. 437 Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error handling: Read ORER flag in SSR Yes [3] Error handling ORER = 1? No If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit-data-empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive-datafull interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations 438 15.3.5 IrDA Operation Figure 15.21 shows a block diagram of the IrDA function. When the IrDA function is enabled with bit IrE in KBCOMP, the SCI channel 2 TxD2 and RxD2 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system. In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600 bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in the H8S/2138 Series and H8S/2134 Series does not include a function for varying the transfer rate automatically, the transfer rate setting must be changed by software. IrDA SCI2 TxD2/IrTxD Pulse encoder TxD RxD RxD2/IrRxD Pulse decoder KBCOMP Figure 15.21 Block Diagram of IrDA Function Transmission: In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the IrDA interface (see figure 15.22). When the serial data is 0, a high-level pulses of 3/16 the bit rate (interval equivalent to the width of one bit) is output (initial value). The high-level pulse can be varied according to the setting of bits IrCKS2 to IrCKS0 in KBCOMP. The high-level pulse width is fixed at a minimum of 1.41 s, and a maximum of (3/16 + 2.5%) x bit rate or (3/16 x bit rate) + 1.08 s. When system clock o is 20 MHz, 1.6 s can be set as the minimum high-level pulse width at 1.41 s or above. 439 When the serial data is 1, no pulse is output. UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1 0 Transmission Reception UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1 0 Bit interval Pulse width is 1.6 s to 3/16 bit interval Figure 15.22 IrDA Transmit/Receive Operations Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the SCI. When a high-level pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 s will be identified as a 0 signal. 440 High-Level Pulse Width Selection: Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and H8S/2138 Series and H8S/2134 Series operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 15.12 Bit IrCKS2 to IrCKS0 Settings Operating Frequency o (MHz) 2 2.097152 2.4576 3 3.6864 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 16.9344 17.2032 18 19.6608 20 Bit Rate (bps) (Upper Row) / Bit Interval x 3/16 (s) (Lower Row) 2400 78.13 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 9600 19.53 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 19200 9.77 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 38400 4.88 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 57600 3.26 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 115200 1.63 -- -- -- -- 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 Legend: --: An SCI bit rate setting cannot be mode. 441 15.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.13 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request. Table 15.13 SCI Interrupt Sources Channel 0 Interrupt Source Description ERI RXI TXI TEI 1 ERI RXI TXI TEI 2 ERI RXI TXI TEI Receive error (ORER, FER, or PER) Receive data register full (RDRF) Transmit data register empty (TDRE) Transmit end (TEND) Receive error (ORER, PER, or PER) Receive data register full (RDRF) Transmit data register empty (TDRE) Transmit end (TEND) Receive error (ORER, PER, or PER) Receive data register full (RDRF) Transmit data register empty (TDRE) Transmit end (TEND) DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Low Priority* High Note: * The table shows the initial state immediately after a reset. Relative channel priorities can be changed by the interrupt controller. 442 The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance, and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be accepted in this case. 15.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 15.14. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 15.14 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer RSR to RDR X O O X X O X Receive Errors Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error Notes: O: Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. 443 Break Detection and Processing: When a framing error (FER) is detected, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break: The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This feature can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin should first be set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the base clock. This is illustrated in figure 15.23. 444 16 clocks 8 clocks 0 Internal base clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 15.23 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by equation (1) below. M = 0.5 - 1 D - 0.5 (1 + F) x 100% - (L - 0.5)F - 2N N .......... (1) Where M: N: D: L: F: Receive margin (%) Ratio of bit rate to clock (N = 16) Clock duty (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in equation (1), a receive margin of 46.875% is given by equation (2) below. When D = 0.5 and F = 0, M = 0.5 - 1 x 100% 2 x 16 = 46.875% .......... (2) However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in system design. 445 Restrictions on Use of DTC * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 o clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 clock cycles after TDR is updated. (Figure 15.24) * When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receive-data-full interrupt (RXI). SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4 states. Figure 15.24 Example of Synchronous Transmission by DTC 446 Section 16 I C Bus Interface [H8S/2138 Series Option] A two-channel I C bus interface is available as an option in the H8S/2138 Series. The I C bus interface is not available for the H8S/2134 Series. Observe the following notes when using this option. 1. For mask-ROM versions, a W is added to the part number in products in which this optional function is used. Examples: HD6432137WF 2. The product number is identical for F-ZTAT versions. However, be sure to inform your Hitachi sales representative if you will be using this option. 2 2 2 16.1 Overview 2 2 A two-channel I C bus interface is available for the H8S/2138 Series as an option. The I C bus 2 interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface 2 functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however. Each I C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer data, saving board and connector space. 16.1.1 Features 2 * Selection of addressing format or non-addressing format 2 I C bus format: addressing format with acknowledge bit, for master/slave operation Serial format: non-addressing format without acknowledge bit, for master operation only * Conforms to Philips I2C bus interface (I2C bus format) * Two ways of setting slave address (I2C bus format) * Start and stop conditions generated automatically in master mode (I2C bus format) * Selection of acknowledge output levels when receiving (I2C bus format) * Automatic loading of acknowledge bit when transmitting (I2C bus format) * Wait function in master mode (I2C bus format) A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. 2 * Wait function in slave mode (I C bus format) A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. * Three interrupt sources 447 Data transfer end (including transmission mode transition with I2C bus format and address reception after loss of master arbitration) Address match: when any slave address matches or the general call address is received in 2 slave receive mode (I C bus format) Stop condition detection * Selection of 16 internal clocks (in master mode) * Direct bus drive (with SCL and SDA pins) Two pins--P52/SCL0 and P97/SDA0--(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Two pins--P86/SCL1 and P42/SDA1--(normally CMOS pins) function as NMOS-only outputs when the bus drive function is selected. * Automatic switching from formatless mode to I2C bus format (channel 0 only) Formatless operation (no start/stop conditions, non-addressing mode) in slave mode Operation using a common data pin (SDA) and independent clock pins (VSYNCI, SCL) Automatic switching from formatless mode to I2C bus format on the fall of the SCL pin 448 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the I2C bus interface. Figure 16.2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins and channel 1 I/O pins differ in structure, and have different specifications for permissible applied voltages. For details, see section 24, Electrical Characteristics. Formatless dedicated clock (channel 0 only) o SCL PS ICCR Clock control Noise canceler Bus state decision circuit Arbitration decision circuit ICMR ICSR ICDRT SDA Output data control circuit ICDRS ICDRR Noise canceler Address comparator SAR, SARX Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register SAR: Slave address register SARX: Slave address register X Prescaler PS: 2 Interrupt generator Interrupt request Figure 16.1 Block Diagram of I C Bus Interface Internal data bus 449 Vcc VCC SCL SCL in SCL out SDA SCL SDA SDA in SDA out (Master) SCL SDA SCL in SCL out SCL in SCL out H8S/2138 Series chip SDA in SDA out (Slave 1) 2 SDA in SDA out (Slave 2) Figure 16.2 I C Bus Interface Connections (Example: H8S/2138 Series Chip as Master) 16.1.3 Input/Output Pins 2 Table 16.1 summarizes the input/output pins used by the I C bus interface. Table 16.1 I C Bus Interface Pins Channel 0 Name Serial clock Serial data Formatless serial clock 1 Serial clock Serial data Abbreviation* SCL0 SDA0 VSYNCI SCL1 SDA1 I/O I/O I/O Input I/O I/O Function IIC0 serial clock input/output IIC0 serial data input/output IIC0 formatless serial clock input IIC1 serial clock input/output IIC1 serial data input/output 2 Note: * In the text, the channel subscript is omitted, and only SCL and SDA are used. 450 SCL SDA 16.1.4 Register Configuration Table 16.2 summarizes the registers of the I2C bus interface. Table 16.2 Register Configuration Channel 0 Name I C bus control register I C bus status register I C bus data register I C bus mode register Slave address register Second slave address register 1 I C bus control register I C bus status register I C bus data register I C bus mode register Slave address register Second slave address register Common Serial/timer control register DDC switch register Module stop control register 2 2 2 2 2 2 2 2 Abbreviation ICCR0 ICSR0 ICDR0 ICMR0 SAR0 SARX0 ICCR1 ICSR1 ICDR1 ICMR1 SAR1 SARX1 STCR DDCSWR MSTPCRH MSTPCRL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'01 H'00 -- H'00 H'00 H'01 H'01 H'00 -- H'00 H'00 H'01 H'00 H'0F H'3F H'FF Address*1 H'FFD8 H'FFD9 H'FFDE* H'FFDF* H'FFDF* 2 2 2 H'FFDE* H'FF88 H'FF89 H'FF8E* H'FF8F* H'FF8F* 2 2 2 2 H'FF8E* H'FFC3 H'FEE6 H'FF86 H'FF87 2 Notes: 1. Lower 16 bits of the address. 2 2. The register that can be written or read depends on the ICE bit in the I C bus control 2 register. The slave address register can be accessed when ICE = 0, and the I C bus mode register can be accessed when ICE = 1. 2 The I C bus interface registers are assigned to the same addresses as other registers. Register selection is performed by means of the IICE bit in the serial/timer control register (STCR). 451 16.2 16.2.1 Bit Register Descriptions I C Bus Data Register (ICDR) 7 ICDR7 -- R/W 6 ICDR6 -- R/W 5 ICDR5 -- R/W 4 ICDR4 -- R/W 3 ICDR3 -- R/W 2 ICDR2 -- R/W 1 ICDR1 -- R/W 0 ICDR0 -- R/W 2 Initial value Read/Write * ICDRR Bit Initial value Read/Write 7 -- R 6 -- R 5 -- R 4 -- R 3 -- R 2 -- R 1 -- R 0 -- R ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 * ICDRS Bit Initial value Read/Write 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 -- -- 0 -- -- ICDRS7 ICDRS6 ICDRR5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0 * ICDRT Bit Initial value Read/Write 7 -- W 6 -- W 5 -- W 4 -- W 3 -- W 2 -- W 1 -- W 0 -- W ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 * TDRE, RDRF (internal flags) Bit Initial value Read/Write -- TDRE 0 -- -- RDRF 0 -- 452 ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as TDRE and RDRF. If IIC is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRT to ICDRS. If IIC is in receive mode and no previous data remains in ICDRR (the RDRF flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRS to ICDRR. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. ICDR is assigned to the same address as SARX, and can be written and read only when the ICE bit is set to 1 in ICCR. The value of ICDR is undefined after a reset. The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the TDRE and RDRF flags affects the status of the interrupt flags. 453 TDRE 0 Description The next transmit data is in ICDR (ICDRT), or transmission cannot be started [Clearing conditions] * * * * When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) When a stop condition is detected in the bus line state after a stop condition is 2 issued with the I C bus format or serial format selected 2 When a stop condition is detected with the I C bus format selected In receive mode (TRS = 0) (A 0 write to TRS during transfer is valid after reception of a frame containing an acknowledge bit) (Initial value) 1 The next transmit data can be written in ICDR (ICDRT) [Setting conditions] * In transmit mode (TRS = 1), when a start condition is detected in the bus line 2 state after a start condition is issued in master mode with the I C bus format or serial format selected When using formatless mode in transmit mode (TRS = 1) When data is transferred from ICDRT to ICDRS (Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is empty) When a switch is made from receive mode (TRS = 0) to transmit mode (TRS = 1 ) after detection of a start condition * * * RDRF 0 Description The data in ICDR (ICDRR) is invalid [Clearing condition] When ICDR (ICDRR) receive data is read in receive mode (Initial value) 1 The ICDR (ICDRR) receive data can be read [Setting condition] When data is transferred from ICDRS to ICDRR (Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and RDRF = 0) 454 16.2.2 Bit Slave Address Register (SAR) 7 SVA6 0 R/W 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W Initial value Read/Write SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SAR is assigned to the same address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SAR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 1--Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0, 2 differing from the addresses of other slave devices connected to the I C bus. Bit 0--Format Select (FS): Used together with the FSX bit in SARX and the SW bit in DDCSWR to select the communication format. * I2C bus format: addressing format with acknowledge bit * Synchronous serial format: non-addressing format without acknowledge bit, for master mode only * Formatless mode (channel 0 only): non-addressing format with or without acknowledge bit, slave mode only, start/stop conditions not detected 455 The FS bit also specifies whether or not SAR slave address recognition is performed in slave mode. DDCSWR Bit 6 SW 0 SAR Bit 0 FS 0 SARX Bit 0 FSX 0 1 Operating Mode I C bus format * 2 2 SAR and SARX slave addresses recognized (Initial value) SAR slave address recognized SARX slave address ignored SAR slave address ignored SARX slave address recognized SAR and SARX slave addresses ignored Acknowledge bit used I C bus format * * 1 0 I C bus format * * 2 1 1 0 0 1 1 0 1 0 1 Synchronous serial format * * Formatless mode (start/stop conditions not detected) Formatless mode* (start/stop conditions not detected) * No acknowledge bit 2 Note: * Do not set this mode when automatic switching to the I C bus format is performed by means of the DDCSWR setting. 456 16.2.3 Bit Second Slave Address Register (SARX) 7 SVAX6 0 R/W 6 SVAX5 0 R/W 5 SVAX4 0 R/W 4 SVAX3 0 R/W 3 SVAX2 0 R/W 2 SVAX1 0 R/W 1 SVAX0 0 R/W 0 FSX 1 R/W Initial value Read/Write SARX is an 8-bit readable/writable register that stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SARX is assigned to the same address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SARX is initialized to H'01 by a reset and in hardware standby mode. Bits 7 to 1--Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 2 to SVAX0, differing from the addresses of other slave devices connected to the I C bus. Bit 0--Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in DDCSWR to select the communication format. * I2C bus format: addressing format with acknowledge bit * Synchronous serial format: non-addressing format without acknowledge bit, for master mode only * Formatless mode: non-addressing format with or without acknowledge bit, slave mode only, start/stop conditions not detected The FSX bit also specifies whether or not SARX slave address recognition is performed in slave mode. For details, see the description of the FS bit in SAR. 457 16.2.4 Bit I C Bus Mode Register (ICMR) 7 MLS 0 R/W 6 WAIT 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W 2 Initial value Read/Write ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR. ICMR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or LSB-first. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. Do not set this bit to 1 when the I C bus format is used. Bit 7 MLS 0 1 Description MSB-first LSB-first (Initial value) 2 458 Bit 6--Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data 2 and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the WAIT setting. The setting of this bit is invalid in slave mode. Bit 6 WAIT 0 1 Description Data and acknowledge bits transferred consecutively Wait inserted between data and acknowledge bits (Initial value) 459 Bits 5 to 3--Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel 1) or IICX0 (channel 0) bit in the STCR register, select the serial clock frequency in master mode. They should be set according to the required transfer rate. STCR Bit 5 or 6 Bit 5 Bit 4 Bit 3 IICX 0 CKS2 CKS1 CKS0 Clock 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 2 Transfer Rate o= 5 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz o= 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz o= 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz o= 16 MHz 571 kHz* 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz o= 20 MHz 714 kHz* 500 kHz* 417 kHz* 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz o/28 o/40 o/48 o/64 o/80 o/100 o/112 o/128 o/56 o/80 o/96 o/128 o/160 o/200 o/224 o/256 0 1 Note: * Outside the I C bus interface specification range (normal mode: max. 100 kHz; high-speed mode: max. 400 kHz). 460 Bits 2 to 0--Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be 2 transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 by a reset and when a start condition is detected. The value returns to 000 at the end of a data transfer, including the acknowledge bit. Bit 2 BC2 0 Bit 1 BC1 0 Bit 0 BC0 0 1 1 0 1 1 0 0 1 1 0 1 Bits/Frame Synchronous Serial Format 8 1 2 3 4 5 6 7 I2C Bus Format 9 2 3 4 5 6 7 8 (Initial value) 461 16.2.5 Bit I C Bus Control Register (ICCR) 7 ICE 0 R/W 6 IEIC 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 3 ACKE 0 R/W 2 BBSY 0 R/W 1 IRIC 0 R/(W)* 0 SCP 1 W 2 Initial value Read/Write Note: * Only 0 can be written, to clear the flag. ICCR is an 8-bit readable/writable register that enables or disables the I C bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or 2 disables acknowledgement, confirms the I C bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. ICCR is initialized to H'01 by a reset and in hardware standby mode. Bit 7--I C Bus Interface Enable (ICE): Selects whether or not the I C bus interface is to be used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer 2 operations are enabled. When ICE is cleared to 0, the I C bus interface module is disabled. The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can be accessed when ICE is 1. Bit 7 ICE 0 Description I C bus interface module disabled, with SCL and SDA signal pins set to port function SAR and SARX can be accessed 1 I C bus interface module enabled for transfer operations (pins SCL and SCA are driving the bus) ICMR and ICDR can be accessed 2 2 2 2 2 2 2 (Initial value) Bit 6--I C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I C bus interface to the CPU. Bit 6 IEIC 0 1 Description Interrupts disabled Interrupts enabled (Initial value) 462 Bit 5--Master/Slave Select (MST) Bit 4--Transmit/Receive Select (TRS) MST selects whether the I C bus interface operates in master mode or slave mode. TRS selects whether the I C bus interface operates in transmit mode or receive mode. In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. In slave receive mode with the addressing format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to the R/W bit in the first frame after a start condition. Modification of the TRS bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. MST and TRS select the operating mode as follows. Bit 5 MST 0 Bit 4 TRS 0 1 1 0 1 Bit 5 MST 0 Description Slave mode [Clearing conditions] 1. When 0 is written by software 2 2. When bus arbitration is lost after transmission is started in I C bus format master mode 1 Master mode [Setting conditions] 1. When 1 is written by software (in cases other than clearing condition 2) 2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2) (Initial value) Operating Mode Slave receive mode Slave transmit mode Master receive mode Master transmit mode (Initial value) 2 2 2 463 Bit 4 TRS 0 Description Receive mode [Clearing conditions] 1. When 0 is written by software (in cases other than setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (in case of clearing condition 3) 2 3. When bus arbitration is lost after transmission is started in I C bus format master mode 4. When the SW bit in DDCSWR changes from 1 to 0 1 Transmit mode [Setting conditions] 1. When 1 is written by software (in cases other than clearing conditions 3 and 4) 2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3 and 4) 2 3. When a 1 is received as the R/W bit of the first frame in I C bus format slave mode (Initial value) Bit 3--Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the 2 acknowledge bit returned from the receiving device when using the I C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. In the H8S/2138 Series, the DTC can be used to perform continuous transfer. The DTC is activated when the IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the other being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1. When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified number of data transfers have been executed. Consequently, interrupts are not generated during continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the ACKE bit is set to 1, the DTC is not activated and an interrupt is generated, if enabled. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. 464 Bit 3 ACKE 0 1 Description The value of the acknowledge bit is ignored, and continuous transfer is performed If the acknowledge bit is 1, continuous transfer is interrupted 2 (Initial value) Bit 2--Bus Busy (BBSY): The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition, clearing BBSY to 0. To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, use a MOV instruction to 2 write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode; the I C bus interface must be set to master transmit mode before issuing a start condition. MST and TRS should both be set to 1 before writing 1 in BBSY and 0 in SCP. Bit 2 BBSY 0 Description Bus is free [Clearing condition] When a stop condition is detected 1 Bus is busy [Setting condition] When a start condition is detected 2 2 (Initial value) Bit 1--I C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR. See section 16.3.6, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC. When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. 465 Bit 1 IRIC 0 Description Waiting for transfer, or transfer in progress (Initial value) [Clearing conditions] 1. When 0 is written in IRIC after reading IRIC = 1 2. When ICDR is written or read by the DTC (When the TDRE or RDRF flag is cleared to 0) (This is not always a clearing condition; see the description of DTC operation for details) Interrupt requested [Setting conditions] 2 * I C bus format master mode 1. When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) 2. When a wait is inserted between the data and acknowledge bit when WAIT = 1 3. At the end of data transfer (at the rise of the 9th transmit/receive clock pulse, and, when a wait is inserted, at the fall of the 8th transmit/receive clock pulse) 4. When a slave address is received after bus arbitration is lost (when the AL flag is set to 1) 5. When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) 2 * I C bus format slave mode 1. When the slave address (SVA, SVAX) matches (when the AAS and AASX flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) 2. When the general call address is detected (when FS = 0 and the ADZ flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) 3. When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) 4. When a stop condition is detected (when the STOP or ESTP flag is set to 1) * Synchronous serial format, and formatless mode 1. At the end of data transfer (when the TDRE or RDRF flag is set to 1) 2. When a start condition is detected with serial format selected 3. When the SW bit is set to 1 in DDCSWR 1 466 When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (SVA) or general call 2 address match in I C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Table 16.3 shows the relationship between the flags and the transfer states. 467 Table 16.3 Flags and Transfer States MST TRS BBSY ESTP STOP IRTR AASX AL 1/0 1 1 1 1 1/0 1 1 1/0 1/0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 AAS ADZ 0 0 0 0 0 0 0 0 0 0 ACKB State 0 0 0 0/1 0/1 Idle state (flag clearing required) Start condition issuance Start condition established Master mode wait Master mode transmit/receive end Arbitration lost SAR match by first frame in slave mode General call address match SARX match Slave mode transmit/receive end (except after SARX match) Slave mode transmit/receive end (after SARX match) Stop condition detected 0 0 0 0 1 1 0 0 0 0 0 0 1/0 0 1 0 1/0 1 1/0 0 0 0 0 0 0 0 0 1/0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0/1 0 0 0 1/0 1 1/0 1 1 0 0 0 1/0 0 0 1/0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0/1 Bit 0--Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. Bit 0 SCP 0 1 Description Writing 0 issues a start or stop condition, in combination with the BBSY flag Reading always returns a value of 1 Writing is ignored (Initial value) 468 16.2.6 Bit I C Bus Status Register (ICSR) 7 ESTP 0 R/(W)* 6 STOP 0 R/(W)* 5 IRTR 0 R/(W)* 4 AASX 0 R/(W)* 3 AL 0 R/(W)* 2 AAS 0 R/(W)* 1 ADZ 0 R/(W)* 0 ACKB 0 R/W 2 Initial value Read/Write Note: * Only 0 can be written, to clear the flags. ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. ICSR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been 2 detected during frame transfer in I C bus format slave mode. Bit 7 ESTP 0 Description No error stop condition [Clearing conditions] 1. When 0 is written in ESTP after reading ESTP = 1 2. When the IRIC flag is cleared to 0 1 * In I C bus format slave mode Error stop condition detected [Setting condition] When a stop condition is detected during frame transfer * In other modes No meaning 2 (Initial value) 469 Bit 6--Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has 2 been detected after completion of frame transfer in I C bus format slave mode. Bit 6 STOP 0 Description No normal stop condition [Clearing conditions] 1. When 0 is written in STOP after reading STOP = 1 2. When the IRIC flag is cleared to 0 1 * In I C bus format slave mode Normal stop condition detected [Setting condition] When a stop condition is detected after completion of frame transfer * In other modes No meaning 2 (Initial value) Bit 5--I C Bus Interface Continuous Transmission/Reception Interrupt Request Flag 2 (IRTR): Indicates that the I C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically when the IRIC flag is cleared to 0. Bit 5 IRTR 0 Description Waiting for transfer, or transfer in progress [Clearing conditions] 1. When 0 is written in IRTR after reading IRTR = 1 2. When the IRIC flag is cleared to 0 1 Continuous transfer state [Setting condition] * * In I C bus interface slave mode When the TDRE or RDRF flag is set to 1 when AASX = 1 In other modes When the TDRE or RDRF flag is set to 1 2 2 (Initial value) 470 Bit 4--Second Slave Address Recognition Flag (AASX): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is also cleared automatically when a start condition is detected. Bit 4 AASX 0 Description Second slave address not recognized [Clearing conditions] 1. When 0 is written in AASX after reading AASX = 1 2. When a start condition is detected 3. In master mode 1 Second slave address recognized [Setting condition] When the second slave address is detected in slave receive mode while FSX = 0 (Initial value) Bit 3--Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The 2 I C bus interface monitors the bus. When two or more master devices attempt to seize the bus at 2 nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 3 AL 0 Description Bus arbitration won [Clearing conditions] 1. When ICDR data is written (transmit mode) or read (receive mode) 2. When 0 is written in AL after reading AL = 1 1 Arbitration lost [Setting conditions] 1. If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode 2. If the internal SCL line is high at the fall of SCL in master transmit mode (Initial value) 471 Bit 2--Slave Address Recognition Flag (AAS): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 2 AAS 0 Description Slave address or general call address not recognized [Clearing conditions] 1. When ICDR data is written (transmit mode) or read (receive mode) 2. When 0 is written in AAS after reading AAS = 1 3. In master mode 1 Slave address or general call address recognized [Setting condition] When the slave address or general call address is detected in slave receive mode while FS = 0 (Initial value) 472 Bit 1--General Call Address Recognition Flag (ADZ): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 1 ADZ 0 Description General call address not recognized [Clearing conditions] 1. When ICDR data is written (transmit mode) or read (receive mode) 2. When 0 is written in ADZ after reading ADZ = 1 3. In master mode 1 General call address recognized [Setting condition] When the general call address is detected in slave receive mode while FSX = 0 or FS = 0 (Initial value) Bit 0--Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line (returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal software is read. Bit 0 ACKB 0 Description Receive mode: 0 is output at acknowledge output timing (Initial value) Transmit mode: Indicates that the receiving device has acknowledged the data (signal is 0) 1 Receive mode: 1 is output at acknowledge output timing Transmit mode: Indicates that the receiving device has not acknowledged the data (signal is 1) 473 16.2.7 Bit Serial/Timer Control Register (STCR) 7 -- 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W 3 FLSHE 0 R/W 2 -- 0 R/W 2 1 ICKS1 0 R/W 0 ICKS0 0 R/W Initial value Read/Write STCR is an 8-bit readable/writable register that controls register access, the I C interface operating mode (when the on-chip IIC option is included), and on-chip flash memory (F-ZTAT 2 versions), and selects the TCNT input clock source. For details of functions not related to the I C bus interface, see section 3.2.4, Serial/Timer Control Register (STCR), and the descriptions of the relevant modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--Reserved: Do not write 1 to this bit. Bit 6--I C Transfer Select 1 (IICX1): This bit, together with bits CKS2 to CKS0 in ICMR of 2 IIC1, selects the transfer rate in master mode. For details, see section 16.2.4, I C Bus Mode Register (ICMR). Bit 5--I C Transfer Select 0 (IICX0): This bit, together with bits CKS2 to CKS0 in ICMR of 2 IIC0, selects the transfer rate in master mode. For details, see section 16.2.4, I C Bus Mode Register (ICMR). Bit 4--I C Master Enable (IICE): Controls CPU access to the I C bus interface data and control registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR). Bit 4 IICE 0 1 Description CPU access to I C bus interface data and control registers is disabled CPU access to I C bus interface data and control registers is enabled 2 2 2 2 2 2 (Initial value) Bit 3--Flash Memory Control Register Enable (FLSHE): Controls the operation of the flash memory in F-ZTAT versions. For details, see section 22, ROM. Bit 2--Reserved: Do not write 1 to this bit. Bits 1 and 0--Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits, together with bits CKS2 to CKS0 in TCR, select the clock input to the timer counters (TCNT). For details, see section 12.2.4, Timer Control Register (TCR). 474 16.2.8 Bit DDC Switch Register (DDCSWR) 7 SWE 0 R/W 6 SW 0 R/W 5 IE 0 R/W 4 IF 0 R/(W)*1 3 CLR3 1 W*2 2 CLR2 1 W*2 1 CLR1 1 W*2 0 CLR0 1 W*2 Initial value Read/Write Notes: 1. Only 0 can be written, to clear the flag. 2. Always read as 1. DDCSWR is an 8-bit readable/writable register that controls the IIC channel 0 automatic format switching function. DDCSWR is initialized to H'0F by a reset and in hardware standby mode. Bit 7--DDC Mode Switch Enable (SWE): Selects the function for automatically switching IIC 2 channel 0 from formatless mode to the I C bus format. Bit 7 SWE 0 1 Description Automatic switching of IIC channel 0 from formatless mode to I C bus format is disabled Automatic switching of IIC channel 0 from formatless mode to I C bus format is enabled 2 2 2 (Initial value) Bit 6--DDC Mode Switch (SW): Selects either formatless mode or the I C bus format for IIC channel 0. Bit 6 SW 0 Description IIC channel 0 is used with the I C bus format [Clearing conditions] 1. When 0 is written by software 2. When a falling edge is detected on the SCL pin when SWE = 1 1 IIC channel 0 is used in formatless mode [Setting condition] When 1 is written in SW after reading SW = 0 2 (Initial value) 475 Bit 5--DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to the CPU when automatic format switching is executed for IIC channel 0. Bit 5 IE 0 1 Description Interrupt when automatic format switching is executed is disabled Interrupt when automatic format switching is executed is enabled (Initial value) Bit 4--DDC Mode Switch Interrupt Flag (IF): Flag that indicates an interrupt request to the CPU when automatic format switching is executed for IIC channel 0. Bit 4 IF 0 Description No interrupt is requested when automatic format switching is executed (Initial value) [Clearing condition] When 0 is written in IF after reading IF = 1 1 An interrupt is requested when automatic format switching is executed [Setting condition] When a falling edge is detected on the SCL pin when SWE = 1 476 Bits 3 to 0--IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal state of IIC0 and IIC1. These bits can only be written to; if read they will always return a value of 1. When a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized. The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. When clearing is required again, all the bits must be written to in accordance with the setting. Bit 3 CLR3 0 Bit 2 CLR2 0 1 Bit 1 CLR1 -- 0 Bit 0 CLR0 -- 0 1 1 0 1 1 -- -- -- Description Setting prohibited Setting prohibited IIC0 internal latch cleared IIC1 internal latch cleared IIC0 and IIC1 internal latches cleared Invalid setting 477 16.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 Bit Initial value Read/Write 7 6 5 4 3 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. When the MSTP4 or MSTP3 bit is set to 1, operation of the corresponding IIC channel is halted at the end of the bus cycle, and a transition is made to module stop mode. For details, see section 23.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRL Bit 4--Module Stop (MSTP4): Specifies IIC channel 0 module stop mode. MSTPCRL Bit 4 MSTP4 0 1 Description IIC channel 0 module stop mode is cleared IIC channel 0 module stop mode is set (Initial value) MSTPCRL Bit 3--Module Stop (MSTP3): Specifies IIC channel 1 module stop mode. MSTPCRL Bit 3 MSTP3 0 1 Description IIC channel 1 module stop mode is cleared IIC channel 1 module stop mode is set (Initial value) 478 16.3 16.3.1 Operation I C Bus Data Format 2 The I2C bus interface has serial and I2C bus formats. The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures 16.3 (a) and (b). The first frame following a start condition always consists of 8 bits. IIC channel 0 only is capable of formatless operation, as shown in figure 16.3 (c). The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 16.4. Figure 16.5 shows the I C bus timing. The symbols used in figures 16.3 to 16.5 are explained in table 16.4. (a) I2C bus format (FS = 0 or FSX = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) 2 2 (b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) (c) Formatless (IIC0 only, FS = 0 or FSX = 0) DATA 8 1 A 1 DATA n A 1 m A/A 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) 2 Figure 16.3 I C Bus Data Formats (I C Bus Formats) 2 479 FS = 1 and FSX = 1 S 1 DATA 8 1 DATA n m P 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) Figure 16.4 I C Bus Data Format (Serial Format) 2 SDA SCL S 1-7 SLA 8 R/W 9 A 1-7 DATA 2 8 9 A 1-7 DATA 8 9 A/A P Figure 16.5 I C Bus Timing Table 16.4 I C Bus Data Format Symbols Legend S SLA R/: A DATA P Start condition. The master device drives SDA from high to low while SCL is high Slave address, by which the master device selects a slave device Indicates the direction of data transfer: from the slave device to the master device when R/: is 1, or from the master device to the slave device when R/: is 0 Acknowledge. The receiving device (the slave in master transmit mode, or the master in master receive mode) drives SDA low to acknowledge a transfer Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or LSB-first format is selected by bit MLS in ICMR Stop condition. The master device drives SDA from low to high while SCL is high 2 480 16.3.2 Master Transmit Operation In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The transmission procedure and operations are described below. [1] Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX in STCR, according to the operating mode. [2] Read the BBSY flag in ICCR to confirm that the bus is free, then set bits MST and TRS to 1 in ICCR to select master transmit mode. Next, write 1 to BBSY and 0 to SCP. This changes SDA from high to low when SCL is high, and generates the start condition. The TDRE internal flag is then set to 1, and the IRIC and IRTR flags are also set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 2 [3] With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction. Write the data (slave address + R/W) to ICDR. The TDRE internal flag is then cleared to 0. The written address data is transferred to ICDRS, and the TDRE internal flag is set to 1 again. This is identified as indicating the end of the transfer, and so the IRIC flag is cleared to 0. The master device sequentially sends the transmit clock and the data written to ICDR using the timing shown in figure 16.6. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. [4] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, after one frame has been transmitted SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [5] To continue transfer, write the next data to be transmitted into ICDR. After the data has been transferred to ICDRS and the TDRE internal flag has been set to 1, clear the IRIC flag to 0. Transmission of the next frame is performed in synchronization with the internal clock. Data can be transmitted sequentially by repeating steps [4] and [5]. To end transmission, clear the IRIC flag, write H'FF dummy data to ICDR after the last data has been transmitted (when ICDRT does not contain the next transmit data), and then write 0 to BBSY and SCP in ICCR when the IRIC flag is set again. This changes SDA from low to high when SCL is high, and generates the stop condition. 481 Start condition issuance SCL (master output) 1 2 3 4 5 6 7 8 9 1 2 Slave address SDA (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [4] Slave address SDA (slave output) TDRE R/W A Data 1 Bit 7 Bit 6 IRIC Interrupt request generation Address + R/W Interrupt request generation ICDRT Data 1 ICDRS Address + R/W Data 1 User processing [2] Write BBSY = 1 and SCP = 0 (start condition issuance) [3] ICDR write [3] IRIC clearance [5] ICDR write [5] IRIC clearance Figure 16.6 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0) To transmit data continuously: [6] Before the rise of the 9th transmit clock pulse for the data being transmitted, clear the IRIC flag to 0 and then write the next transmit data to ICDR. [7] When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. At the same time, the next transmit data written into ICDR (ICDRT) is transferred to ICDRS, the TDRE internal flag is set to 1, and then the next frame is transmitted in synchronization with the internal clock. Data can be transmitted continuously by repeating steps [6] and [7]. 482 SCL (master output) 1 2 3 4 5 6 7 8 9 1 2 3 SDA (master output) SDA (slave output) TDRE Bit 7 Bit 6 Bit 5 Bit 4 Data 1 Bit 3 Bit 2 Bit 1 Bit 0 [7] A Bit 7 Bit 6 Bit 5 Data 2 IRIC Interrupt request generation Data 1 Data 2 [7] Data 3 ICDRT ICDRS Data 1 Data 2 User processing ICDR write [6] IRIC clearance [6] ICDR write [6] IRIC clearance [6] ICDR write Figure 16.7 Example of Master Transmit Mode Continuous Transmit Operation Timing (MLS = WAIT = 0) 16.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The reception procedure and operations in master receive mode are described below. [1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Also clear the ACKB bit in ICSR to 0 (acknowledge data setting). [2] When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. In order to determine the end of reception, the IRIC flag in ICCR must be cleared beforehand. [3] The master device drives SDA at the 9th receive clock pulse to return an acknowledge signal. When one frame of data has been received, the IRIC flag in ICCR is set to 1 at the rise of the 9th receive clock pulse. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and the receive operation continues. If reception of the next frame ends before the ICDR read/IRIC flag clearing in [4] is performed, SCL is automatically fixed low in synchronization with the internal clock. [4] Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. 483 Data can be received continuously by repeating steps [3] and [4]. As the RDRF internal flag is cleared to 0 when reception is started after initially switching from master transmit mode to master receive mode, reception of the next frame of data is started automatically. To halt reception, the TRS bit must be set to 1 before the rise of the receive clock for the next frame. To halt reception, set the TSR bit to 1, read ICDR, then write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Master transmit mode SCL (master output) Master receive mode 9 1 2 3 4 5 6 7 8 9 1 2 SDA (slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Data 1 Bit 3 Bit 2 Bit 1 Bit 0 [3] A Bit 7 Bit 6 Data 2 SDA (master output) RDRF IRIC Interrupt request generation Interrupt request generation ICDRS Data 1 ICDRR Data 1 User processing [1] TRS cleared to 0 [2] ICDR read [2] IRIC clearance (dummy read) [4] ICDR read [4] IRIC clearance Figure 16.8 Example of Master Receive Mode Operation Timing (MLS = WAIT = ACKB = 0) 484 16.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. [1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. [2] When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. [3] When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit in ICCR remains cleared to 0, and slave receive operation is performed. [4] At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag has been set to 1, the slave device drives SCL low from the fall of the receive clock until data is read into ICDR. [5] Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. 485 Start condition issuance SCL (master output) SCL (slave output) SDA (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W [4] A Bit 7 Bit 6 Data 1 1 2 3 4 5 6 7 8 9 1 2 Slave address SDA (slave output) RDRF IRIC Interrupt request generation ICDRS Address + R/W ICDRR Address + R/W User processing [5] ICDR read [5] IRIC clearance Figure 16.9 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) SCL (master output) SCL (slave output) SDA (master output) 7 8 9 1 2 3 4 5 6 7 8 9 Bit 1 Data 1 Bit 0 [4] Bit 7 Bit 6 Bit 5 Bit 4 Data 2 Bit 3 Bit 2 Bit 1 Bit 0 [4] SDA (slave output) A A RDRF IRIC Interrupt request generation Data 1 Interrupt request generation Data 2 ICDRS ICDRR Data 1 Data 2 User processing [5] ICDR read [5] IRIC clearance Figure 16.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) 486 16.3.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. [1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. [2] When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. .If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The TDRF flag is set to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is written. [3] After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0. The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at the timing shown in figure 16.11. [4] When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is written to ICDR. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed normally. When the TDRE internal flag is 0, the data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. [5] To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted into ICDR. The TDRE flag is cleared to 0. Transmit operations can be performed continuously by repeating steps [4] and [5]. To end transmission, write H'FF to ICDR to release SDA on the slave side. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. 487 Slave receive mode SCL (master output) SDA (slave output) SDA (slave output) SDA (slave output) Slave transmit mode 8 9 1 2 3 4 5 6 7 8 9 1 2 A [2] R/W Bit 7 Bit 6 Bit 5 Bit 4 Data 1 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Data 2 A TDRE [3] Interrupt request generation Data 2 IRIC Interrupt request generation Interrupt request generation Data 1 ICDRT ICDRS Data 1 Data 2 User processing [3] IRIC [3] ICDR write clearance [3] ICDR write [5] IRIC [5] ICDR write clearance Figure 16.11 Example of Slave Transmit Mode Operation Timing (MLS = 0) 488 16.3.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 16.12 shows the IRIC set timing and SCL control. (a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 SDA IRIC 7 8 A 1 User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 SDA IRIC 8 A 1 User processing Clear IRIC Clear Write to ICDR (transmit) IRIC or read ICDR (receive) (c) When FS = 1 and FSX = 1 (synchronous serial format) SCL 7 8 1 SDA IRIC 7 8 1 User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) Figure 16.12 IRIC Setting Timing and SCL Control 489 16.3.7 Automatic Switching from Formatless Mode to I C Bus Format 2 Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC0 2 operating mode. Switching from formatless mode to the I C bus format (slave mode) is performed automatically when a falling edge is detected on the SCL pin. The following four preconditions are necessary for this operation: * * * * A common data pin (SDA) for formatless and I2C bus format operation Separate clock pins for formatless operation (VSYNCI) and I2C bus format operation (SCL) A fixed 1 level for the SCL pin during format operation Settings of bits other than TRS in ICCR that allow I2C bus format operation 2 Automatic switching is performed from formatless mode to the I C bus format when the SW bit in DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. 2 Switching from the I C bus format to formatless mode is achieved by having software set the SW bit in DDCSWR to 1. In formatless mode, bits (such as MSL and TRS) that control the I C bus interface operating 2 mode must not be modified. When switching from the I C bus format to formatless mode, set the TRS bit to 1 or clear it to 0 according to the transmit data (transmission or reception) in formatless mode, then set the SW bit to 1. After automatic switching from formatless mode to 2 the I C bus format (slave mode), in order to wait for slave address reception, the TRS bit is automatically cleared to 0. If a falling edge is detected on the SCL pin during formatless operation, I C bus interface operation is deferred until a stop condition is detected. 2 2 490 16.3.8 Operation Using the DTC The I2C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 16.5 shows some examples of processing using the DTC. These examples assume that the number of transfer data bytes is known in slave mode. Table 16.5 Examples of Operation Using the DTC Item Master Transmit Mode Master Receive Mode Slave Transmit Mode Slave Receive Mode Reception by CPU (ICDR read) Slave address + Transmission by R/W bit DTC (ICDR write) transmission/ reception Dummy data read Actual data transmission/ reception Dummy data (H'FF) write Last frame processing Transfer request processing after last frame processing Setting of number of DTC transfer data frames -- Transmission by DTC (ICDR write) -- Not necessary 1st time: Clearing by CPU 2nd time: End condition issuance by CPU Transmission by Reception by CPU (ICDR write) CPU (ICDR read) Processing by CPU (ICDR read) Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Not necessary -- Transmission by DTC (ICDR write) Processing by DTC (ICDR write) Not necessary -- Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Automatic clearing Not necessary on detection of end condition during transmission of dummy data (H'FF) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to dummy data (H'FF)) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to slave address + R/W bits) 491 16.3.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock period Sampling clock Figure 16.13 Block Diagram of Noise Canceler 492 16.3.10 Sample Flowcharts Figures 16.14 to 16.17 show sample flowcharts for using the I2C bus interface in each mode. Start Initialize [1] Test the status of the SCL and SDA lines. Read BBSY in ICCR No BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Write BBSY = 1 and SCP = 0 in ICCR Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Read ACKB in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Read ACKB in ICSR [9] No End of transmission (ACKB = 1)? Yes Write BBSY = 0 and SCP = 0 in ICCR End [10] [7] No Master receive mode No [6] [2] [1] [2] Select master transmit mode. [3] Generate a start condition. [4] Set transmit data for the first byte (slave address + R/W). [5] Wait for 1 byte to be transmitted. [6] Test for acknowledgement by the designated slave device. [7] Set transmit data for the second and subsequent bytes. [8] Wait for 1 byte to be transmitted. [4] [9] Test for end of transfer. [10] Generate a stop condition. [3] [5] [8] Figure 16.14 Flowchart for Master Transmit Mode (Example) 493 Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR [1] [2] [1] Select receive mode. [2] Set acknowledge data. [3] Start receiving. The first read is a dummy read. [4] Wait for 1 byte to be received. Last receive? No Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No [3] Yes [5] Set acknowledge data for the last receive. [6] Start the last receive. [7] Wait for 1 byte to be received. [8] Select transmit mode. [9] Read the last receive data (if ICDR is read without selecting transmit mode, receive operations will resume). [10] Generate a stop condition. IRIC = 1? Yes [4] Set ACKB = 1 in ICSR Read ICDR Clear IRIC in ICCR [5] [6] Read IRIC in ICCR No IRIC = 1? Yes Set TRS = 1 in ICCR Read ICDR Clear IRIC in ICCR Write BBSY = 0 and SCP = 0 in ICCR End [7] [8] [9] [10] Figure 16.15 Flowchart for Master Receive Mode (Example) 494 Start Initialize Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Read IRIC in ICCR [2] No IRIC = 1? Yes Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? Yes Read TRS in ICCR TRS = 0? Yes Last receive? No Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No [4] IRIC = 1? Yes Set ACKB = 1 in ICSR Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Read ICDR Clear IRIC in ICCR End [8] [5] [6] Yes [1] Select slave receive mode. [2] Wait for the first byte to be received (slave address). [3] Start receiving. The first read is a dummy read. [4] Wait for the transfer to end. [5] Set acknowledge data for the last receive. [6] Start the last receive. [7] Wait for the transfer to end. [8] Read the last receive data. No Slave transmit mode No General call address processing * Description omitted [1] [3] [7] Figure 16.16 Flowchart for Slave Receive Mode (Example) 495 Slave transmit mode Clear IRIC in ICCR [1] Set transmit data for the second and subsequent bytes. [2] Wait for 1 byte to be transmitted. [3] Test for end of transfer. Read IRIC in ICCR No [2] IRIC = 1? Yes Read ACKB in ICSR End of transmission (ACKB = 1)? Yes Set TRS = 0 in ICCR Read ICDR Clear IRIC in ICCR End [4] [3] [4] Select slave receive mode. [5] Dummy read (to release the SCL line). Write transmit data in ICDR Clear IRIC in ICCR [1] No [5] Figure 16.17 Flowchart for Slave Transmit Mode (Example) 496 16.3.11 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in the DDCSWR register. For details see section 16.2.8, DDC Switch Register (DDCSWR). Scope of Initialization: The initialization executed by this function covers the following items: * TDRE and RDRF internal flags * Transmit/receive sequencer and internal operating clock counter * Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) The following items are not initialized: * Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR) * Internal latches used to retain register read information for setting/clearing flags in the ICMR, ICCR, ICSR, and DDCSWR registers * The value of the ICMR register bit counter (BC2 to BC0) * Generated interrupt sources (interrupt sources transferred to the interrupt controller) Notes on Initialization: * Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. * Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. * The write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. * If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. 497 The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBST bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0. 4. Initialize (re-set) the IIC registers. 16.4 Usage Notes * In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. * Either of the following two conditions will start the next transfer. Pay attention to these conditions when reading or writing to ICDR. Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) * Table 16.6 shows the timing of SCL and SDA output in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. 498 Table 16.6 I C Bus Timing (SCL and SDA Output) Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time tSDAHO Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28tcyc to 256tcyc 0.5tSCLO 0.5tSCLO 0.5tSCLO - 1tcyc 0.5tSCLO - 1tcyc 1tSCLO 0.5tSCLO + 2tcyc 1tSCLLO - 3tcyc 1tSCLL - (6tcyc or 12tcyc*) 3tcyc ns Unit ns ns ns ns ns ns ns ns Notes Figure 24.25 (reference) 2 Note: * 6tcyc when IICX is 0, 12tcyc when 1. * SCL and SDA input is sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in table 24.10 in section 24, 2 Electrical Characteristics. Note that the I C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. * The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high2 speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) 2 exceeds the time determined by the input clock of the I C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in the table below. 499 Table 16.7 Permissible SCL Rise Time (tSR) Values Time Indication tcyc Indication 7.5tcyc Normal mode I C Bus Specification (Max.) 1000 ns 2 IICX 0 o= 5 MHz 1000 ns 300 ns 1000 ns 300 ns o= 8 MHz 937 ns 300 ns 1000 ns 300 ns o= 10 MHz 750 ns 300 ns 1000 ns 300 ns o= 16 MHz 468 ns 300 ns 1000 ns 300 ns o= 20 MHz 375 ns 300 ns 875 ns 300 ns High-speed mode 300 ns 1 17.5tcyc Normal mode 1000 ns High-speed mode 300 ns * The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 2 ns and 300 ns. The I C bus interface SCL and SDA output timing is prescribed by tScyc and tcyc, 2 as shown in table 16.6. However, because of the rise and fall times, the I C bus interface specifications may not be satisfied at the maximum transfer rate. Table 16.8 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. 2 tBUFO fails to meet the I C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input 2 timing permits this output timing for use as slave devices connected to the I C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to 2 the I C bus. 500 Table 16.8 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] tSr/tSf Influence (Max.) Standard mode High-speed mode tSCLLO 0.5tSCLO (-tSf ) Standard mode High-speed mode tBUFO 0.5tSCLO -1tcyc Standard mode ( -tSr ) High-speed mode 0.5tSCLO -1tcyc Standard mode (-tSf ) High-speed mode 1tSCLO (-tSr ) Standard mode High-speed mode tSTOSO 0.5tSCLO + 2tcyc (-tSr ) Standard mode High-speed mode Standard mode High-speed mode Standard mode High-speed mode -1000 -300 -250 -250 -1000 -300 -250 -250 -1000 -300 -1000 -300 -1000 -300 -1000 -300 I C Bus Specification (Min.) 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 100 2 2 Item tSCLHO tcyc Indication 0.5tSCLO (-tSr) o= 5 MHz 4000 950 4750 1000* 3800* 750* 1 1 o= 8 MHz 4000 950 4750 1000* 3875* 825* 1 1 o= o= 10 MHz 16 MHz 4000 950 4750 1000* 3900* 850* 1 1 o= 20 MHz 4000 950 4750 4000 950 4750 1000* 3938* 888* 1 1 1000* 3950* 900* 1 1 1 1 1 1 1 tSTAHO 4550 800 9000 2200 4400 1350 3100 400 1300 -1400* 1 4625 875 9000 2200 4250 1200 3325 625 2200 -500* 1 4650 900 9000 2200 4200 1150 3400 700 2500 -200* 1 4688 938 9000 2200 4125 1075 3513 813 2950 250 4700 950 9000 2200 4100 1050 3550 850 3100 400 tSTASO tSDASO (master) 1tSCLLO* - 3tcyc (-tSr ) 3 tSDASO (slave) 1tSCLL* - 2 12tcyc* (-tSr ) 3 501 Table 16.8 I C Bus Timing (with Maximum Influence of tSr/tSf) (cont) Time Indication (at Maximum Transfer Rate) [ns] tSr/tSf Influence (Max.) Standard mode High-speed mode 2 2 Item tSDAHO tcyc Indication 3tcyc I C Bus Specification (Min.) 0 0 2 o= 5 MHz 600 600 o= 8 MHz 375 375 o= o= 10 MHz 16 MHz 300 300 188 188 o= 20 MHz 150 150 0 0 Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the 2 maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL - 6tcyc). 2 3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). 502 * Note on ICDR Read at End of Master Reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR, and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the bus has been released, then read the ICDR register with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 16.18 (after confirming that the BBSY bit has been cleared to 0 in the ICCR register). Stop condition (a) SDA SCL Internal clock BBSY bit Master receive mode ICDR reading prohibited Bit 0 8 A 9 Start condition Execution of stop condition issuance instruction (0 written to BBSY and SCP) Confirmation of stop condition generation (0 read from BBSY) Start condition issuance Figure 16.18 Points for Attention Concerning Reading of Master Receive Data 503 504 Section 17 Host Interface Provided in the H8S/2138 Series; not provided in the H8S/2134 Series. 17.1 Overview The H8S/2138 Series has an on-chip host interface (HIF) that enables connection to an ISA bus, widely used as the internal bus in personal computers. The host interface provides a dualchannel parallel interface between the on-chip CPU and a host processor. The host interface is available only when the HI12E bit is set to 1 in SYSCR2. This mode is called slave mode, because it is designed for a master-slave communication system in which the H8S/2138 Series chip is slaved to a host processor. 17.1.1 Features The features of the host interface are summarized below. The host interface consists of 4-byte data registers, 2-byte status registers, a 1-byte control register, fast A20 gate logic, and a host interrupt request circuit. Communication is carried out via five control signals from the host processor (&6, &6 or (&6, HA0, ,25, and ,2:), four output signals to the host processor (GA20, HIRQ1, HIRQ11, and HIRQ12), and an 8-bit bidirectional command/data bus (HDB7 to HDB0). The &6 and &6 (or (&6) signals select one of the two interface channels. 505 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the host interface. (Internal interrupt signals) IBF2 IBF1 HDB7 to HDB0 CS1 CS2/ECS2 IOR IOW HA0 Control logic IDR1 ODR1 Host data bus STR1 IDR2 ODR2 STR2 HICR Module data bus Host interrupt request Fast A20 gate control HIRQ1 HIRQ11 HIRQ12 GA20 HIFSD Port 4, Port 8 Internal data bus Legend: IDR1: Input data register 1 IDR2: Input data register 2 ODR1: Output data register 1 ODR2: Output data register 2 STR1: Status register 1 STR2: Status register 2 HICR: Host interface control register Bus interface Figure 17.1 Block Diagram of Host Interface 506 17.1.3 Input and Output Pins Table 17.1 lists the input and output pins of the host interface module. Table 17.1 Name I/O read I/O write Chip select 1 Chip select 2* Host Interface Input/Output Pins Abbreviation Port P93 P94 P95 P81 P90 P80 Input I/O Input Input Input Input Function Host interface read signal Host interface write signal Host interface chip select signal for IDR1, ODR1, STR1 Host interface chip select signal for IDR2, ODR2, STR2 Host interface address select signal. In host read access, this signal selects the status registers (STR1, STR2) or data registers (ODR1, ODR2). In host write access to the data registers (IDR1, IDR2), this signal indicates whether the host is writing a command or data. ,25 ,2: &6 &6 (&6 HA0 Command/data Data bus Host interrupt 1 HDB7 to HDB0 P37 to I/O P30 HIRQ1 P44 P43 P45 P81 P82 Output Output Output Output Input Host interface data bus Interrupt output 1 to host Interrupt output 11 to host Interrupt output 12 to host A20 gate control signal output Host interface shutdown control signal Host interrupt 11 HIRQ11 Host interrupt 12 HIRQ12 Gate A20 HIF shutdown GA20 HIFSD Note: * Selection of &6 or (&6 is by means of the CS2E bit in STCR and the FGA20E bit in HICR. Host interface channel 2 and the &6 pin can be used when CS2E = 1. When CS2E = 1, &6 is used when FGA20E =0, and (&6 is used when FGA20E = 1. In this manual, both are referred to as &6. 507 17.1.4 Register Configuration Table 17.2 lists the host interface registers. Host interface registers HICR, IDR1, IDR2, ODR1, ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR. Table 17.2 Host Interface Registers R/W Name System control register System control register 2 Host interface control register Input data register 1 Output data register 1 Status register 1 Input data register 2 Output data register 2 Status register 2 Module stop control register Abbreviation SYSCR SYSCR2 HICR IDR1 ODR1 STR1 IDR2 ODR2 STR2 MSTPCRH MSTPCRL Slave R/W* R/W R/W R R/W R/(W)* R R/W R/(W)* R/W R/W 2 2 1 Host -- -- -- W R R W R R -- -- Initial Value H'09 H'00 H'F8 -- -- H'00 -- -- H'00 H'3F H'FF Slave 3 Address* H'FFC4 H'FF83 H'FFF0 H'FFF4 H'FFF5 H'FFF6 H'FFFC H'FFFD H'FFFE H'FF86 H'FF87 Master Address* 4 $ -- -- -- 0 0 0 1 1 1 -- -- $ -- -- -- 1 1 1 0 0 0 -- -- HA0 -- -- -- 0/1* 0 1 0/1* 0 1 -- -- 5 5 Notes: 1. Bits 5 and 3 are read-only bits. 2. The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave processor. 3. Address when accessed from the slave processor. The lower 16 bits of the address are shown. 4. Pin inputs used in access from the host processor. 5. The HA0 input discriminates between writing of commands and data. 508 17.2 17.2.1 Bit Register Descriptions System Control Register (SYSCR) 7 CS2E 0 R/W 6 IOSE 0 R/W 5 INTM1 0 R 4 INTM0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W Initial value Read/Write SYSCR is an 8-bit readable/writable register which controls H8S/2138 Series chip operations. Of the host interface registers, HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2 can only be accessed when the HIE bit is set to 1. The host interface &6 and (&6 pins are controlled by the CS2E bit in SYSCR and the FGA20E bit in HICR. See section 3.2.2, System Control Register (SYSCR), and section 5.2.1, System Control Register (SYSCR), for information on other SYSCR bits. SYSCR is initialized to H'09 by a reset and in hardware standby mode. Bit 7--CS2 Enable Bit (CS2E): Used together with the FGA20E bit in HICR to select the pin that performs the &6 function. SYSCR Bit 7 CS2E 0 HICR Bit 0 FGA20E 0 1 1 0 1 Description &6 pin function halted (&6 fixed high internally) &6 pin function selected for P81/&6 pin &6 pin function selected for P90/(&6 pin (Initial value) Bit 1--Host Interface Enable (HIE): Enables or disables CPU access to the host interface registers. When enabled, the host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2) can be accessed. Bit 1 HIE 0 1 Description Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU access is disabled (Initial value) Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU access is enabled 509 17.2.2 Bit System Control Register 2 (SYSCR2) 7 KWUL1 6 KWUL0 0 R/W 5 P6PUE 0 R/W 4 -- 0 -- 3 SDE 0 R/W 2 CS4E 0 R/W 1 CS3E 0 R/W 0 HI12E 0 R/W Initial value Read/Write 0 R/W SYSCR2 is an 8-bit readable/writable register which controls chip operations. Host interface functions are enabled or disabled by the HI12E bit in SYSCR2. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6--Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level can be set and changed by software. For details see section 8, I/O Ports. Bit 5--Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for the port 6 MOS input pull-up function connected by means of KMPCR settings. For details see section 8, I/O Ports. Bit 4--Reserved: Do not write 1 to this bit. Bit 3--Shutdown Enable (SDE): Enables or disables the host interface pin shutdown function. When this function is enabled, host interface pin functions can be halted, and the pins placed in the high-impedance state, according to the state of the HIFSD pin. Bit 3 SDE 0 1 Description Host interface pin shutdown function disabled Host interface pin shutdown function enabled (Initial value) Bit 2--CS4 Enable (CS4E): Reserved. Do not write 1 to this bit. Bit 1--CS3 Enable (CS3E): Reserved. Do not write 1 to this bit. Bit 0--Host Interface Enable Bit (HI12E): Enables or disables host interface functions in single-chip mode. When the host interface functions are enabled, slave mode is entered and processing is performed for data transfer between the slave and host. Bit 0 HI12E 0 1 Description Host interface functions are disabled Host interface functions are enabled (Initial value) 510 17.2.3 Bit Host Interface Control Register (HICR) 7 -- 1 -- -- 6 -- 1 -- -- 5 -- 1 -- -- 4 -- 1 -- -- 3 -- 1 -- -- 2 IBFIE2 0 R/W -- 1 0 R/W -- 0 0 R/W -- IBFIE1 FGA20E Initial value Slave Read/Write Host Read/Write HICR is an 8-bit readable/writable register which controls host interface interrupts and the fast A20 gate function. HICR is initialized to H'F8 by a reset and in hardware standby mode. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1. Bit 2--Input Data Register Full Interrupt Enable 2 (IBFIE2): Enables or disables the IBF2 interrupt to the internal CPU. Bit 2 IBFIE2 0 1 Description Input data register (IDR2) receive complete interrupt is disabled Input data register (IDR2) receive complete interrupt is enabled (Initial value) Bit 1-- Input Data Register Full Interrupt Enable 1 (IBFIE1): Enables or disables the IBF1 interrupt to the internal CPU. Bit 1 IBFIE1 0 1 Description Input data register (IDR1) receive complete interrupt is disabled Input data register (IDR1) receive complete interrupt is enabled (Initial value) Bit 0--Fast Gate A20 Enable (FGA20E): Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, a regular-speed A20 gate signal can be implemented by using firmware to manipulate the P81 output. Bit 0 FGA20E 0 1 Description Fast A20 gate function is disabled Fast A20 gate function is enabled (Initial value) 511 17.2.4 Bit Input Data Register 1 (IDR1) 7 IDR7 -- R W 6 IDR6 -- R W 5 IDR5 -- R W 4 IDR4 -- R W 3 IDR3 -- R W 2 IDR2 -- R W 1 IDR1 -- R W 0 IDR0 -- R W Initial value Slave Read/Write Host Read/Write IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host processor. When &6 is low, information on the host data bus is written into IDR1 at the rising edge of ,2:. The HA0 state is also latched into the C/' bit in STR1 to indicate whether the written information is a command or data. The initial values of IDR1 after a reset and in standby mode are undetermined. 17.2.5 Bit Initial value Slave Read/Write Host Read/Write Output Data Register 1 (ODR1) 7 ODR7 -- R/W R 6 ODR6 -- R/W R 5 ODR5 -- R/W R 4 ODR4 -- R/W R 3 ODR3 -- R/W R 2 ODR2 -- R/W R 1 ODR1 -- R/W R 0 ODR0 -- R/W R ODR1 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register to the host processor. The ODR1 contents are output on the host data bus when HA0 is low, &6 is low, and ,25 is low. The initial values of ODR1 after a reset and in standby mode are undetermined. 512 17.2.6 Bit Status Register 1 (STR1) 7 DBU 0 R/W R 6 DBU 0 R/W R 5 DBU 0 R/W R 4 DBU 0 R/W R 3 C/D 0 R R 2 DBU 0 R/W R 1 IBF 0 R R 0 OBF 0 R/(W)* R Initial value Slave Read/Write Host Read/Write Note: * Only 0 can be written, to clear the flag. STR1 is an 8-bit register that indicates status information during host interface processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors. STR1 is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4 and Bit 2--Defined by User (DBU): The user can use these bits as necessary. Bit 3--Command/Data (C/): Receives the HA0 input when the host processor writes to IDR1, and indicates whether IDR1 contains data or a command. Bit 3 C/' ' 0 1 Description Contents of input data register (IDR1) are data Contents of input data register (IDR1) are a command (Initial value) Bit 1--Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR1. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads IDR1. The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 17.8, Fast A20 Gate Output Signals. Bit 1 IBF 0 1 Description [Clearing condition] When the slave processor reads IDR1 [Setting condition] When the host processor writes to IDR1 (Initial value) 513 Bit 0--Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to 0 when the host processor reads ODR1. Bit 0 OBF 0 Description [Clearing condition] When the host processor reads ODR1 or the slave writes 0 in the OBF bit (Initial value) 1 [Setting condition] When the slave processor writes to ODR1 Table 17.3 shows the conditions for setting and clearing the STR1 flags. Table 17.3 Set/Clear Timing for STR1 Flags Flag C/' IBF* OBF Setting Condition Rising edge of host's write signal (,2:) when HA0 is high Rising edge of host's write signal (,2:) when writing to IDR1 Falling edge of slave's internal write signal (:5) when writing to ODR1 Clearing Condition Rising edge of host's write signal (,2:) when HA0 is low Falling edge of slave's internal read signal (5') when reading IDR1 Rising edge of host's read signal (,25) when reading ODR1 Note: * The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 17.8, Fast A20 Gate Output Signals. 17.2.7 Bit Input Data Register 2 (IDR2) 7 IDR7 -- R W 6 IDR6 -- R W 5 IDR5 -- R W 4 IDR4 -- R W 3 IDR3 -- R W 2 IDR2 -- R W 1 IDR1 -- R W 0 IDR0 -- R W Initial value Slave Read/Write Host Read/Write IDR2 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host processor. When &6 is low, information on the host data bus is written into IDR2 at the rising edge of ,2:. The HA0 state is also latched into the C/' bit in STR2 to indicate whether the written information is a command or data. The initial values of IDR2 after a reset and in standby mode are undetermined. 514 17.2.8 Bit Output Data Register 2 (ODR2) 7 ODR7 -- R/W R 6 ODR6 -- R/W R 5 ODR5 -- R/W R 4 ODR4 -- R/W R 3 ODR3 -- R/W R 2 ODR2 -- R/W R 1 ODR1 -- R/W R 0 ODR0 -- R/W R Initial value Slave Read/Write Host Read/Write ODR2 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register to the host processor. The ODR2 contents are output on the host data bus when HA0 is low, &6 is low, and ,25 is low. The initial values of ODR2 after a reset and in standby mode are undetermined. 17.2.9 Bit Initial value Slave Read/Write Host Read/Write Status Register 2 (STR2) 7 DBU 0 R/W R 6 DBU 0 R/W R 5 DBU 0 R/W R 4 DBU 0 R/W R 3 C/D 0 R R 2 DBU 0 R/W R 1 IBF 0 R R 0 OBF 0 R/(W)* R Note: * Only 0 can be written, to clear the flag. STR2 is an 8-bit register that indicates status information during host interface processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors. STR2 is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4 and Bit 2--Defined by User (DBU): The user can use these bits as necessary. Bit 3--Command/Data (C/): Receives the HA0 input when the host processor writes to IDR2, and indicates whether IDR2 contains data or a command. Bit 3 C/' ' 0 1 Description Contents of input data register (IDR2) are data Contents of input data register (IDR2) are a command (Initial value) 515 Bit 1--Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads IDR2. The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 17.8, Fast A20 Gate Output Signals. Bit 1 IBF 0 1 Description [Clearing condition] When the slave processor reads IDR2 [Setting condition] When the host processor writes to IDR2 (Initial value) Bit 0--Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared to 0 when the host processor reads ODR2. The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 17.8, Fast A20 Gate Output Signals. Bit 0 OBF 0 Description [Clearing condition] When the host processor reads ODR2 or the slave writes 0 in the OBF bit (Initial value) 1 [Setting condition] When the slave processor writes to ODR2 Table 17.4 shows the conditions for setting and clearing the STR2 flags. Table 17.4 Set/Clear Timing for STR2 Flags Flag C/' IBF* OBF Setting Condition Rising edge of host's write signal (,2:) when HA0 is high Rising edge of host's write signal (,2:) when writing to IDR2 Falling edge of slave's internal write signal (:5) when writing to ODR2 Clearing Condition Rising edge of host's write signal (,2:) when HA0 is low Falling edge of slave's internal read signal (5') when reading IDR2 Rising edge of host's read signal (,25) when reading ODR2 Note: * The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 17.8, Fast A20 Gate Output Signals. 516 17.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit Initial value Read/Write 7 6 5 4 3 2 1 0 7 6 5 MSTPCRL 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP2 bit is set to 1, the host interface halts and enters module stop mode. See section 23.5, Module Stop Mode, for details. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRL Bit 2--Module Stop (MSTP2): Specifies host interface module stop mode. MSTPCRL Bit 2 MSTP2 0 1 Description Host interface module stop mode is cleared Host interface module stop mode is set (Initial value) 517 17.3 17.3.1 Operation Host Interface Operation The host interface is activated by setting the HI12E bit (bit 0) to 1 in SYSCR2 in single-chip mode, establishing slave mode. Activation of the host interface (entry to slave mode) appropriates the related I/O lines in port 3 (data), port 8 or 9 (control) and port 4 (host interrupt requests) for interface use. Table 17.5 shows HIF host interface channel selection and pin operation. Table 17.5 Host Interface Channel Selection and Pin Operation HI12E 0 1 CS2E -- 0 Operation Host interface functions halted Host interface channel 1 only operating Operation of channel 2 halted (No operation as &6 or (&6 input. Pins P43, P81, and P90 operate as I/O ports.) 1 Host interface channel 1 and 2 functions operating For host read/write timing, see section 24.3.4, On-Chip Supporting Module Timing. 518 17.3.2 Control States Table 17.6 indicates the slave operations carried out in response to host interface signals from the host processor. Table 17.6 Host Interface Operation &6 1 &6 0 ,25 0 ,2: 0 HA0 0 1 Operation Setting prohibited Setting prohibited Data read from output data register 1 (ODR1) Status read from status register 1 (STR1) Data write to input data register 1 (IDR1) Command write to input data register 1 (IDR1) Idle state Idle state Setting prohibited Setting prohibited Data read from output data register 2 (ODR2) Status read from status register 2 (STR2) Data write to input data register 2 (IDR2) Command write to input data register 2 (IDR2) Idle state Idle state 1 0 1 1 0 0 1 1 0 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 519 17.3.3 A20 Gate The A20 gate signal can mask address A20 to emulate an addressing mode used by personal computers with an 8086*-family CPU. In slave mode, a regular-speed A20 gate signal can be output under firmware control, or a fast A20 gate signal can be output under hardware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR (H'FFF0). Note: * Intel microprocessor. Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor receives data, it normally uses an interrupt routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command, software copies bit 1 of the data and outputs it at the gate A20 pin. Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host processor can manipulate the output from this pin by sending commands and data. This function is available only when register IDR1 is accessed using &6. Slave logic decodes the commands input from the host processor. When an H'D1 host command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 17.7 lists the conditions that set and clear GA20 (P81). Figure 17.2 shows the GA20 output in flowchart form. Table 17.8 indicates the GA20 output signal values. Table 17.7 GA20 (P81) Set/Clear Timing Pin Name GA20 (P81) Setting Condition Rising edge of the host's write signal (,2:) when bit 1 of the written data is 1 and the data follows an H'D1 host command Clearing Condition Rising edge of the host's write signal (,2:) when bit 1 of the written data is 0 and the data follows an H'D1 host command Also, when bit FGA20E in HICR is cleared to 0 520 Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to DR bit of P81/GA20 Figure 17.2 GA20 Output 521 Table 17.8 Fast A20 Gate Output Signal HA0 1 0 1 1 0 1 1 0 1/0 1 0 1/0 1 1 1 1 1 0 1 Notes: Data/Command H'D1 command 1 1 data* H'FF command H'D1 command 2 0 data* H'FF command H'D1 command 1 1 data* Command other than H'FF and H'D1 H'D1 command 2 0 data* Command other than H'FF and H'D1 H'D1 command Command other than H'D1 H'D1 command H'D1 command Internal CPU Interrupt Flag (IBF) 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 GA20 (P81) Q 1 Q (1) Q 0 Q (0) Q 1 Q (1) Q 0 Q (0) Q Q Q Q Q 1/0 Q(1/0) Remarks Turn-on sequence Turn-off sequence Turn-on sequence (abbreviated form) Turn-off sequence (abbreviated form) Cancelled sequence Retriggered sequence Consecutively executed sequences H'D1 command 0 Any data 0 H'D1 command 0 1. Arbitrary data with bit 1 set to 1. 2. Arbitrary data with bit 1 cleared to 0. 522 17.3.4 Host Interface Pin Shutdown Function Host interface output can be placed in the high-impedance state according to the state of the HIFSD pin. Setting the SDE bit to 1 in the SYSCR2 register enables the HIFSD pin is slave mode. The HIF constantly monitors the HIFSD pin, and when this pin goes low, places the host interface output pins (HIRQ1, HIRQ11, HIRQ12, and GA20) in the high-impedance state. At the same time, the host interface input pins (&6, &6 or (&6, ,2:, ,25, and HA0) are disabled (fixed at the high input state internally) regardless of the pin states, and the signals of the multiplexed functions of these pins (input block) are similarly fixed internally. As a result, the host interface I/O pins (HDB7 to HDB0) also go to the high-impedance state. This state is maintained while the HIFSD pin is low, and when the HIFSD pin returns to the high-level state, the pins are restored to their normal operation as host interface pins. Table 17.9 shows the scope of HIF pin shutdown in slave mode. Table 17.9 Scope of HIF Pin Shutdown in Slave Mode Scope of Shutdown in Slave Mode O O O O O Abbreviation ,25 ,2: &6 &6 (&6 HA0 HDB7 to HDB0 HIRQ11 HIRQ1 HIRQ12 GA20 Port P93 P94 P95 P81 P90 P80 P37 to P30 P43 P44 P45 P81 I/O Input Input Input Input Input Input I/O Selection Conditions Slave mode Slave mode Slave mode Slave mode and CS2E = 1 and FGA20E = 0 Slave mode and CS2E = 1 and FGA20E = 1 Slave mode Slave mode Output Slave mode and CS2E = 1 and P43DDR = 1 Output Slave mode and P44DDR = 1 Output Slave mode and P45DDR = 1 Output Slave mode and FGA20E = 1 HIFSD P82 -- Input Slave mode and SDE = 1 Notes: Slave mode: Single-chip mode and HI12E = 1 O: Pins shut down by shutdown function The ,54/$'75* input signal is also fixed in the case of P90 shutdown, the TMCI1/HSYNCI signal in the case of P43 shutdown, and the TMRI/CSYNCI in the case of P45 shutdown. : Pins shut down only when the HIF function is selected by means of a register setting --: Pin not shut down 523 17.4 17.4.1 Interrupts IBF1, IBF2 The host interface can issue two interrupt requests to the slave CPU: IBF1 and IBF2. They are input buffer full interrupts for input data registers IDR1 and IDR2 respectively. Each interrupt is enabled when the corresponding enable bit is set. Table 17.10 Input Buffer Full Interrupts Interrupt IBF1 IBF2 Description Requested when IBFIE1 is set to 1 and IDR1 is full Requested when IBFIE2 is set to 1 and IDR2 is full 17.4.2 HIRQ11, HIRQ1, and HIRQ12 In slave mode (single-chip mode, with HI12E = 1 in SYSCR2), bits P45DR to P43DR in the port 4 data register (P4DR) can be used as host interrupt request latches. These three P4DR bits are cleared to 0 by the host processor's read signal (,25). If &6 and HA0 are low, when ,25 goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared to 0. If &6 and HA0 are low, when ,25 goes low and the host reads ODR2, HIRQ11 is cleared to 0. To generate a host interrupt request, normally on-chip firmware writes 1 in the corresponding bit. In processing the interrupt, the host's interrupt handling routine reads the output data register (ODR1 or ODR2), and this clears the host interrupt latch to 0. Table 17.11 indicates how these bits are set and cleared. Figure 17.3 shows the processing in flowchart form. Table 17.11 HIRQ Setting/Clearing Conditions Host Interrupt Signal HIRQ11 (P43) HIRQ1 (P44) HIRQ12 (P45) Setting Condition Slave CPU reads 0 from bit P43DR, then writes 1 Slave CPU reads 0 from bit P44DR, then writes 1 Slave CPU reads 0 from bit P45DR, then writes 1 Clearing Condition Slave CPU writes 0 in bit P43DR, or host reads output data register 2 Slave CPU writes 0 in bit P44DR, or host reads output data register 1 Slave CPU writes 0 in bit P45DR, or host reads output data register 1 524 Slave CPU Master CPU Write to ODR Write 1 to P4DR HIRQ output high HIRQ output low P4DR = 0? Yes All bytes transferred? Yes Interrupt initiation ODR read No No Hardware operations Software operations Figure 17.3 HIRQ Output Flowchart HIRQ Setting/Clearing Contention: If there is contention between a P4DR read/write by the CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) clearing by the host, clearing by the host is held pending during the P4DR read/write by the CPU. P4DR clearing is executed after completion of the read/write. 17.5 Usage Note The host interface provides buffering of asynchronous data from the host and slave processors, but an interface protocol must be followed to implement necessary functions and avoid data contention. For example, if the host and slave processors try to access the same input or output data register simultaneously, the data will be corrupted. Interrupts can be used to design a simple and effective protocol. Also, if &6 and &6 or (&6 are driven low simultaneously in attempting IDR or ODR access, signal contention will occur within the chip, and a through-current may result. This usage must therefore be avoided. 525 526 Section 18 D/A Converter 18.1 Overview The H8S/2138 Series and H8S/2134 Series have an on-chip D/A converter module with two channels. 18.1.1 Features Features of the D/A converter module are listed below. * * * * * Eight-bit resolution Two-channel output Maximum conversion time: 10 s (with 20-pF load capacitance) Output voltage: 0 V to AVCC D/A output retention in software standby mode 527 18.1.2 Block Diagram Figure 18.1 shows a block diagram of the D/A converter. Module data bus Bus interface Internal data bus AVCC DADR0 DADR1 8-bit D/A DA1 AVSS Control circuit Legend: DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 Figure 18.1 Block Diagram of D/A Converter 528 DACR DA0 18.1.3 Input and Output Pins Table 18.1 lists the input and output pins used by the D/A converter module. Table 18.1 Input and Output Pins of D/A Converter Module Name Analog supply voltage Analog ground Analog output 0 Analog output 1 Abbreviation AVCC AVSS DA0 DA1 I/O Input Input Output Output Function Power supply for analog circuits Ground and reference voltage for analog circuits Analog output channel 0 Analog output channel 1 18.1.4 Register Configuration Table 18.2 lists the registers of the D/A converter module. Table 18.2 D/A Converter Registers Name D/A data register 0 D/A data register 1 D/A control register Module stop control register Abbreviation DADR0 DADR1 DACR MSTPCRH MSTPCRL Note: * Lower 16 bits of the address. R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'3F H'FF Address* H'FFF8 H'FFF9 H'FFFA H'FF86 H'FF87 529 18.2 18.2.1 Bit Register Descriptions D/A Data Registers 0 and 1 (DADR0, DADR1) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value Read/Write D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit readable/writable registers that store data to be converted. When analog output is enabled, the value in the D/A data register is converted and output continuously at the analog output pin. The D/A data registers are initialized to H'00 by a reset and in hardware standby mode. 18.2.2 Bit Initial value Read/Write D/A Control Register (DACR) 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- DACR is an 8-bit readable/writable register that controls the operation of the D/A converter module. DACR is initialized to H'1F by a reset and in hardware standby mode. Bit 7--D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 0 1 Description Analog output DA1 is disabled (Initial value) D/A conversion is enabled on channel 1. Analog output DA1 is enabled 530 Bit 6--D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 0 1 Description Analog output DA0 is disabled (Initial value) D/A conversion is enabled on channel 0. Analog output DA0 is enabled Bit 5--D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0. Channels 0 and 1 are controlled together when DAE = 1. Output of the converted results is always controlled independently by DAOE0 and DAOE1. Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE * 0 1 1 0 0 1 1 *: Don't care * D/A conversion Disabled on channels 0 and 1 Enabled on channel 0 Disabled on channel 1 Enabled on channels 0 and 1 Disabled on channel 0 Enabled on channel 1 Enabled on channels 0 and 1 Enabled on channels 0 and 1 If the H8S/2138 Series chip enters software standby mode while D/A conversion is enabled, the D/A output is retained and the analog power supply current is the same as during D/A conversion. If it is necessary to reduce the analog power supply current in software standby mode, disable D/A output by clearing both the DAOE0, DAOE1 and DAE bits to 0. Bits 4 to 0--Reserved: These bits cannot be modified and are always read as 1. 531 18.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 Bit Initial value Read/Write 7 6 5 4 3 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP10 bit is set to 1, the D/A converter halts and enters module stop mode at the end of the bus cycle. See section 23.5, Module Stop Mode, for details. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 10--Module Stop (MSTP10): Specifies D/A converter module stop mode. MSTPCRH Bit 2 MSTP10 0 1 Description D/A converter module stop mode is cleared D/A converter module stop mode is set (Initial value) 532 18.3 Operation The D/A converter module has two built-in D/A converter circuits that can operate independently. D/A conversion is performed continuously whenever enabled by the D/A control register (DACR). When a new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The converted result is output by setting the DAOE0 or DAOE1 bit to 1. An example of conversion on channel 0 is given next. Figure 18.2 shows the timing. * Software writes the data to be converted in DADR0. * D/A conversion begins when the DAOE0 bit in DACR is set to 1. After the elapse of the conversion time, analog output appears at the DA0 pin. Output of the converted result begins after the conversion time. The output value is AVcc x (DADR value)/256. This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0. * If a new value is written in DADR0, conversion begins immediately. Output of the converted result begins after the conversion time. * When the DAOE0 bit is cleared to 0, DA0 becomes an input pin. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle O Address DADR0 Conversion data (1) Conversion data (2) DAOE0 DA0 High-impedance state t DCONV Conversion result (1) Conversion result (2) t DCONV t DCONV: D/A conversion time Figure 18.2 D/A Conversion (Example) 533 534 Section 19 A/D Converter 19.1 Overview The H8S/2138 Series and H8S/2134 Series incorporate a 10-bit successive-approximations A/D converter that allows up to eight analog input channels to be selected. In addition to the eight analog input channels, up to 8 channels of digital input can be selected for A/D conversion. Since the conversion precision falls to the equivalent of 6-bit resolution when digital input is selected, digital input is ideal for use by a comparator identifying multivalued inputs, for example. 19.1.1 Features A/D converter features are listed below. * 10-bit resolution * Eight (analog) or 8 (digital) input channels * Settable analog conversion voltage range The analog conversion voltage range is set using the analog power supply voltage pin (AVcc) as the analog reference voltage * High-speed conversion Minimum conversion time: 6.7 s per channel (at 20 MHz operation) * Choice of single mode or scan mode Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Choice of software or timer conversion start trigger (8-bit timer), or $'75* pin * A/D conversion end interrupt generation An A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion 535 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the A/D converter. Module data bus Bus interface ADDRC ADDRD ADDRA ADDRB ADCSR Internal data bus AVCC 10-bit D/A AVSS Successive approximations register AN0 AN1 Multiplexer + - Comparator Sample-andhold circuit Control circuit o/16 o/8 AN2 AN3 AN4 AN5 AN6/CIN0 to CIN7 AN7 ADCR ADI interrupt signal ADTRG Conversion start trigger from 8-bit timer A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: Figure 19.1 Block Diagram of A/D Converter 536 19.1.3 Pin Configuration Table 19.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. Table 19.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Expansion A/D input pins 0 to 7 Symbol AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O Input Input Input Input Input Input Input Input Input Input Input Input Function Analog block power supply Analog block ground and A/D conversion reference voltage Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7 External trigger input for starting A/D conversion Expansion A/D conversion input (digital input pin) channels 0 to 7 $'75* CIN0 to CIN7 537 19.1.4 Register Configuration Table 19.2 summarizes the registers of the A/D converter. Table 19.2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCRH MSTPCRL Keyboard comparator control register KBCOMP R/W R R R R R R R R R/(W)* R/W R/W R/W R/W 2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'3F H'FF H'00 Address*1 H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FF86 H'FF87 H'FEE4 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written in bit 7, to clear the flag. 538 19.2 19.2.1 Bit Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value Read/Write There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 19.3. The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 19.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Table 19.3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 or CIN0 to CIN7 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD 539 19.2.2 Bit A/D Control/Status Register (ADCSR) 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value Read/Write Note: * Only 0 can be written in bit 7, to clear the flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations. ADCSR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7--A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing conditions] * * 1 * * When 0 is written in the ADF flag after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels (Initial value) [Setting conditions] Bit 6--A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request is disabled A/D conversion end interrupt (ADI) request is enabled (Initial value) 540 Bit 5--A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin ($'75*). Bit 5 ADST 0 1 Description A/D conversion stopped (Initial value) Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode Bit 4--Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 19.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped. Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3--Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time while ADST = 0. Bit 3 CKS 0 1 Description Conversion time = 266 states (max.) Conversion time = 134 states (max.) (Initial value) 541 Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channel(s). One analog input channel can be switched to digital input. Only set the input channel while conversion is stopped. Group Selection CH2 0 CH1 0 Channel Selection CH0 0 1 1 0 1 1 0 0 1 1 0 1 Single Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 or CIN0 to CIN7 AN7 Description Scan Mode (Initial value) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4, AN5, AN6 or CIN0 to CIN7 AN4, AN5, AN6 or CIN0 to CIN7 AN7 542 19.2.3 Bit A/D Control Register (ADCR) 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value Read/Write ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bits 7 and 6--Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped. Bit 7 TRGS1 0 Bit 6 TRGS0 0 1 1 0 1 Description Start of A/D conversion by external trigger is disabled Start of A/D conversion by external trigger is disabled Start of A/D conversion by external trigger (8-bit timer) is enabled Start of A/D conversion by external trigger pin is enabled (Initial value) Bits 5 to 0--Reserved: These bits cannot be modified and are always read as 1. 543 19.2.4 Keyboard Comparator Control Register (KBCOMP) Bit 7 IrE Initial value Read/Write 0 R/W 6 IrCKS2 0 R/W 5 IrCKS1 0 R/W 4 IrCKS0 0 R/W 3 KBADE 0 R/W 2 KBCH2 0 R/W 1 KBCH1 0 R/W 0 KBCH0 0 R/W KBCOMP is an 8-bit readable/writable register that controls the SCI2 IrDA function and selects the CIN input channels for A/D conversion. KBCOMP is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4--IrDA Control: See the description in section 15.2.11, Keyboard Comparator Control Register (KBCOMP). Bit 3--Keyboard A/D Enable: Selects either analog input pin (AN6) or digital input pin (CIN0 to CIN7) for A/D converter channel 6 input. If digital input pins are selected, input on A/D converter channel 7 will not be converted correctly. Bits 2 to 0--Keyboard A/D Channel Select 2 to 0 (KBCH2 to KBCH0): These bits select the channels for A/D conversion from among the digital input pins. Only set the input channel while A/D conversion is stopped. Bit 3 KBADE 0 1 Bit 2 KBCH2 -- 0 Bit 1 KBCH1 -- 0 Bit 0 KBCH0 -- 0 1 1 0 1 1 0 0 1 1 0 1 A/D Converter Channel 6 Input AN6 CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 A/D Converter Channel 7 Input AN7 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 544 19.2.5 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 Bit Initial value Read/Write 7 6 5 4 3 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 23.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRH Bit 1--Module Stop (MSTP9): Specifies the A/D converter module stop mode. MSTPCRH Bit 1 MSTP9 0 1 Description A/D converter module stop mode is cleared A/D converter module stop mode is set (Initial value) 545 19.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, but the data bus to the bus master is only 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 19.2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 19.2 ADDR Access Operation (Reading H'AA40) 546 19.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 19.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 19.3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADCSR, then writes 0 to the ADF flag. 6. The routine reads and processes the conversion result (ADDRB). 7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. 547 Set* ADIE ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Idle Idle Idle Idle A/D conversion 1 A/D conversion starts Set* Clear* Set* Clear* Idle A/D conversion 2 Idle ADDRA ADDRB ADDRC ADDRD Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 19.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 548 19.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 19.4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). 549 Continuous A/D conversion execution Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle A/D conversion 1 Clear*1 Clear*1 Idle A/D conversion 2 A/D conversion 4 Idle A/D conversion 5 *2 Idle A/D conversion 3 Idle Idle Idle Figure 19.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) 550 19.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 19.5 shows the A/D conversion timing. Table 19.4 indicates the A/D conversion time. As indicated in figure 19.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 19.4. In scan mode, the values given in table 19.4 apply to the first conversion time. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. (1) o Address (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time Figure 19.5 A/D Conversion Timing 551 Table 19.4 A/D Conversion Time (Single Mode) CKS = 0 Item A/D conversion start delay Input sampling time A/D conversion time Symbol tD tSPL tCONV Min 10 -- 259 Typ -- 63 -- Max 17 -- 266 Min 6 -- 131 CKS = 1 Typ -- 31 -- Max 9 -- 134 Note: Values in the table are the number of states. 19.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the $'75* pin. A falling edge at the $'75* pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit is set to 1 by software. Figure 19.6 shows the timing. o ADTRG Internal trigger signal ADST A/D conversion Figure 19.6 External Trigger Input Timing 552 19.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 19.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: 1. Analog input voltage range The voltage applied to the ANn analog input pins during A/D conversion should be in the range AVSS ANn AVCC (n = 0 to 7). 2. Digital input voltage range The voltage applied to the CINn digital input pins should be in the range AVSS CINn AVCC and VSS CINn VCC (n = 0 to 7). 3. Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. If conditions 1 to 3 above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) should be connected between AVCC and AVSS as shown in figure 19.7. Also, the bypass capacitors connected to AVCC and the filter capacitor connected to AN0 to AN7 must be connected to AVSS. If a filter capacitor is connected as shown in figure 19.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance 553 of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Rin* 2 *1 0.1 F AVSS 100 AN0 to AN7 Notes: Figures are reference values. 1. 10 F 0.01 F 2. R in: Input impedance Figure 19.7 Example of Analog Input Protection Circuit Table 19.5 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min -- -- Max 20 10* Unit pF k Note: * When VCC = 4.0 V to 5.5 V and o 12 MHz 10 k AN0 to AN7 To A/D converter 20 pF Note: Figures are reference values. Figure 19.8 Analog Input Pin Equivalent Circuit 554 A/D Conversion Precision Definitions: H8S/2138 Series and H8S/2134 Series A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 19.10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'111111111 (H'3FF) (see figure 19.10). * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 19.9). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. 555 Digital output H'3FF H'3FE H'3FD H'004 H'003 H'002 H'001 H'000 Ideal A/D conversion characteristic Quantization error 2 1 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 19.9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 19.10 A/D Conversion Precision Definitions (2) 556 Permissible Signal Source Impedance: H8S/2138 Series and H8S/2134 Series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k (Vcc = 4.0 to 5.5 V, when o 12 MHz or CKS = 0) or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k (Vcc = 4.0 to 5.5 V, when o 12 MHz or CKS = 0), charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. But since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/sec or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. Sensor output impedance, up to 10 k Sensor input Low-pass filter C to 0.1 F H8S/2138 Series or H8S/2134 Series A/D converter chip equivalent circuit 10 k Cin = 15 pF 20 pF Figure 19.11 Example of Analog Input Circuit 557 558 Section 20 RAM 20.1 Overview The H8S/2138, H8S/2134 and H8S/2133 have 4 kbytes of on-chip high-speed static RAM, and the H8S/2137, H8S/2132, and H8S/2130 have 2 kbytes. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 20.1.1 Block Diagram Figure 20.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFE080 H'FFE082 H'FFE084 H'FFE081 H'FFE083 H'FFE085 H'FFEFFE H'FFFF00 H'FFEFFF H'FFFF01 H'FFFF7E H'FFFF7F Figure 20.1 Block Diagram of RAM (H8S/2138, H8S/2134, H8S/2133) 559 20.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 20.1 shows the register configuration. Table 20.1 Register Configuration Name System control register Abbreviation SYSCR R/W R/W Initial Value H'09 Address* H'FFC4 Note: * Lower 16 bits of the address. 20.2 Bit System Control Register (SYSCR) 7 CS2E 0 R/W 6 IOSE 0 R/W 5 INTM1 0 R 4 INTM0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W Initial value Read/Write The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 560 20.3 20.3.1 Operation Expanded Mode (Modes 1, 2, and 3 (EXPE = 1)) When the RAME bit is set to 1, accesses to H8S/2138, H8S/2134, and H8S/2133 addresses H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2137, H8S/2132, and H8S/2130 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the on-chip RAM. When the RAME bit is cleared to 0, accesses to addresses H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the off-chip address space. Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to and read in byte or word units. Each type of access is performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 20.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0)) When the RAME bit is set to 1, accesses to H8S/2138, H8S/2134, and H8S/2133 addresses H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2137, H8S/2132, and H8S/2130 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the on-chip RAM. When the RAME bit is cleared to 0, the on-chip RAM is not accessed. A read will always return H'FF, and writes are invalid. Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to and read in byte or word units. Each type of access is performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 561 562 Section 21 ROM 21.1 Overview The H8S/2138 and H8S/2134 have 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2133 has 96 kbytes, the H8S/2137 and H8S/2132 have 64 kbytes, and the H8S/2130 has 32 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed. The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the on-chip ROM. The flash memory versions of the H8S/2138, H8S/2134, and H8S/2132 can be erased and programmed on-board as well as with a general-purpose PROM programmer. 21.1.1 Block Diagram Figure 21.1 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'01FFFE H'01FFFF Figure 21.1 ROM Block Diagram (H8S/2138, H8S/2134) 563 21.1.2 Register Configuration The H8S/2138 Series and H8S/2134 Series on-chip ROM is controlled by the operating mode and register MDCR. The register configuration is shown in table 21.1. Table 21.1 ROM Register Register Name Mode control register Abbreviation MDCR R/W R/W Initial Value Undefined Depends on the operating mode Address* H'FFC5 Note: * Lower 16 bits of the address. 21.2 21.2.1 Bit Register Descriptions Mode Control Register (MDCR) 7 EXPE --* R/W* 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 MDS1 --* R 0 MDS0 --* R Initial value Read/Write Note: * Determined by the MD1 and MD0 pins. MDCR is an 8-bit register used to set the H8S/2138 Series or H8S/2134 Series operating mode and monitor the current operating mode. The EXPE bit is initialized in accordance with the mode pin states by a reset and in hardware standby mode. Bit 7--Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, EXPE is fixed at 1 and cannot be modified. In modes 2 and 3, EXPE has an initial value of 0 and can be read or written. Bit 7 EXPE 0 1 Description Single-chip mode selected Expanded mode selected 564 Bits 6 to 2--Reserved: These bits cannot be modified and are always read as 0. Bits 1 and 0--Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified. When MDCR is read, the input levels of mode pins MD1 and MD0 are latched in these bits. 21.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data is accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the on-chip ROM, as shown in table 21.2. In normal mode, the maximum amount of ROM that can be used is 56 kbytes. Table 21.2 Operating Modes and ROM Mode Pins Operating Mode Mode 1 Mode 2 Normal expanded mode with on-chip ROM disabled Advanced single-chip mode Advanced expanded mode with on-chip ROM enabled Mode 3 Normal single-chip mode Normal expanded mode with on-chip ROM enabled 1 MD1 0 1 MD0 1 0 MDCR EXPE 1 0 1 0 1 Enabled (max. 56 kbytes) On-Chip ROM Disabled Enabled* Note: * 128 kbytes in the H8S/2138 and H8S/2134, 96 kbytes in the H8S/2133, 64 kbytes in the H8S/2137 and H8S/2132, and 32 kbytes in the H8S/2130. 565 21.4 21.4.1 Overview of Flash Memory Features The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units). When erasing multiple blocks, the individual blocks must be erased sequentially. Block erasing can be performed as required on 1-kbyte, 8-kbyte, 16-kbyte, 28kbyte, and 32-kbyte blocks. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 s (typ.) per byte, and the erase time is 100 ms (typ.) per block. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the H8S/2138 Series or H8S/2134 Series chip can be automatically adjusted to match the transfer bit rate of the host. * Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. * Writer mode Flash memory can be programmed/erased in writer mode, using a PROM programmer, as well as in on-board programming mode. 566 21.4.2 Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 * FLMCR2 * EBR1 EBR2 * * Bus interface/controller Operating mode Mode pins Flash memory (128 kbytes/64 kbytes) Legend: FLMCR1: FLMCR2: EBR1: EBR2: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Note: *These registers are used only in the flash memory version. In the mask ROM version, a read at any of these addresses will return an undefined value, and writes are invalid. Figure 21.2 Block Diagram of Flash Memory 567 21.4.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 21.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and writer mode. MD1 = 1 User mode with on-chip ROM enabled RES = 0 Reset state RES = 0 *1 RES = 0 *2 RES = 0 Writer mode SWE = 1 SWE = 0 User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. MD0 = MD1 = 0, P92 = 0, P91 = P90 = 1 2. MD1 = MD0 = 0, P92 = P91 = P90 = 1 Figure 21.3 Flash Memory Mode Transitions 568 On-Board Programming Modes * Boot mode 1. Initial state The flash memory is in the erased state when the device is shipped. The description here applies to the case where the old program version or data is being rewritten. The user should prepare the programming control program and new application program beforehand in the host. Host 2. SCI communication check When boot mode is entered, the boot program in the H8S/2138 or H8S/2134 Series chip (originally incorporated in the chip) is started, an SCI communication check is carried out, and the boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Programming control program New application program Programming control program New application program H8S/2138 or H8S/2134 Series chip Boot program H8S/2138 or H8S/2134 Series chip Boot program SCI SCI Flash memory RAM Flash memory RAM Boot program area Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host Programming control program New application program 4. Writing new application program The programming control program transferred from the host to RAM by SCI communication is executed, and the new application program in the host is written into the flash memory. Host H8S/2138 or H8S/2134 Series chip Boot program H8S/2138 or H8S/2134 Series chip Boot program SCI SCI Flash memory RAM Flash memory RAM Boot program area Programming control program Flash memory erase New application program Program execution state Figure 21.4 Boot Mode 569 * User program mode 1. Initial state (1) The program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program H8S/2138 or H8S/2134 Series chip Boot program Flash memory Transfer program RAM SCI New application program H8S/2138 or H8S/2134 Series chip Boot program Flash memory Transfer program Programming/ erase control program 2. Programming/erase control program transfer Executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host SCI RAM Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program H8S/2138 or H8S/2134 Series chip Boot program H8S/2138 or H8S/2134 Series chip Boot program SCI SCI Flash memory RAM Flash memory RAM Transfer program Transfer program Programming/ erase control program Programming/ erase control program Flash memory erase New application program Program execution state Figure 21.5 User Program Mode (Example) 570 Differences between Boot Mode and User Program Mode Boot Mode Entire memory erase Block erase Programming control program* 1 User Program Mode Yes Yes * 2, 3 Yes No * 2 Notes: 1. To be provided by the user, in accordance with the recommended algorithm. 2. Program/program-verify 3. Erase/erase-verify Block Configuration: The flash memory is divided into two 32-kbyte blocks (128-kbyte version only), two 8-kbyte blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks. Address H'00000 1 kbyte 1 kbyte 1 kbyte 1 kbyte 28 kbytes 16 kbytes 128 kbytes 8 kbytes 8 kbytes Address H'00000 1 kbyte 1 kbyte 1 kbyte 1 kbyte 32 kbytes 28 kbytes 64 kbytes 16 kbytes 8 kbytes 8 kbytes 32 kbytes Address H'1FFFF (a) 128-kbyte version Address H'0FFFF (b) 64-kbyte version Figure 21.6 Flash Memory Block Configuration 571 21.4.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 21.3. Table 21.3 Flash Memory Pins Pin Name Reset Mode 1 Mode 0 Port 92 Port 91 Port 90 Transmit data Receive data Abbreviation I/O Input Input Input Input Input Input Output Input Function Reset Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode when MD1 = MD0 = 0 Sets MCU operating mode when MD1 = MD0 = 0 Sets MCU operating mode when MD1 = MD0 = 0 Serial transmit data output Serial receive data input 5(6 MD1 MD0 P92 P91 P90 TxD1 RxD1 21.4.5 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 21.4. In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR. Table 21.4 Flash Memory Registers Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Serial/timer control register Abbreviation R/W FLMCR1* FLMCR2* EBR1* EBR2* STCR 5 5 5 Initial Value 3 Address*1 H'FF80* 2 2 R/W* R/W* R/W* R/W* R/W H'00 H'00* H'00* H'00* H'00 4 4 5 3 H'FF81* H'FF82* H'FF83* H'FFC3 3 2 3 4 2 Notes: 1. Lower 16 bits of the address. 2. Flash memory registers share addresses with other registers. Register selection is performed by the FLSHE bit in the serial/timer control register (STCR). 3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. 4. The SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. These registers are used only in the flash memory version. In the mask ROM version, a read at any of these addresses will return an undefined value, and writes are invalid. 572 21.5 21.5.1 Register Descriptions Flash Memory Control Register 1 (FLMCR1) Bit 7 FWE Initial value Read/Write 1 R 6 SWE 0 R/W 5 -- 0 -- 4 -- 0 -- 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1. Program mode is entered by setting SWE to 1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by setting SWE to 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is initialized to H'80 by a reset, and in hardware standby mode, software standby mode, subactive mode, subsleep mode, and watch mode. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the EV and PV bits in FLMCR1 are enabled only when SWE=1; writes to the E bit only when SWE = 1, and ESU = 1; and writes to the P bit only when SWE = 1, and PSU = 1. Bit 7--Flash Write Enable (FWE): Controls programming and erasing of the on-chip flash memory. This bit cannot be modified and is always read as 1. Bit 6--Software Write Enable (SWE): Enables or disables flash memory programming. SWE should be set before setting bits ESU, PSU, EV, PV, E, P, and EB9 to EB0, and should not be cleared at the same time as these bits. Bit 6 SWE 0 1 Description Writes disabled Writes enabled (Initial value) 573 Bit 5 and 4--Reserved: These bits cannot be modified and are always read as 0. Bit 3--Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When SWE = 1 (Initial value) Bit 2--Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When SWE = 1 (Initial value) Bit 1--Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When SWE = 1, and ESU = 1 (Initial value) 574 Bit 0--Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P 0 1 Description Program mode cleared Transition to program mode [Setting condition] When SWE = 1, and PSU = 1 (Initial value) 21.5.2 Flash Memory Control Register 2 (FLMCR2) Bit 7 FLER Initial value Read/Write 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 ESU 0 R/W 0 PSU 0 R/W FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, subactive mode, subsleep mode, and watch mode. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Bit 7--Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. Bit 7 FLER 0 1 Description Flash memory is operating normally value) Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 21.8.3, Error Protection (Initial 575 Bits 6 to 2--Reserved: These bits cannot be modified and are always read as 0. Bit 1--Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 1 ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] When SWE = 1 (Initial value) Bit 0--Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 0 PSU 0 1 Description Program setup cleared Program setup [Setting condition] When SWE = 1 (Initial value) 576 21.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) Bit EBR1 Initial value Read/Write Bit EBR2 Initial value Read/Write 7 -- 0 -- 7 EB7 0 R/W* 1 6 -- 0 -- 6 EB6 0 R/W 5 -- 0 -- 5 EB5 0 R/W 4 -- 0 -- 4 EB4 0 R/W 3 -- 0 -- 3 EB3 0 R/W 2 -- 0 -- 2 EB2 0 R/W 1 2 0 2 EB9/--* EB8/--* 0 1, 2 0 1, 2 R/W* * R/W* * 1 EB1 0 R/W 0 EB0 0 R/W Notes: 1. In normal mode, these bits cannot be modified and are always read as 0. 2. Bits EB8 and EB9 are not present in the 64-kbyte versions; they cannot be modified and are always read as 0. EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and 2 in EBR1 (128 kB versions only) and bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized to H'00 by a reset, in hardware standby mode, software standby mode, subactive mode, subsleep mode, and watch mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR1 or EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set). When onchip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 21.5. Table 21.5 Flash Memory Erase Blocks Block (Size) 128-kbyte Versions 64-kbyte Versions EB0 (1 kbyte) EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbytes) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) -- -- Address H'(00)0000 to H'(00)03FF H'(00)0400 to H'(00)07FF H'(00)0800 to H'(00)0BFF H'(00)0C00 to H'(00)0FFF H'(00)1000 to H'(00)7FFF H'(00)8000 to H'(00)BFFF H'(00)C000 to H'(00)DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF 577 21.5.4 Serial/Timer Control Register (STCR) Bit 7 IICS Initial value Read/Write 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W 3 FLSHE 0 R/W 2 -- 0 R/W 1 ICKS1 0 R/W 0 ICKS0 0 R/W STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), and on-chip flash memory control (in F-ZTAT versions), and also selects the TCNT input clock. For details on functions not related to on-chip flash memory, see section 3.2.4, Serial/Timer Control Register (STCR), and descriptions of individual modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4--I C Control (IICS, IICX1, IICX0, IICE): When the on-chip IIC option is 2 2 included, these bits control the operation of the I C bus interface. For details, see section 16, I C Bus Interface. Bit 3--Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained. Bit 3 FLSHE 0 1 Description Flash memory control registers deselected Flash memory control registers selected (Initial value) 2 Bit 2--Reserved: Do not write 1 to this bit. Bits 1 and 0--Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits control 8-bit timer operation. See section 12, 8-Bit Timers, for details. 578 21.6 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 21.6. For a diagram of the transitions to the various flash memory modes, see figure 21.3. Only advanced mode setting is possible for boot mode. In the case of user program mode, established in advanced mode or normal mode, depending on the setting of the MD0 pin. In normal mode, only programming of a 56-kbyte area of flash memory is possible. Table 21.6 Setting On-Board Programming Modes Mode Mode Name Boot mode User program mode CPU Operating Mode Advanced mode Advanced mode Normal mode Note: * Can be used as I/O ports after boot mode is initiated. MD1 0 1 MD0 0 0 1 P92 1* -- -- P91 1* -- -- P90 1* -- -- 579 21.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2138 or H8S/2134 Series MCU's pins have been set to boot mode, the boot program built into the MCU is started and the programming control program prepared in the host is serially transmitted to the MCU via the SCI. In the MCU, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 21.7, and the boot program mode execution procedure in figure 21.8. H8S/2138 or H8S/2134 Series chip Flash memory Host Write data reception Verify data transmission RxD1 SCI1 TxD1 On-chip RAM Figure 21.7 System Configuration in Boot Mode 580 Start Set pins to boot program mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate MCU measures low period of H'00 data transmitted by host MCU calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, MCU transfers part of boot program to RAM Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, MCU transmits one H'AA data byte to host Host transmits number of user program bytes (N), upper byte followed by lower byte MCU transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits user program sequentially in byte units MCU transmits received user program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Transmit one H'AA data byte to host, and execute programming control program transferred to on-chip RAM n+1n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 21.8 Boot Mode Execution Procedure 581 Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 21.9 RxD1 Input Signal when Using Automatic SCI Bit Rate Adjustment When boot mode is initiated, the H8S/2138 or H8S/2134 Series MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the MCU's system clock frequency, there will be a discrepancy between the bit rates of the host and the MCU. To ensure correct SCI operation, the host's transfer bit rate should be set to (2400, 4800, or 9600) bps. Table 21.7 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU's bit rate is possible. The boot program should be executed within this system clock range. Table 21.7 System Clock Frequencies for which Automatic Adjustment of H8S/2138 or H8S/2134 Series Bit Rate is Possible Host Bit Rate 9600 bps 4800 bps 2400 bps System Clock Frequency for which Automatic Adjustment of H8S/2138 or H8S/2134 Series Bit Rate is Possible 8 MHz to 20 MHz 4 MHz to 20 MHz 2 MHz to 18 MHz 582 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 128-byte area from H'(FF)FF00 to H'(FF)FF7F is reserved for use by the boot program, as shown in figure 21.10. The area to which the programming control program is transferred is H'(FF)E080 to H'(FF)EFFF (3968 bytes) in the 128-kbyte versions, or H'(FF)E880 to H'(FF)EFFF (1920 bytes) in the 64kbyte versions. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required. H'(FF)E080 Programming control program area (3,968 bytes) H'(FF)E880 Programming control program area (1,920 bytes) H'(FF)EFFF H'(FF)EFFF H'(FF)FF00 Boot program area* (128 bytes) (a) 128-kbyte versions H'(FF)FF00 H'(FF)FF7F H'(FF)FF7F Boot program area* (128 bytes) (b) 64-kbyte versions Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. Figure 21.10 RAM Areas in Boot Mode 583 Notes on Use of User Mode: * When the chip comes out of reset in boot mode, it measures the low period of the input at the SCI's RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the RxD1 input. * In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. * Interrupts cannot be used while the flash memory is being programmed or erased. * The RxD1 and TxD1 pins should be pulled up on the board. * Before branching to the programming control program (RAM area H'(FF)E080 (128-kbyte versions) or H'(FF)E880 (64-kbyte versions)), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P84DDR = 1, P84DR = 1). The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. * Boot mode can be entered by making the pin settings shown in table 21.6 and executing a reset-start. 1 When the chip detects the boot mode setting at reset release* , P92, P91, and P90 can be used as I/O ports. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting 1 the mode pins, and executing reset release* . Boot mode can also be cleared by a WDT overflow reset. The mode pin input levels must not be changed in boot mode. * If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins ($6, 5', :5) 2 will change according to the change in the microcomputer's operating mode* . Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. Ports with multiplexed address functions will output a low level as the address signal if mode pin setting is for mode 1 is entered during a reset. In other modes, the port pins go to the high-impedance state. The bus control output signals will output a high 584 level if mode pin setting is for mode 1 is entered during a reset. In other modes, the port pins go to the high-impedance state. 21.6.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board supply of programming data, and storing a program/erase control program in part of the program area as necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 2 or 3). In this mode, on-chip supporting modules other than flash memory operate as they normally would in mode 2 and 3. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. Figure 21.11 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the transfer program (and the program/ erase control program if necessary) beforehand MD1, MD0 = 10, 11 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area Execute program/erase control program (flash memory rewriting) Branch to flash memory application program Note: The watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Figure 21.11 User Program Mode Execution Procedure 585 21.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in FLMCR1, and the ESU and PSU bits in FLMCR2, is executed by a program in flash memory. 2. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 21.7.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 21.12 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a time. The wait times (x, y, z, , , , , ) after setting/clearing individual bits in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of writes (N) are shown in table 24.13 in section 24.6, Flash Memory Characteristics. Following the elapse of (x) s or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the reprogram data area written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z + + ) s as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory 586 programming time. Make a program setting so that the time for one programming operation is within the range of (z) s. 21.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least () s later). The watchdog timer is cleared after the elapse of () s or more, and the operating mode is switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 21.12) and transferred to the reprogram data area. After 32 bytes of data have been verified, exit programverify mode, wait for at least () s, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. 587 Start Set SWE bit in FLMCR1 Wait (x) s Store 32-byte program data in program data area and reprogram data area n=1 m=0 Write 32-byte data in RAM reprogram data area consecutively to flash memory Enable WDT Set PSU bit in FLMCR2 Wait (y) s Set P bit in FLMCR1 Wait (z) s Clear P bit in FLMCR1 Wait () s Clear PSU bit in FLMCR2 Wait () s Disable WDT Set PV bit in FLMCR1 Wait () s H'FF dummy write to verify address Wait () s Read verify data Increment address Program data = verify data? OK Reprogram data computation Transfer reprogram data to reprogram data area NG End of 32-byte data verification? OK Clear PV bit in FLMCR1 Wait () s m = 0? OK Clear SWE bit in FLMCR1 End of programming *5 *5 *5 *5 *5 *1 *5 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *4 nn+1 Start of programming *5 End of programming *5 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. If a bit for which programming has been completed in the 32-byte programming loop fails the following verify phase, additional programming is performed for that bit. 4. An area for storing program data (32 bytes) and reprogram data (32 bytes) must be provided in RAM. The contents of the latter are rewritten as programming progresses. 5. See section 24.6, Flash Memory Characteristics, for the values of x, y, z, , , , , , and N. Program Data 0 Verify Data 0 Reprogram Data 1 Comments Reprogramming is not performed if program data and verify data match Programming incomplete; reprogram -- Still in erased state; no action *2 0 1 m=1 1 1 0 1 0 1 1 NG *3 *4 RAM Program data storage area (32 bytes) Reprogram data storage area (32 bytes) n N? *5 NG NG OK Clear SWE bit in FLMCR1 Programming failure Figure 21.12 Program/Program-Verify Flowchart 588 21.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 21.13. The wait times (x, y, z, , , , , ) after setting/clearing individual bits in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of erases (N) are shown in table 24.13 in section 24.6, Flash Memory Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) s after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + + ) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 21.7.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the ESU bit in FLMCR2 is cleared at least () s later), the watchdog timer is cleared after the elapse of () s or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-verify sequence is not repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait for at least () s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. 589 Start *1 Set SWE bit in FLMCR1 Wait (x) s n=1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR2 Wait (y) s Set E bit in FLMCR1 Wait (z) ms Clear E bit in FLMCR1 Wait () s Clear ESU bit in FLMCR2 Wait () s Disable WDT Set EV bit in FLMCR1 Wait () s Set block start address to verify address *5 *5 *5 *3 *5 Start of erase *5 Halt erase *5 nn+1 H'FF dummy write to verify address Wait () s Increment address Read verify data Verify data = all 1? OK NG Last address of block? OK Clear EV bit in FLMCR1 Wait () s NG *4 *5 *5 *2 NG Clear EV bit in FLMCR1 Wait () s *5 *5 End of erasing of all erase blocks? OK n N? OK Clear SWE bit in FLMCR1 Erase failure NG Clear SWE bit in FLMCR1 End of erasing Notes: 1. 2. 3. 4. 5. Preprogramming (setting erase block data to all 0) is not necessary. Verify data is read in 16-bit (W) units. Set only one bit in EBR1or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. See section 24.6, Flash Memory Characteristics, for the values of x, y, z, , , , , , and N. Figure 21.13 Erase/Erase-Verify Flowchart (Single-Block Erase) 590 21.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 21.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 21.8.) Table 21.8 Hardware Protection Functions Item Reset/standby protection Description * In a reset (including a WDT overflow reset), software standby mode, subactive mode, subsleep mode, and watch mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/eraseprotected state is entered. In a reset via the 5(6 pin, the reset state is not entered unless the 5(6 pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the 5(6 pin low for the 5(6 pulse width specified in the AC Characteristics section. Program Yes Erase Yes * 591 21.8.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase mode. (See table 21.9.) Table 21.9 Software Protection Functions Item SWE bit protection Description * Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM or external memory.) Block specification protection * Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. -- Yes Program Yes Erase Yes * 21.8.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. 592 FLER bit setting conditions are as follows: * When flash memory is read during programming/erasing (including a vector read or instruction fetch) * Immediately after exception handling (excluding a reset) during programming/erasing * When a SLEEP instruction (transition to software standby, sleep, subactive, subsleep, or watch mode) is executed during programming/erasing * When the bus is released during programming/erasing Error protection is released only by a reset and in hardware standby mode. Figure 21.14 shows the flash memory state transition diagram. Program mode Erase mode RD VF PR ER FLER = 0 RES = 0 or STBY = 0 Reset or hardware standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence*2 Error occurrence*1 RES = 0 or STBY = 0 RES = 0 or STBY = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode Software standby, sleep, subsleep, and watch mode Error protection mode (software standby, sleep, subsleep, and watch ) RD VF PR ER FLER = 1 RD VF*4 PR ER FLER = 1 Software standby, sleep, subsleep, and watch mode release FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 initialization state*3 Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: Memory read not possible VF: Verify-read not possible PR: Programming not possible ER: Erasing not possible Notes: 1. When an error occurs other than due to a SLEEP instruction, or when a SLEEP instruction is executed for a transition to subactive mode 2. When an error occurs due to a SLEEP instruction (except subactive mode) 3. Except sleep mode 4. VF in subactive mode Figure 21.14 Flash Memory State Transitions 593 21.9 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot 1 mode* , to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector 2 would not be read correctly* , possibly resulting in MCU runaway. 3. If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All interrupt requests, including NMI input, must therefore be disabled inside and outside the MCU when programming or erasing flash memory. Interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 594 21.10 Flash Memory Writer Mode 21.10.1 Writer Mode Setting Programs and data can be written and erased in writer mode as well as in the on-board programming modes. In writer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Hitachi microcomputer device types with 128-kbyte or 64kbyte on-chip flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with these device types. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 21.10 shows writer mode pin settings. Table 21.10 Writer Mode Pin Settings Pin Names Mode pins: MD1, MD0 Setting/External Circuit Connection Low-level input to MD1, MD0 High-level input (Hardware standby mode not set) Power-on reset circuit Oscillation circuit Low-level input to P92, P67, high-level input to P97, P91, P90 67%< pin 5(6 pin XTAL and EXTAL pins Other setting pins: P97, P92, P91, P90, P67 595 21.10.2 Socket Adapters and Memory Map In writer mode, a socket adapter is mounted on the writer programmer to match the package concerned. Socket adapters are available for each writer manufacturer supporting Hitachi microcomputer device types with 128-kbyte or 64-kbyte on-chip flash memory. Figure 21.15 shows the memory map in writer mode. For pin names in writer mode, see section 1.3.2, Pin Functions in Each Operating Mode. H8S/2138 H8S/2134 MCU mode H'000000 Writer mode H'00000 MCU mode H'000000 H8S/2132 On-chip ROM area Writer mode H'00000 On-chip ROM area H'01FFFF H'1FFFF H'00FFFF Undefined value output H'0FFFF H'1FFFF Figure 21.15 Memory Map in Writer Mode 21.10.3 Writer Mode Operation Table 21.11 shows how the different operating modes are set when using writer mode, and table 21.12 lists the commands used in writer mode. Details of each mode are given below. * Memory Read Mode Memory read mode supports byte reads. * Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. * Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. * Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the FO6 signal. In status read mode, error information is output if an error occurs. 596 Table 21.11 Settings for Each Operating Mode in Writer Mode Pin Names Mode Read Output disable Command write Chip disable* 1 &( L L L H 2( L H H X :( H H L X FO0 to FO7 Data output Hi-z Data input Hi-z FA0 to FA17 Ain X Ain* X 2 Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. Table 21.12 Writer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address Data X X X X H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address Data RA WA X X Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 597 21.10.4 Memory Read Mode * After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. * Command writes can be performed in memory read mode, just as in the command wait state. * Once memory read mode has been entered, consecutive reads can be performed. * After power-on, memory read mode is entered. Table 21.13 AC Characteristics in Memory Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 30 30 Max Unit s ns ns ns ns ns ns ns Notes &( hold time &( setup time Data hold time Data setup time Write pulse width :( rise time :( fall time Command write FA17 to FA0 Memory read mode Address stable CE OE WE FO7 to FO0 twep tceh tnxtc tces tf tr Data tdh tds Data Note: Data is latched on the rising edge of WE. Figure 21.16 Memory Read Mode Timing Waveforms after Command Write 598 Table 21.14 AC Characteristics when Entering Another Mode from Memory Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 30 30 Max Unit s ns ns ns ns ns ns ns Notes &( hold time &( setup time Data hold time Data setup time Write pulse width :( rise time :( fall time Memory read mode FA17 to FA0 Address stable Other mode command write CE OE WE FO7 to FO0 tnxtc tces tf twep tceh tr H'XX tdh Data Note: Do not enable WE and OE at the same time. tds Figure 21.17 Timing Waveforms when Entering Another Mode from Memory Read Mode 599 Table 21.15 AC Characteristics in Memory Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Access time Symbol tacc tce toe tdf toh 5 Min Max 20 150 150 100 Unit s ns ns ns ns Notes &( output delay time 2( output delay time Output disable delay time Data output hold time FA17 to FA0 CE OE WE Address stable Address stable VIL tacc VIL VIH tacc FO7 to FO0 Data toh Data toh Figure 21.18 Timing Waveforms for / Enable State Read FA17 to FA0 Address stable Address stable tacc CE OE WE tacc FO7 to FO0 tce toe tce toe VIH tdf Data toh Data tdf toh Figure 21.19 Timing Waveforms for / Clocked Read 600 21.10.5 Auto-Program Mode AC Characteristics Table 21.16 AC Characteristics in Auto-Program Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tr tf 0 60 1 3000 30 30 Min 20 0 0 50 50 70 1 150 Max Unit s ns ns ns ns ns ms ns ns ns ms ns ns Notes &( hold time &( setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time :( rise time :( fall time FA17 to FA0 tceh CE tnxtc OE twep WE tces tf tds tdh FO6 FO7 to FO0 H'40 Address stable tas tah tnxtc Data transfer 1 byte to 128 bytes twsts tspa twrite (1 to 3000 ms) Programming operation end identification signal FO7 tr Programming normal end identification signal Programming wait Data Data FO0 to 5 = 0 Figure 21.20 Auto-Program Mode Timing Waveforms 601 Notes on Use of Auto-Program Mode * In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. * A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. * The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. * Memory address transfer is performed in the second cycle (figure 21.20). Do not perform transfer after the second cycle. * Do not perform a command write during a programming operation. * Perform one auto-programming operation for a 128-byte block for each address. Characteristics are not guaranteed for two or more programming operations. * Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-program operation end identification pin). * The status polling FO6 and FO7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling &( and 2(. 602 21.10.6 Auto-Erase Mode AC Characteristics Table 21.17 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle Symbol tnxtc tceh tces tdh tds twep tests tspa terase tr tf 100 Min 20 0 0 50 50 70 1 150 40000 30 30 Max Unit s ns ns ns ns ns ms ns ms ns ns Notes &( hold time &( setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time :( rise time :( fall time FA17 to FA0 tces CE tspa OE WE FO7 FO6 CLin FO7 to FO0 H'20 DLin H'20 FO0 to FO5 = 0 twep tf tds tdh tr tnxtc tests terase (100 to 40000 ms) Erase end identification signal Erase normal end confirmation signal tceh tnxtc Figure 21.21 Auto-Erase Mode Timing Waveforms 603 Notes on Use of Erase-Program Mode * Auto-erase mode supports only entire memory erasing. * Do not perform a command write during auto-erasing. * Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin). * The status polling FO6 and FO7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling &( and 2(. 21.10.7 Status Read Mode * Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. * The return code is retained until a command write for other than status read mode is performed. Table 21.18 AC Characteristics in Status Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 150 100 150 30 30 Max Unit s ns ns ns ns ns ns ns ns ns ns Notes &( hold time &( setup time Data hold time Data setup time Write pulse width 2( output delay time Disable delay time &( output delay time :( rise time :( fall time 604 FA17 to FA0 CE tce OE twep WE tces tf tds tdh FO7 to FO0 H'71 tceh tr tnxtc tces tf tds tdh H'71 Data twep tceh tr tnxtc toe tnxtc tdf Note: FO2 and FO3 are undefined. Figure 21.22 Status Read Mode Timing Waveforms Table 21.19 Status Read Mode Return Commands Pin Name Attribute FO7 FO6 FO5 FO4 FO3 -- FO2 -- FO1 FO0 Normal Command end error identification 0 Command error: 1 Programming Erase error error Programming Effective or erase address error count exceeded 0 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 0 0 -- 0 -- Programming Erase error: 1 error: 1 Otherwise: 0 Otherwise: 0 Otherwise: 0 Count Effective exceeded: 1 address error: 1 Otherwise: 0 Otherwise: 0 Note: FO2 and FO3 are undefined. 605 21.10.8 Status Polling * The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode. * The FO6 status polling flag indicates a normal or abnormal end in auto-program or autoerase mode. Table 21.20 Status Polling Output Truth Table Pin Names FO7 FO6 FO0 to FO5 Internal Operation in Progress 0 0 0 Abnormal End 1 0 0 -- 0 1 0 Normal End 1 1 0 21.10.9 Writer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the writer mode setup period. After the writer mode setup time, a transition is made to memory read mode. Table 21.21 Command Wait State Transition Time Specifications Item Standby release (oscillation stabilization time) PROM mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min 20 10 0 Max -- -- -- Unit ms ms ms Notes VCC RES tosc1 tbmv Memory read Auto-program mode mode Auto-erase mode Command wait state tdwn Command Don't care wait state Normal/ abnormal end identification Command reception Figure 21.23 Oscillation Stabilization Time, Writer Mode Setup Time, and Power Supply Fall Sequence 606 21.10.10 Notes On Memory Programming * When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. * When performing programming using writer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. 21.11 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode and writer mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports Hitachi microcomputer device types with 128-kbyte or 64-kbyte on-chip flash memory. Do not select the HN28F101 setting for the PROM programmer, and only use the specified socket adapter. Incorrect use will result in damaging the device. Powering on and off: When applying or disconnecting VCC, fix the 5(6 pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE bit during program execution in flash memory: Clear the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing). Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled to give priority to program/erase operations. 607 Do not perform additional programming. Erase the memory before reprogramming. In onboard programming, perform only one programming operation on a 32-byte programming unit block. In writer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. 608 Section 22 Clock Pulse Generator 22.1 Overview The H8S/2138 Series and H8S/2134 Series have a built-in clock pulse generator (CPG) that generates the system clock (o), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock input circuit, and waveform shaping circuit. 22.1.1 Block Diagram Figure 22.1 shows a block diagram of the clock pulse generator. EXTAL Oscillator XTAL Duty adjustment circuit Medium-speed clock divider Clock selection circuit o/2 to o/32 Bus master clock selection circuit oSUB o EXCL Subclock input circuit Waveform shaping circuit System clock To o pin Internal clock To supporting modules Bus master clock To CPU, DTC WDT1 count clock Figure 22.1 Block Diagram of Clock Pulse Generator 609 22.1.2 Register Configuration The clock pulse generator is controlled by the standby control register (SBYCR) and low-power control register (LPWRCR). Table 22.1 shows the register configuration. Table 22.1 CPG Registers Name Standby control register Low-power control register Abbreviation SBYCR LPWRCR R/W R/W R/W Initial Value H'00 H'00 Address* H'FF84 H'FF85 Note: * Lower 16 bits of the address. 22.2 22.2.1 Bit Register Descriptions Standby Control Register (SBYCR) 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 -- 0 -- 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value Read/Write SBYCR is an 8-bit readable/writable register that performs power-down mode control. Only bits 0 to 2 are described here. For a description of the other bits, see section 23.2.1, Standby Control Register (SBYCR). SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. 610 Bits 2 to 0--System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock for high-speed mode and medium-speed mode. When operating the device after a transition to subactive mode or watch mode bits SCK2 to SCK0 should all be cleared to 0. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master is in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- (Initial value) 22.2.2 Bit Low-Power Control Register (LPWRCR) 7 DTON 0 R/W 6 LSON 0 R/W 5 NESEL 0 R/W 4 EXCLE 0 R/W 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Initial value Read/Write LPWRCR is an 8-bit readable/writable register that performs power-down mode control. Only bit 4 is described here. For a description of the other bits, see section 23.2.2, Low-Power Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 4--Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin. Bit 4 EXCLE 0 1 Description Subclock input from EXCL pin is disabled Subclock input from EXCL pin is enabled (Initial value) 611 22.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 22.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 22.2. Select the damping resistance Rd according to table 22.2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22pF Figure 22.2 Connection of Crystal Resonator (Example) Table 22.2 Damping Resistance Value Frequency (MHz) Rd () 2 1k 4 500 8 200 10 0 12 0 16 0 20 0 Crystal resonator: Figure 22.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 22.3 and the same frequency as the system clock (o). CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 22.3 Crystal Resonator Equivalent Circuit 612 Table 22.3 Crystal Resonator Parameters Frequency (MHz) RS max () C0 max (pF) 2 500 7 4 120 7 8 80 7 10 70 7 12 60 7 16 50 7 20 40 7 Note on Board Design: When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 22.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid CL2 Signal A Signal B H8S/2138 Series or H8S/2134 Series chip XTAL EXTAL CL1 Figure 22.4 Example of Incorrect Board Design 613 22.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 22.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 22.5 External Clock Input (Examples) 614 External Clock: The external clock signal should have the same frequency as the system clock (o). Table 22.4 and figure 22.6 show the input conditions for the external clock. Table 22.4 External Clock Input Conditions VCC = 2.7 to 5.5 V Item Symbol Min 40 Max -- External clock tEXL input low pulse width External clock tEXH input high pulse width External clock tEXr rise time External clock tEXf fall time Clock low pulse width tCL VCC = 5.0 V 10% Min 20 Max -- Unit ns Test Conditions Figure 22.6 40 -- 20 -- ns -- -- 0.4 80 10 10 0.6 -- 0.6 -- -- -- 0.4 80 0.4 80 5 5 0.6 -- 0.6 -- ns ns tcyc ns tcyc ns o 5 MHz Figure 24.4 o < 5 MHz o 5 MHz o < 5 MHz Clock high pulse width tCH 0.4 80 tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 22.6 External Clock Input Timing 615 Table 22.5 shows the external clock output settling delay time, and figure 22.7 shows the external clock output settling delay timing. The oscillator and duty adjustment circuit have a function for adjusting the waveform of the external clock input at the EXTAL pin. When the prescribed clock signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the external clock output settling delay time (tDEXT). As the clock signal output is not fixed during the tDEXT period, the reset signal should be driven low to maintain the reset state. Table 22.5 External Clock Output Settling Delay Time Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V Item External clock output settling delay time Symbol tDEXT* Min 500 Max -- Unit s Notes Figure 22.7 Note: * tDEXT includes 5(6 pulse width (tRESW). VCC 2.7V STBY VIH EXTAL o (internal or external) RES tDEXT* Note: * tDEXT includes RES pulse width (tRESW). Figure 22.7 External Clock Output Settling Delay Timing 616 22.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (o). 22.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate o/2, o/4, o/8, o/16, and o/32 clocks. 22.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (o) or one of the medium-speed clocks (o/2, o/4, o/8, o/16, or o/32) to be supplied to the bus master, according to the settings of bits SCK2 to SCK0 in SBYCR. 617 22.7 Subclock Input Circuit The subclock input circuit controls the subclock input from the EXCL pin. Inputting the Subclock: When a subclock is used, a 32.768 kHz external clock should be input from the EXCL pin. In this case, clear bit P96DDR to 0 in P9DDR and set bit EXCLE to 1 in LPWRCR. The subclock input conditions are shown in table 22.6 and figure 22.8. Table 22.6 Subclock Input Conditions VCC = 2.7 to 5.5 V Item Symbol Min -- -- -- -- Typ 15.26 15.26 -- -- Max -- -- 10 10 Unit s s ns ns Test Conditions Figure 22.8 Subclock input low pulse tEXCLL width Subclock input high pulse tEXCLH width Subclock input rise time Subclock input fall time tEXCLr tEXCLf tEXCLH tEXCLL EXCL VCC x 0.5 tEXCLr tEXCLf Figure 22.8 Subclock Input Timing When Subclock is not Needed: Do not enable subclock input when the subclock is not needed 22.8 Subclock Waveform Shaping Circuit To eliminate noise in the subclock input from the EXCL pin, this circuit samples the clock using a clock obtained by dividing the o clock. The sampling frequency is set with the NESEL bit in LPWRCR. For details, see section 23.2.2, Low-Power Control Register (LPWRCR). The clock is not sampled in subactive mode, subsleep mode, or watch mode. 618 Section 23 Power-Down State 23.1 Overview In addition to the normal program execution state, the H8S/2138 Series and H8S/2134 Series have a power-down state in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2138 Series and H8S/2134 Series operating modes are as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. High-speed mode Medium-speed mode Subactive mode Sleep mode Subsleep mode Watch mode Module stop mode Software standby mode Hardware standby mode Of these, 2 to 9 are power-down modes. Sleep mode and subsleep mode are CPU modes, medium-speed mode is a CPU and bus master mode, subactive mode is a CPU, bus master, and on-chip supporting module mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). Certain combinations of these modes can be set. After a reset, the MCU is in high-speed mode and module stop mode (excluding the DTC). Table 23.1 shows the internal chip states in each mode, and table 23.2 shows the conditions for transition to the various modes. Figure 23.1 shows a mode transition diagram. 619 Table 23.1 H8S/2138 Series and H8S/2134 Series Internal States in Each Mode Function System clock oscillator Subclock input CPU operation Instructions Registers External interrupts NMI IRQ0 IRQ1 IRQ2 On-chip DTC supporting module operation WDT1 WDT0 TMR0, 1 FRT TMRX, Y Timer connection IIC0 IIC1 SCI0 SCI1 SCI2 PWM PWMX HIF D/A A/D RAM I/O Functioning Functioning Functioning Functioning Function- Functioning (DTC) ing Functioning Functioning Retained Retained Functioning Functioning Retained Retained Retained Retained Retained High impedance Function- Halted ing/halted (reset) (reset) Halted (reset) Halted (reset) Halted (reset) Functioning/halted (retained) Functioning Functioning Mediumspeed Functioning Functioning Functioning Function- Halted Halted Halted Halted Halted ing/halted (retained) (retained) (retained) (retained) (reset) (retained) Functioning Subclock operation Halted (retained) Subclock operation Subclock operation Halted Halted (retained) (reset) Functioning Functioning HighSpeed Functioning Functioning Functioning MediumSpeed Functioning Functioning Mediumspeed Sleep Functioning Functioning Halted Retained Functioning Functioning Module Stop Functioning Functioning Functioning Subactive Watch Halted Functioning Halted Retained Functioning Functioning Halted Functioning Subclock operation Software Subsleep Standby Halted Functioning Halted Retained Functioning Halted Halted Halted Retained Functioning Hardware Standby Halted Halted Halted Undefined Halted Halted Halted (retained) (retained) Note: "Halted (retained)" means that internal register values are retained. The internal state is operation suspended. "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 620 Program-halted state STBY pin = low Reset state STBY pin = high RES pin = low RES pin = high Program execution state SLEEP instruction Any interrupt*3 SLEEP instruction External interrupt*4 SLEEP instruction SSBY = 1 PSS = 1, DTON = 0 Watch mode (subclock) SSBY = 1 PSS = 0, LSON = 0 Software standby mode SSBY = 0, LSON = 0 Sleep mode (main clock) Hardware standby mode High-speed mode (main clock) SCK2 to SCK0 = 0 SCK2 to SCK0 0 Medium-speed mode (main clock) SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 Clock switching exception handling after oscillation setting time (STS2 to STS0) Interrupt*1, SLEEP instruction SSBY = 1, PSS = 1, LSON bit = 0 DTON = 1, LSON = 1 Clock switching SLEEP exception handling instruction Interrupt*1, LSON bit = 1 SLEEP instruction Interrupt*2 SSBY = 0 PSS = 1, LSON = 1 Subsleep mode (subclock) Subactive mode (subclock) : Transition after exception handling : Power-down mode Notes: * When a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. * From any state, a transition to hardware standby mode occurs when STBY goes low. * When a transition is made to watch mode or subactive mode, high-speed mode must be set. *1 NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts *2 NMI, IRQ0 to RQ7, and WDT0 interrupts, WDT1 interrupt, TMR0 interrupt, TMR1 interrupt *3 All interrupts *4 NMI, IRQ0 to IRQ2, IRQ6, IRQ7 Figure 23.1 Mode Transitions 621 Table 23.2 Power-Down Mode Transition Conditions Control Bit States at Time of Transition State before Transition SSBY PSS * * 0 0 1 1 1 1 0 1 1 0 1 1 1 1 LSON 0 1 0 1 0 1 0 1 * 0 1 * 0 1 0 1 DTON * * * * 0 0 1 1 * * * * 0 0 1 1 State after Transition State after Return by SLEEP Instruction by Interrupt Sleep -- Software standby -- Watch Watch -- Subactive -- -- Subsleep -- Watch Watch High-speed -- High-speed/ medium-speed -- High-speed/ medium-speed -- High-speed Subactive -- -- -- -- Subactive -- High-speed Subactive -- -- High-speed/ 0 medium-speed 0 1 1 1 1 1 1 Subactive 0 0 0 1 1 1 1 1 *: Don't care --: Do not set. 622 23.1.1 Register Configuration The power-down state is controlled by the SBYCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 23.3 summarizes these registers. Table 23.3 Power-Down State Registers Name Standby control register Low-power control register Timer control/status register (WDT1) Module stop control register Abbreviation SBYCR LPWRCR TCSR MSTPCRH MSTPCRL Note: * Lower 16 bits of the address. R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'3F H'FF Address* H'FF84 H'FF85 H'FFEA H'FF86 H'FF87 23.2 23.2.1 Bit Register Descriptions Standby Control Register (SBYCR) 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 -- 0 -- 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value Read/Write SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. 623 Bit 7--Software Standby (SSBY): Determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a SLEEP instruction. The SSBY setting is not changed by a mode transition due to an interrupt, etc. Bit 7 SSBY 0 Description Transition to sleep mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to subsleep mode after execution of SLEEP instruction in subactive mode 1 Transition to software standby mode, subactive mode, or watch mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to watch mode or high-speed mode after execution of SLEEP instruction in subactive mode (Initial value) Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when software standby mode, watch mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction. With crystal oscillation, refer to table 23.4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation settling time). With an external clock, any selection can be made. Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states* (Initial value) Note: Do not used this setting in the on-chip flash memory version. Bit 3--Reserved: This bit cannot be modified and is always read as 0. 624 Bits 2 to 0--System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master in high-speed mode and medium-speed mode. When operating the device after a transition to subactive mode or watch mode, bits SCK2 to SCK0 should all be cleared to 0. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master is in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- (Initial value) 23.2.2 Bit Low-Power Control Register (LPWRCR) 7 DTON 0 R/W 6 LSON 0 R/W 5 NESEL 0 R/W 4 EXCLE 0 R/W 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Initial value Read/Write LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. 625 Bit 7--Direct-Transfer On Flag (DTON): Specifies whether a direct transition is made between high-speed mode, medium-speed mode, and subactive mode when making a powerdown transition by executing a SLEEP instruction. The operating mode to which the transition is made after SLEEP instruction execution is determined by a combination of other control bits. Bit 7 DTON 0 Description When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (Initial value) 1 When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or software standby mode When a SLEEP instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. Bit 6--Low-Speed On Flag (LSON): Determines the operating mode in combination with other control bits when making a power-down transition by executing a SLEEP instruction. Also controls whether a transition is made to high-speed mode or to subactive mode when watch mode is cleared. Bit 6 LSON 0 Description When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode After watch mode is cleared, a transition is made to high-speed mode 1 (Initial value) When a SLEEP instruction is executed in high-speed mode a transition is made to watch mode or subactive mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode After watch mode is cleared, a transition is made to subactive mode Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. 626 Bit 5--Noise Elimination Sampling Frequency Select (NESEL): Selects the frequency at which the subclock (oSUB) input from the EXCL pin is sampled with the clock (o) generated by the system clock oscillator. When o = 5 MHz or higher, clear this bit to 0. Bit 5 NESEL 0 1 Description Sampling at o divided by 32 Sampling at o divided by 4 (Initial value) Bit 4--Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin. Bit 4 EXCLE 0 1 Description Subclock input from EXCL pin is disabled Subclock input from EXCL pin is enabled (Initial value) Bits 3 to 0--Reserved: These bits cannot be modified and are always read as 0. 23.2.3 TCSR1 Bit Initial value Read/Write 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Timer Control/Status Register (TCSR) Note: * Only 0 can be written in bit 7, to clear the flag. TCSR1 is an 8-bit readable/writable register that performs selection of the WDT1 TCNT input clock, mode, etc. Only bit 4 is described here. For details of the other bits, see section 14.2.2, Timer Control/Status Register (TCSR). TCSR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. 627 Bit 4--Prescaler Select (PSS): Selects the WDT1 TCNT input clock. This bit also controls the operation in a power-down mode transition. The operating mode to which a transition is made after execution of a SLEEP instruction is determined in combination with other control bits. For details, see the description of Clock Select 2 to 0 in section 14.2.2, Timer Control/Status Register (TCSR). Bit 4 PSS 0 Description TCNT counts o-based prescaler (PSM) divided clock pulses When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode or software standby mode (Initial value) 1 TCNT counts oSUB-based prescaler (PSM) divided clock pulses When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, watch mode*, or subactive mode* When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode, watch mode, or high-speed mode Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. 23.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 Bit Initial value Read/Write 7 6 5 4 3 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. 628 MSTRCRH and MSTPCRL Bits 7 to 0--Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 23.3 for the method of selecting on-chip supporting modules. MSTPCRH, MSTPCRL Bits 7 to 0 MSTP15 to MSTP0 0 1 Description Module stop mode is cleared Module stop mode is set (Initial value of MSTP15, MSTP14) (Initial value of MSTP13 to MSTP0) 23.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the operating clock (o/2, o/4, o/8, o/16, or o/32) specified by the SCK2 to SCK0 bits. The bus master other than the CPU (the DTC) also operates in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (o). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if o/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON bit in LPWRCR and the PSS bit in TCSR (WDT1) are both cleared to 0, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the 5(6 pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. When the 67%< pin is driven low, a transition is made to hardware standby mode. Figure 23.2 shows the timing for transition to and clearance of medium-speed mode. 629 Medium-speed mode o, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 23.2 Medium-Speed Mode Transition and Clearance Timing 23.4 23.4.1 Sleep Mode Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other supporting modules do not stop. 23.4.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt, or with the 5(6 pin or 67%< pin. Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled, or if interrupts other than NMI have been masked by the CPU. Clearing with the 5(6 Pin: When the 5(6 pin is driven low, the reset state is entered. When the 5(6 pin is driven high after the prescribed reset input period, the CPU begins reset exception handling. Clearing with the 67%< Pin: When the 67%< pin is driven low, a transition is made to hardware standby mode. 630 23.5 23.5.1 Module Stop Mode Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 23.4 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, A/D converter, 8-bit PWM module, and 14-bit PWM module, are retained. After reset release, all modules other than the DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Table 23.4 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRH Bit MSTP15 MSTP14* MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4* MSTP3* MSTP2* MSTP1* MSTP0* Module -- Data transfer controller (DTC) 16-bit free-running timer (FRT) 8-bit timers (TMR0, TMR1) 8-bit PWM timer (PWM), 14-bit PWM timer (PWMX) D/A converter A/D converter 8-bit timers (TMRX, TMRY), timer connection Serial communication interface 0 (SCI0) Serial communication interface 1 (SCI1) Serial communication interface 2 (SCI2) I C bus interface (IIC) channel 0 (option) I C bus interface (IIC) channel 1 (option) Host interface (HIF) -- -- 2 2 Note: Bits 1 and 0 can be read or written to, but do not affect operation. * Must be set to 1 in the H8S/2134 Series. 631 23.5.2 Usage Note If there is conflict between DTC module stop mode setting and a DTC bus request, the bus request has priority and the MSTP bit will not be set to 1. Write 1 to the MSTP bit again after the DTC bus cycle. When using an H8S/2134 Series MCU, the MSTP bits for nonexistent modules must not be set to 1. 23.6 23.6.1 Software Standby Mode Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is cleared to 0, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip supporting modules other than the SCI, PWM, and PWMX, and of the I/O ports, are retained. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 23.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pin ,54, ,54, ,54, ,54, or ,54), or by means of the 5(6 pin or 67%< pin. Clearing with an Interrupt: When an NMI, IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. Software standby mode cannot be cleared with an IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt if the corresponding enable bit has been cleared to 0 or has been masked by the CPU. Clearing with the 5(6 Pin: When the 5(6 pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the 5(6 pin must be held low until clock oscillation stabilizes. When the 5(6 pin goes high, the CPU begins reset exception handling. Clearing with the 67%< Pin: When the 67%< pin is driven low, a transition is made to hardware standby mode. 632 23.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation settling time). Table 23.5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 23.5 Oscillation Settling Time Settings 20 STS2 STS1 STS0 Standby Time MHz 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 0.41 0.82 1.6 3.3 16 MHz 0.51 1.0 2.0 4.1 8.2 12 MHz 0.65 1.3 2.7 5.5 10.9 21.8 -- 1.3 10 MHz 0.8 1.6 3.3 6.6 8 MHz 1.0 2.0 4.1 8.2 6 MHz 1.3 2.7 5.5 4 MHz 2.0 4.1 8.2 2 MHz Unit 4.1 8.2 16.4 32.8 65.5 131.2 -- 8.0 *: Don't care s ms 10.9 16.4 21.8 43.6 -- 1.7 32.8 65.6 -- 4.0 131072 states 6.6 262144 states Reserved 16 states* 13.1 16.4 26.2 -- 1.6 32.8 -- 2.0 13.1 16.4 -- 0.8 -- 1.0 : Recommended time setting Note: Do not used this setting in the on-chip flash memory version. Using an External Clock: Any value can be set. Normally, use of the minimum time is recommended. 633 23.6.4 Software Standby Mode Application Example Figure 23.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator o NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down state) Oscillation settling time tOSC2 NMI exception handling SLEEP instruction Figure 23.3 Software Standby Mode Application Example 634 23.6.5 Usage Note In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current dissipation increases while waiting for oscillation to settle. 23.7 23.7.1 Hardware Standby Mode Hardware Standby Mode When the 67%< pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the 67%< pin low. Do not change the state of the mode pins (MD1 and MD0) while the chip is in hardware standby mode. Hardware standby mode is cleared by means of the 67%< pin and the 5(6 pin. When the 67%< pin is driven high while the 5(6 pin is low, the reset state is set and clock oscillation is started. Ensure that the 5(6 pin is held low until the clock oscillation settles (at least 8 ms--the oscillation settling time--when using a crystal oscillator). When the 5(6 pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 635 23.7.2 Hardware Standby Mode Timing Figure 23.4 shows an example of hardware standby mode timing. When the 67%< pin is driven low after the 5(6 pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the 67%< pin high, waiting for the oscillation settling time, then changing the 5(6 pin from low to high. Oscillator RES STBY Oscillation settling time Reset exception handling Figure 23.4 Hardware Standby Mode Timing 636 23.8 23.8.1 Watch Mode Watch Mode If a SLEEP instruction is executed in high-speed mode or subactive mode when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is set to 1, the CPU makes a transition to watch mode. In this mode, the CPU and all on-chip supporting modules except WDT1 stop. As long as the prescribed voltage is supplied, the contents of some of the CPU's internal registers and on-chip RAM are retained, and I/O ports retain their states prior to the transition. 23.8.2 Clearing Watch Mode Watch mode is cleared by an interrupt (WOVI1 interrupt, NMI pin, or pin ,54, ,54, ,54, ,54, or ,54), or by means of the 5(6 pin or 67%< pin. Clearing with an Interrupt: When an interrupt request signal is input, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode if the LSON bit in LPWRCR is cleared to 0, or to subactive mode if the LSON bit is set to 1. When making a transition to high-speed mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire chip, and interrupt exception handling is started. Watch mode cannot be cleared with an IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the CPU. See section 23.6.3, Setting Oscillation Settling Time after Clearing Software Standby Mode, for the oscillation settling time setting when making a transition from watch mode to high-speed mode. Clearing with the 5(6 Pin: See "Clearing with the 5(6 Pin" in section 23.6.2, Clearing Software Standby Mode. Clearing with the 67%< Pin: When the 67%< pin is driven low, a transition is made to hardware standby mode. 637 23.9 23.9.1 Subsleep Mode Subsleep Mode If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, the CPU makes a transition to subsleep mode. In this mode, the CPU and all on-chip supporting modules except TMR0, TMR1, WDT0, and WDT1 stop. As long as the prescribed voltage is supplied, the contents of some of the CPU's internal registers and on-chip RAM are retained, and I/O ports retain their states prior to the transition. 23.9.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (on-chip supporting module interrupt, NMI pin, or pin ,54 to ,54), or by means of the 5(6 pin or 67%< pin. Clearing with an Interrupt: When an interrupt request signal is input, subsleep mode is cleared and interrupt exception handling is started. Subsleep mode cannot be cleared with an IRQ0 to IRQ7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the CPU. Clearing with the 5(6 Pin: See "Clearing with the 5(6 Pin" in section 23.6.2, Clearing Software Standby Mode. Clearing with the 67%< Pin: When the 67%< pin is driven low, a transition is made to hardware standby mode 638 23.10 Subactive Mode 23.10.1 Subactive Mode If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the PSS bit in TCSR (WDT1) are all set to 1, the CPU makes a transition to subactive mode. When an interrupt is generated in watch mode, if the LSON bit in LPWRCR is set to 1, a transition is made to subactive mode. When an interrupt is generated in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU performs sequential program execution at low speed on the subclock. In this mode, all on-chip supporting modules except TMR0, TMR1, WDT0, and WDT1 stop. When operating the device in subactive mode, bits SCK2 to SCK0 in SBYCR must all be cleared to 0. 23.10.2 Clearing Subactive Mode Subsleep mode is cleared by a SLEEP instruction, or by means of the 5(6 pin or 67%< pin. Clearing with a SLEEP Instruction: When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, a transition is made to subsleep mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit is set to 1 and the LSON bit is cleared to 0 in LPWRCR, and the PSS bit in TCSR (WDT1) is set to 1, a transition is made directly to high-speed mode. Fort details of direct transition, see section 23.11, Direct Transition. Clearing with the 5(6 Pin: See "Clearing with the 5(6 Pin" in section 23.6.2, Clearing Software Standby Mode. Clearing with the 67%< Pin: When the 67%< pin is driven low, a transition is made to hardware standby mode 639 23.11 Direct Transition 23.11.1 Overview of Direct Transition There are three operating modes in which the CPU executes programs: high-speed mode, medium-speed mode, and subactive mode. A transition between high-speed mode and subactive mode without halting the program is called a direct transition. A direct transition can be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction. After the transition, direct transition interrupt exception handling is started. Direct Transition from High-Speed Mode to Subactive Mode: If a SLEEP instruction is executed in high-speed mode while the SSBY bit in SBYCR, the LSON bit and DTON bit in LPWRCR, and the PSS bit in TSCR (WDT1) are all set to 1, a transition is made to subactive mode. Direct Transition from Subactive Mode to High-Speed Mode: If a SLEEP instruction is executed in subactive mode while the SSBY bit in SBYCR is set to 1, the LSON bit is cleared to 0 and the DTON bit is set to 1 in LPWRCR, and the PSS bit in TSCR (WDT1) is set to 1, after the elapse of the time set in bits STS2 to STS0 in SBYCR, a transition is made to directly to high-speed mode. 640 Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Power supply voltage Symbol VCC Value -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 Lower voltage of -0.3 to VCC +0.3 and AVCC +0.3 -0.3 to AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75* Wide-range specifications: -40 to +85* Operating temperature (flash memory programming/erasing) Topr Regular specifications: 0 to +75 Wide-range specifications: 0 to +85 Storage temperature Tstg -55 to +125 - Preliminary - Unit V V V V V V V C C C C C Input voltage (except ports 6 and Vin 7) Input voltage (CIN input not selected for port 6) Vin Input voltage (CIN input selected Vin for port 6) Input voltage (port 7) Analog power supply voltage Analog input voltage Operating temperature Vin AVCC VAN Topr Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. 641 24.2 DC Characteristics Table 24.2 lists the DC characteristics. Table 24.3 lists the permissible output currents. Table 24.2 DC Characteristics (1) - Preliminary - 1 1 Conditions:VCC = 5.0 V 10%, AVCC* = 5.0 V 10%, VSS = AVSS* = 0 V, Ta = 9 9 -20 to +75C* (regular specifications), Ta = -40 to +85C* (wide-range specifications) Item Schmitt P67 to P60* * , (1) 3 trigger input ,54 to ,54* , ,54 to ,54 voltage 2, 6 Symbol VT VT VT VT - Min 1.0 -- Typ -- -- -- -- -- -- -- -- Max -- Unit V Test Conditions + VCC x 0.7 V -- -- V V H8S/2138 Series only VT - VT Schmitt P67 to P60 trigger input (KWUL = 00) voltage (in level 6 switching)* P67 to P60 (KWUL = 01) - + - 0.4 1.0 -- + VCC x 0.7 V -- -- V V VT - VT VT VT VT VT VT VT (2) - + + - 0.4 VCC x 0.3 -- VCC x 0.7 V -- -- V V VT - VT P67 to P60 (KWUL = 10) - + + - VCC x 0.05 -- VCC x 0.4 -- -- -- VCC x 0.8 V -- -- V V VT - VT P67 to P60 (KWUL = 11) - + + - VCC x 0.03 -- VCC x 0.45 -- -- -- -- -- -- -- -- VCC x 0.9 V -- VCC +0.3 VCC +0.3 AVCC +0.3 V V V V VT - VT Input high voltage + - 0.05 VCC - 0.7 VCC x 0.7 2.0 2.0 5(6, 67%<, NMI, MD1, MD0 EXTAL Port 7 Input pins except (1) and (2) above VIH VCC +0.3 V 642 Table 24.2 DC Characteristics (1) (cont) - Preliminary - 1 1 Conditions:VCC = 5.0 V 10%, AVCC* = 5.0 V 10%, VSS = AVSS* = 0 V, Ta = 9 9 -20 to +75C* (regular specifications), Ta = -40 to +85C* (wide-range specifications) Item Input low voltage Symbol Min -0.3 (3) VIL -0.3 Typ -- -- Max 0.5 0.8 Unit V V Test Conditions 5(6, 67%<, MD1, MD0 NMI, EXTAL, input pins except (1) and (3) above Output high All output pins voltage (except P97, and 4 5 P52* )* P97, P52* Output low voltage Input leakage current 4 5 VOH VCC -0.5 -- -- V IOH = -200 A 3.5 2.5 VOL Iin -- -- -- -- -- ITSI -- -- -- -- -- -- -- -- -- -- -- 0.4 1.0 10.0 1.0 1.0 1.0 V V V V A A A A IOH = -1 mA IOH = -1 mA IOL = 1.6 mA IOL = 10 mA Vin = 0.5 to VCC - 0.5 V All output pins* Ports 1 to 3 5(6 67%<, NMI, MD1, MD0 Port 7 Three-state leakage current (off state) Input pullup MOS current Ports 1 to 6 Ports 8, 9 Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V Ports 1 to 3 Port 6 Port 6 (P6PUE = 0) Port 6 (P6PUE = 1) -IP 50 60 60 15 -- -- -- -- -- -- -- -- -- -- -- -- 300 500 500 150 80 50 20 15 A A A A pF pF pF pF Vin = 0 V Vin = 0 V H8S/2138 Series only Vin = 0 V f = 1 MHz Ta = 25C Input 5(6 capacitance NMI P52, P97, P42, P86 Input pins except (4) above (4) Cin 643 Table 24.2 DC Characteristics (1) (cont) - Preliminary - 1 1 Conditions:VCC = 5.0 V 10%, AVCC* = 5.0 V 10%, VSS = AVSS* = 0 V, Ta = 9 9 -20 to +75C* (regular specifications), Ta = -40 to +85C* (wide-range specifications) Item Current Normal operation 7 dissipation* Symbol ICC Min -- Typ 75 85 Sleep mode -- 60 70 Standby mode* 8 Max 100 120 85 100 5.0 20.0 7.0 5.0 5.5 5.5 -- Unit mA mA mA mA A A mA A V V V Test Conditions f = 20 MHz, H8S/2134 Series f = 20 MHz, H8S/2138 Series f = 20 MHz, H8S/2134 Series f = 20 MHz, H8S/2138 Series Ta 50C 50C < Ta -- -- 0.01 -- 3.2 0.01 -- -- -- Analog power supply current During A/D, D/A conversion Idle 1 AlCC -- -- AVCC= 2.0 V to 5.5 V Operating Idle/not used Analog power supply voltage* AVCC VRAM 4.5 2.0 RAM standby voltage Notes: 2.0 1. Do not leave the AVCC, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC by connection to the power supply (VCC), or some other method. 2. P67 to P60 include supporting module inputs multiplexed on those pins. 3. ,54 includes the $'75* signal multiplexed on that pin. 4. In the H8S/2138 Series, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0 and SDA0 (ICE = 1). P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS. 5. In the H8S/2138 Series, When ICE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 8. The values are for VRAM VCC < 4.5V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 9. For flash memory program/erase operations, the applicable range is Ta = 0 to +75C (regular specifications) or Ta = 0 to +85C (wide-range specifications). 644 Table 24.2 DC Characteristics (2) - Preliminary - 7 1 1 Conditions:VCC = 4.0 V to 5.5 V* , AVCC* = 4.0 V to 5.5 V, VSS = AVSS* = 0 V, 7 7 Ta = -20 to +75C* (regular specifications), Ta = -40 to +85C* (wide-range specifications) Item 2, 6 Schmitt P67 to P60* * , (1) trigger input ,54 to ,54*3, voltage ,54 to ,54 Symbol - VT VT + Min 1.0 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- Unit V Test Conditions VCC= 4.5 V to 5.5 V VCC x 0.7 V -- -- -- -- V V V V VCC < 4.5 V VT - VT VT + VT Schmitt P67 to P60 trigger input (KWUL = 00) voltage (in level switching)* 6 - + - 0.4 0.8 -- VCC x 0.7 V H8S/2138 Series only VCC = 4.0 V to 4.5 V VT - VT - VT VT + + - 0.3 0.8 -- VCC x 0.7 V -- -- -- -- -- -- -- VCC +0.3 VCC +0.3 VCC +0.3 V V V V V V V V V VT - VT P67 to P60 (KWUL = 01) P67 to P60 (KWUL = 10) P67 to P60 (KWUL = 11) VT VT VT VT VT VT (2) - + + - + + - + + + - 0.3 VCC x 0.3 -- VCC x 0.7 V VT - VT - VCC x 0.05 -- VCC x 0.4 -- VCC x 0.8 V VT - VT - VCC x 0.03 -- VCC x 0.45 -- -- -- VCC x 0.9 V VT - VT Input high voltage - 5(6, 67%<, NMI, MD1, MD0 EXTAL Port 7 Input pins except (1) and (2) above VIH 0.05 VCC - 0.7 VCC x 0.7 2.0 2.0 -- -- -- -- -- AVCC +0.3 V V Input low voltage 5(6, 67%<, MD1, MD0 NMI, EXTAL, input pins except (1) and (3) above (3) VIL -0.3 -0.3 -- -- 0.5 0.8 V V 645 Table 24.2 DC Characteristics (2) (cont) - Preliminary - 7 1 1 Conditions:VCC = 4.0 V to 5.5 V* , AVCC* = 4.0 V to 5.5 V, VSS = AVSS* = 0 V, 7 7 Ta = -20 to +75C* (regular specifications), Ta = -40 to +85C* (wide-range specifications) Item Output high All output pins voltage (except P97, and P52*4)*5 Symbol VOH Min VCC -0.5 3.5 Typ -- -- Max -- -- Unit Test Conditions V V IOH = -200 A IOH = -1 mA, VCC= 4.5 V to 5.5 V IOH = -1 mA, VCC < 4.5 V IOH = -1 mA IOL = 1.6 mA IOL = 10 mA Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V 3.0 P97, P52* Output low voltage Input leakage current 4 -- -- -- -- -- -- -- -- -- -- 0.4 1.0 10.0 1.0 1.0 1.0 V V V V A A A A 2.0 5 All output pins* Ports 1 to 3 VOL Iin -- -- -- -- -- 5(6 67%<, NMI, MD1, MD0 Port 7 Three-state Ports 1 to 6 leakage Ports 8, 9 current (off state) Input pullup MOS current Ports 1 to 3 ITSI -- -IP 50 -- 300 A Vin = 0 V, VCC = 4.5 V to 5.5 V Port 6 Ports 1 to 3 Port 6 Port 6 (P6PUE = 0) Port 6 (P6PUE = 1) Port 6 (P6PUE = 0) Port 6 (P6PUE = 1) 60 30 40 60 15 40 10 -- -- -- -- -- -- -- 500 200 400 500 150 400 110 A A A A A A A Vin = 0 V, VCC = 4.5 V to 5.5 V H8S/2138 Series only Vin = 0 V, VCC = 4.0 V to 4.5 V H8S/2138 Series only Vin = 0 V, VCC < 4.5 V 646 Table 24.2 DC Characteristics (2) (cont) - Preliminary - 7 1 1 Conditions:VCC = 4.0 V to 5.5 V* , AVCC* = 4.0 V to 5.5 V, VSS = AVSS* = 0 V, 7 7 Ta = -20 to +75C* (regular specifications), Ta = -40 to +85C* (wide-range specifications) Item Input capacitance Symbol Min -- -- -- -- ICC -- -- Sleep mode -- -- Standby mode* Analog power supply current 9 Typ -- -- -- -- 65 70 50 60 0.01 -- 3.2 0.01 -- -- -- Max 80 50 20 15 85 100 70 85 5.0 20.0 7.0 5.0 5.5 5.5 -- Unit pF pF pF pF mA mA mA mA A A mA A V V V Test Conditions Vin = 0 V, f = 1 MHz, Ta = 25C 5(6 NMI P52, P97, P42, P86 Input pins except (4) above (4) Cin Current 8 dissipation* Normal operation f = 16 MHz, H8S/2134 Series f = 16 MHz, H8S/2138 Series f = 16 MHz, H8S/2134 Series f = 16 MHz, H8S/2138 Series Ta 50C 50C < Ta -- -- AlCC -- -- During A/D, D/A conversion Idle 1 AVCC = 2.0 V to 5.5 V Operating Idle/not used Analog power supply voltage* RAM standby voltage Notes: AVCC VRAM 4.0 2.0 2.0 1. Do not leave the AVCC, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC by connection to the power supply (VCC), or some other method. 2. P67 to P60 include supporting module inputs multiplexed on those pins. 3. ,54 includes the $'75* signal multiplexed on that pin. 4. In the H8S/2138 Series, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0 and SDA0 (ICE = 1). P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS. 5. In the H8S/2138 Series, When ICE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. Ranges of VCC = 4.5 to 5.5 V, Ta = 0 to +75C (regular specifications), and Ta = 0 to +85C (widerange specifications) must be observed for flash memory programming/erasing. 8. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 9. The values are for VRAM VCC < 4.5 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 647 Table 24.2 DC Characteristics (3) - Preliminary - 1 Conditions (Mask ROM version): VCC = 2.7 V to 5.5 V, AVCC* = 2.7 V to 5.5 V, 1 VSS = AVSS* = 0 V, Ta = -20 to +75C 7 1 (Flash memory version): VCC = 3.0 V to 5.5 V* , AVCC* = 3.0 V to 5.5 V, 1 7 VSS = AVSS* = 0 V, Ta = -20 to +75C* Item Schmitt P67 to P60* * , (1) 3 trigger input ,54 to ,54* , voltage ,54 to ,54 2, 6 Symbol VT VT VT VT - Min VCC x 0.2 -- Typ -- -- Max -- Unit V Test Conditions + VCC x 0.7 V -- -- V V H8S/2138 Series only VT - VT Schmitt P67 to P60 trigger input (KWUL = 00) voltage (in level 6 switching)* P67 to P60 (KWUL = 01) - + - VCC x 0.05 -- VCC x 0.2 -- -- -- + VCC x 0.7 V -- -- V V VT - VT VT VT VT VT VT VT (2) - + + - VCC x 0.05 -- VCC x 0.3 -- -- -- VCC x 0.7 V -- -- V V VT - VT P67 to P60 (KWUL = 10) - + + - VCC x 0.05 -- VCC x 0.4 -- -- -- VCC x 0.8 V -- -- V V VT - VT P67 to P60 (KWUL = 11) - + + - VCC x 0.03 -- VCC x 0.45 -- -- -- -- -- -- -- -- VCC x 0.9 V -- VCC +0.3 VCC +0.3 VCC +0.3 V V V VT - VT Input high voltage + - 0.05 VCC x 0.9 VCC x 0.7 VCC x 0.7 VCC x 0.7 5(6, 67%<, NMI, MD1, MD0 EXTAL Port 7 Input pins except (1) and (2) above VIH AVCC +0.3 V V Input low voltage 5(6, 67%<, MD1, MD0 NMI, EXTAL, input pins except (1) and (3) above (3) VIL -0.3 -0.3 -- -- VCC x 0.1 V VCC x 0.2 V VCC < 4.0 V 0.8 V VCC = 4.0 V to 5.5 V 648 Table 24.2 DC Characteristics (3) (cont) - Preliminary - 1 Conditions (Mask ROM version): VCC = 2.7 V to 5.5 V, AVCC* = 2.7 V to 5.5 V, 1 VSS = AVSS* = 0 V, Ta = -20 to +75C 7 1 (Flash memory version): VCC = 3.0 V to 5.5 V* , AVCC* = 3.0 V to 5.5 V, 1 7 VSS = AVSS* = 0 V, Ta = -20 to +75C* Item Output high All output pins voltage (except P97, and P52*4)*5 P97, P52* Output low voltage 4 Symbol VOH Min VCC - 0.5 VCC - 1.0 1.0 Typ -- -- -- -- -- Max -- -- -- 0.4 1.0 Unit Test Conditions V V V V V IOH = -200 A IOH = -1 mA (VCC < 4.0 V) IOH = -1 mA IOL = 1.6mA IOL = 5 mA (VCC < 4.0 V), IOL = 10 mA (4.0 V VCC 5.5 V) Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V All output pins* Ports 1 to 3 5 VOL -- -- Input leakage current 5(6 67%<, NMI, MD1, MD0 Port 7 Iin -- -- -- -- -- -- -- 10.0 1.0 1.0 1.0 A A A A Three-state Ports 1 to 6 leakage Ports 8, 9 current (off state) Input pullup MOS current Ports 1 to 3 Port 6 Port 6 (P6PUE = 0) Port 6 (P6PUE = 1) Input 5(6 capacitance NMI P52, P97, P42, P86 Input pins except (4) above ITSI -- -IP 10 30 30 3 -- -- -- -- -- -- -- -- -- -- -- -- 150 250 250 70 80 50 20 15 A A A A pF pF pF pF Vin = 0 V, VCC = 2.7 V to 3.6 V Vin = 0 V, VCC = 2.7 V to 3.6 V H8S/2138 Series only Vin = 0 V, f = 1 MHz, Ta = 25C (4) Cin 649 Table 24.2 DC Characteristics (3) (cont) - Preliminary - 1 Conditions (Mask ROM version): VCC = 2.7 V to 5.5 V, AVCC* = 2.7 V to 5.5 V, 1 VSS = AVSS* = 0 V, Ta = -20 to +75C 7 1 (Flash memory version): VCC = 3.0 V to 5.5 V* , AVCC* = 3.0 V to 5.5 V, 1 7 VSS = AVSS* = 0 V, Ta = -20 to +75C* Item Current Normal operation 8 dissipation* Symbol ICC Min -- -- Sleep mode -- -- Standby mode* Analog power supply current 9 Typ 45 50 35 40 0.01 -- 3.2 0.01 -- -- -- Max 60 70 50 60 5.0 20.0 7.0 5.0 5.5 5.5 -- Unit mA mA mA mA A A mA A V V V Test Conditions f = 10 MHz, H8S/2134 Series f = 10 MHz, H8S/2138 Series f = 10 MHz, H8S/2134 Series f = 10 MHz, H8S/2138 Series Ta 50C 50C < Ta -- AlCC -- -- -- During A/D, D/A conversion Idle 1 AVCC = 2.0 V to 5.5 V Operating Idle/not used Analog power supply voltage* RAM standby voltage Notes: AVCC VRAM 2.7 2.0 2.0 1. Do not leave the AVCC, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a value in the range 2.0 V to 5.5 V to AVCC by connection to the power supply (VCC), or some other method. 2. P67 to P60 include supporting module inputs multiplexed on those pins. 3. ,54 includes the $'75* signal multiplexed on that pin. 4. In the H8S/2138 Series, P52/SCK0/SCL0 and P97/SDA0 are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0 and SDA0 (ICE = 1). P52/SCK0 and P97 (ICE = 0) high levels are driven by NMOS. 5. In the H8S/2138 Series, When ICE = 0. Low-level output when the bus drive function is selected is determined separately. 6. The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is equivalent to the applied voltage. 7. For flash memory program/erase operations, the applicable ranges are VCC = 3.0 V to 3.6 V, Ta = 0 to +75C. 8. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 9. The values are for VRAM VCC < 2.7 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 650 Table 24.3 Permissible Output Currents - Preliminary - Conditions:VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Permissible output low current (per pin) SCL1, SCL0, SDA1, SDA0 Ports 1, 2, 3 Other output pins Permissible output low current (total) Total of ports 1, 2, and 3 IOL Total of all output pins, including the above -IOH -IOH Symbol Min IOL -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- Max 20 10 2 80 120 2 40 Unit mA mA mA mA mA mA mA Permissible output All output pins high current (per pin) Permissible output high current (total) Total of all output pins Notes: 1. To protect chip reliability, do not exceed the output current values in table 24.3. 2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the output line, as show in figures 24.1 and 24.2. Table 24.3 Permissible Output Currents (cont) - Preliminary - Conditions: VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C Item Permissible output low current (per pin) SCL1, SCL0, SDA1, SDA0 Ports 1, 2, 3 Other output pins Permissible output low current (total) Total of ports 1, 2, and 3 IOL Total of all output pins, including the above -IOH -IOH Symbol Min IOL -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- Max 10 2 1 40 60 2 30 Unit mA mA mA mA mA mA mA Permissible output All output pins high current (per pin) Permissible output high current (total) Total of all output pins Notes: 1. To protect chip reliability, do not exceed the output current values in table 24.3. 2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the output line, as show in figures 24.1 and 24.2. 651 Table 24.4 Bus Drive Characteristics - Preliminary - Conditions: VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Schmitt trigger input voltage Symbol VT VT Input high voltage Input low voltage Output low voltage - Min VCC x 0.3 -- Typ -- -- -- -- -- -- -- -- -- -- Max -- VCC x 0.7 -- VCC + 0.5 VCC x 0.3 0.8 0.5 0.4 20 1.0 250 Unit V Test Conditions VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V + VT - VT VIH VIL VOL + - VCC x 0.05 VCC x 0.7 -0.5 -- -- -- V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V IOL = 16 mA, VCC = 4.5 V to 5.5 V IOL = 8 mA IOL = 3 mA V Input capacitance Cin -- -- pF A ns Vin = 0 V, f = 1 MHz, Ta = 25C Vin = 0.5 to VCC - 0.5 V VCC = 2.7 V to 5.5 V Three-state leakage | ITSI | current (off state) SCL, SDA output fall time tOf 20 + 0.1Cb -- 652 H8S/2138 Series or H8S/2134 Series chip 2 k Port Darlington pair Figure 24.1 Darlington Pair Drive Circuit (Example) H8S/2138 Series or H8S/2134 Series chip 600 Ports 1 to 3 LED Figure 24.2 LED Drive Circuit (Example) 24.3 AC Characteristics Figure 24.3 shows the test conditions for the AC characteristics. 5V RL Chip output pin C = 30 pF: All output ports RL = 2.4 k RH = 12 k I/O timing test levels * Low level: 0.8 V * High level: 2.0 V C RH Figure 24.3 Output Load Circuit 653 24.3.1 Clock Timing Table 24.5 shows the clock timing. The clock timing specified here covers clock (o) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 22, Clock Pulse Generator. Table 24.5 Clock Timing - Preliminary - Condition A:VCC = 5.0 V 10%, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B:VCC = 4.0 V to 5.5V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C:VCC = 2.7 V to 5.5V*, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 20 MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Oscillation settling time at reset (crystal) Oscillation settling time in software standby (crystal) External clock output stabilization delay time Symbol tcyc tCH tCL tCr tCf tOSC1 Min 50 17 17 -- -- 10 Max 500 -- -- 8 8 -- Condition B 16 MHz Min 62.5 20 20 -- -- 10 Max 500 -- -- 10 10 -- Condition C 10 MHz Min 100 30 30 -- -- 20 Max 500 -- -- 20 20 -- Unit ns ns ns ns ns ms Figure 24.5 Figure 24.6 Test Conditions Figure 24.4 Figure 24.4 tOSC2 8 -- 8 -- 8 -- ms tDEXT 500 -- 500 -- 500 -- s Note: * For the low-voltage F-ZTAT version, VCC = 3.0 V to 5.5 V. 654 tcyc tCH o tCL tCr tCf Figure 24.4 System Clock Timing EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 o Figure 24.5 Oscillation Settling Timing Figure 24.6 Oscillation Setting Timing (Exiting Software Standby Mode) 655 24.3.2 Control Signal Timing Table 24.6 shows the control signal timing. The only external interrupts that can operate on the subclock (o = 32.768 kHz) are NMI and IRQ0, IRQ1, IRQ2, IRQ6, and IRQ7. Table 24.6 Control Signal Timing - Preliminary - Condition A:VCC = 5.0 V 10%, VSS = 0 V, o = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B:VCC = 4.0 V to 5.5V, VSS = 0 V, o = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C:VCC = 2.7 V to 5.5V*, VSS = 0 V, o = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 20 MHz Item Symbol Min tRESS tRESW tNMIS tNMIH tNMIW 200 20 150 10 200 Max -- -- -- -- -- Condition B 16 MHz Min 200 20 150 10 200 Max -- -- -- -- -- Condition C 10 MHz Min 300 20 250 10 200 Max -- -- -- -- -- ns Unit ns tcyc ns Figure 24.8 Test Conditions Figure 24.7 5(6 setup time 5(6 pulse width NMI setup time (NMI) NMI hold time (NMI) NMI pulse width (exiting software standby mode) IRQ setup time (,54 to ,54) IRQ hold time (,54 to ,54) IRQ pulse width (,54, ,54, ,54 to ,54) (exiting software standby mode) tIRQS tIRQH tIRQW 150 10 200 -- -- -- 150 10 200 -- -- -- 250 10 200 -- -- -- ns ns ns Note: * For the low-voltage F-ZTAT version, VCC = 3.0 V to 5.5 V. 656 o tRESS RES tRESW tRESS Figure 24.7 Reset Input Timing o tNMIS NMI tNMIW tNMIH IRQi (i = 7 to 0) tIRQS IRQ Edge input tIRQS IRQ Level input tIRQW tIRQH Figure 24.8 Interrupt Input Timing 657 24.3.3 Bus Timing Table 24.7 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (o = 32.768 kHz). Table 24.7 Bus Timing - Preliminary - Condition A:VCC = 5.0 V 10%, VSS = 0 V, o = 2 MHz to maximum operating frequency,Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B:VCC = 4.0 V to 5.5V, VSS = 0 V, o = 2 MHz to maximum operating frequency,Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C:VCC = 2.7 V to 5.5V*, VSS = 0 V, o = 2 MHz to maximum operating frequency,Ta = -20 to +75C Condition A 20 MHz Item Address delay time Address setup time Address hold time Symbol Min tAD tAS tAH tCSD tASD tRSD1 tRSD2 tRDS tRDH -- Max 20 Min -- Condition B 16 MHz Max 30 Min -- Condition C 10 MHz Max 40 Test Unit Conditions ns ns ns ns ns ns ns ns ns ns ns Figure 24.9 to figure 24.13 -- 0.5 x tcyc - 15 -- 0.5 x tcyc - 10 -- -- -- -- 15 0 -- -- 20 30 30 30 -- -- 1.0 x tcyc - 30 1.5 x tcyc - 25 0.5 x -- tcyc - 20 0.5 x -- tcyc - 15 -- -- -- -- 20 0 -- -- 30 45 45 45 -- -- 1.0 x tcyc - 40 1.5 x tcyc - 35 0.5 x -- tcyc - 30 0.5 x -- tcyc - 20 -- -- -- -- 35 0 -- -- 40 60 60 60 -- -- 1.0 x tcyc - 60 1.5 x tcyc - 50 &6 delay time (,26) $6 delay time 5' delay time 1 5' delay time 2 Read data setup time Read data hold time Read data tACC1 access time 1 Read data tACC2 access time 2 658 Table 24.7 Bus Timing (cont) - Preliminary - Condition A:VCC = 5.0 V 10%, VSS = 0 V, o = 2 MHz to maximum operating frequency,Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B:VCC = 4.0 V to 5.5V, VSS = 0 V, o = 2 MHz to maximum operating frequency,Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C:VCC = 2.7 V to 5.5V*, VSS = 0 V, o = 2 MHz to maximum operating frequency,Ta = -20 to +75C Condition A 20 MHz Item Symbol Min -- -- -- -- -- Max 2.0 x tcyc - 30 2.5 x tcyc - 25 3.0 x tcyc - 30 30 30 Min -- -- -- -- -- Condition B 16 MHz Max 2.0 x tcyc - 40 2.5 x tcyc - 35 3.0 x tcyc - 40 45 45 Min -- -- -- -- -- Condition C 10 MHz Max 2.0 x tcyc - 60 2.5 x tcyc - 50 3.0 x tcyc - 60 60 60 Test Unit Conditions ns ns ns ns ns ns ns ns ns ns ns ns Figure 24.9 to figure 24.13 Read data tACC3 access time 3 Read data tACC4 access time 4 Read data tACC5 access time 5 :5 delay time 1 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH :5 delay time 2 :5 pulse width 1 -- 1.0 x tcyc - 20 -- 1.5 x tcyc - 20 -- 0 10 30 5 30 -- -- -- -- 1.0 x -- tcyc - 30 1.5 x -- tcyc - 30 -- 0 15 45 5 45 -- -- -- -- 1.0x -- tcyc - 40 1.5 x -- tcyc - 40 -- 0 20 60 10 60 -- -- -- -- :5 pulse width 2 Write data delay time Write data setup time Write data hold time :$,7 setup time :$,7 hold time Note: * For the low-voltage F-ZTAT version, VCC = 3.0 V to 5.5 V. 659 T1 T2 o tAD A15 to A0, IOS* tCSD AS* tAS tAH tASD tASD tRSD1 RD (read) tAS tACC2 tRSD2 tACC3 D7 to D0 (read) tRDS tRDH tWRD2 WR (write) tAS tWDD D7 to D0 (write) tWSW1 tWRD2 tAH tWDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 24.9 Basic Bus Timing (Two-State Access) 660 T1 T2 T3 o tAD A15 to A0, IOS* tCSD AS* tAS tASD tASD tAH tRSD1 RD (read) tAS tACC4 tRSD2 tACC5 D7 to D0 (read) tRDS tRDH tWRD1 WR (write) tWDD tWDS D7 to D0 (write) tWSW2 tWRD2 tAH tWDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 24.10 Basic Bus Timing (Three-State Access) 661 T1 T2 TW T3 o A15 to A0, IOS* AS* RD (read) D7 to D0 (read) WR (write) D7 to D0 (write) tWTS tWTH WAIT tWTS tWTH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 24.11 Basic Bus Timing (Three-State Access with One Wait State) 662 T1 T2 or T3 T1 T2 o tAD A15 to A0, IOS* tAS AS* tASD tASD tAH tRSD2 RD (read) tACC3 D7 to D0 (read) tRDS tRDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 24.12 Burst ROM Access Timing (Two-State Access) 663 T1 o T2 or T3 T1 tAD A15 to A0, IOS* AS* tRSD2 RD (read) tACC1 D7 to D0 (read) tRDS tRDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 24.13 Burst ROM Access Timing (One-State Access) 664 24.3.4 Timing of On-Chip Supporting Modules Tables 24.8 and 24.9 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (o = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 24.8 Timing of On-Chip Supporting Modules (1) - Preliminary - 1 Condition A:VCC = 5.0 V 10%, VSS = 0 V, o = 32.768 kHz* , 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) 1 Condition B:VCC = 4.0 V to 5.5V, VSS = 0 V, o = 32.768 kHz* , 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) 2 1 Condition C:VCC = 2.7 V to 5.5V* , VSS = 0 V, o = 32.768 kHz* , 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A Condition B Condition C 20 MHz Item I/O ports Symbol Min Output data delay tPWD time Input data setup time Input data hold time FRT tPRS tPRH -- 30 30 -- 30 30 1.5 2.5 Max 50 -- -- 50 -- -- -- -- 16 MHz Min -- 30 30 -- 30 30 1.5 2.5 Max 50 -- -- 50 -- -- -- -- 10 MHz Min -- 50 50 -- 50 50 1.5 2.5 Max 100 -- -- 100 -- -- -- -- tcyc Figure 24.16 ns Figure 24.15 Test Unit Conditions ns Figure 24.14 Timer output delay tFTOD time Timer input setup tFTIS time Timer clock input tFTCS setup time Timer clock pulse width Single edge Both edges tFTCWH tFTCWL 665 Table 24.8 Timing of On-Chip Supporting Modules (1) (cont) - Preliminary - 1 Condition A:VCC = 5.0 V 10%, VSS = 0 V, o = 32.768 kHz* , 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) 1 Condition B:VCC = 4.0 V to 5.5V, VSS = 0 V, o = 32.768 kHz* , 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) 2 1 Condition C:VCC = 2.7 V to 5.5V* , VSS = 0 V, o = 32.768 kHz* , 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A Condition B Condition C 20 MHz Item TMR Timer output delay time Timer reset input setup time Symbol Min tTMOD tTMRS -- 30 30 1.5 2.5 -- 4 6 tSCKW tSCKr tSCKf 0.4 -- -- Max 50 -- -- -- -- 50 -- -- 0.6 1.5 1.5 16 MHz Min -- 30 30 1.5 2.5 -- 4 6 0.4 -- -- Max 50 -- -- -- -- 50 -- -- 0.6 1.5 1.5 10 MHz Min -- 50 50 1.5 2.5 -- 4 6 0.4 -- -- Max 100 -- -- -- -- 100 -- -- 0.6 1.5 1.5 tScyc tcyc ns tcyc Figure 24.20 Figure 24.21 tcyc Test Unit Conditions ns Figure 24.17 Figure 24.19 Figure 24.18 Timer clock input tTMCS setup time Timer clock pulse width Single edge Both edges tTMCWH tTMCWL tPWOD PWM, Pulse output PWMX delay time SCI Input clock cycle Asynchro- tScyc nous Synchronous Input clock pulse width Input clock rise time Input clock fall time 666 Table 24.8 Timing of On-Chip Supporting Modules (1) (cont) - Preliminary - 1 Condition A:VCC = 5.0 V 10%, VSS = 0 V, o = 32.768 kHz* , 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) 1 Condition B:VCC = 4.0 V to 5.5V, VSS = 0 V, o = 32.768 kHz* , 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) 2 1 Condition C:VCC = 2.7 V to 5.5V* , VSS = 0 V, o = 32.768 kHz* , 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A Condition B Condition C 20 MHz Item SCI Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input converter setup time Symbol Min tTXD -- Max 50 16 MHz Min -- Max 50 10 MHz Min -- Max 100 Test Unit Conditions ns Figure 24.22 tRXS 50 -- 50 -- 100 -- ns tRXH 50 -- 50 -- 100 -- ns tTRGS 30 -- 30 -- 50 -- ns Figure 24.23 Notes: 1. Only supporting modules that can be used in subclock operation. 2. For the low-voltage F-ZTAT version, VCC = 3.0 V to 5.5 V. 667 T1 T2 o tPRS Ports 1 to 9 (read) tPRH tPWD Ports 1 to 6, 8, 9 (write) Figure 24.14 I/O Port Input/Output Timing o tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 24.15 FRT Input/Output Timing o tFTCS FTCI tFTCWL tFTCWH Figure 24.16 FRT Clock Input Timing 668 o tTMOD TMO0, TMO1 TMOX Figure 24.17 8-Bit Timer Output Timing o tTMCS TMCI0, TMCI1 TMIX, TMIY tTMCWL tTMCWH tTMCS Figure 24.18 8-Bit Timer Clock Input Timing o tTMRS TMRI0, TMRI1 TMIX, TMIY Figure 24.19 8-Bit Timer Reset Input Timing o tPWOD PW15 to PW0, PWX1 to PWX0 Figure 24.20 PWM, PWMX Output Timing 669 tSCKW SCK0 to SCK2 tSCKr tSCKf tScyc Figure 24.21 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS RxD0 to RxD2 (receive data) tRXH Figure 24.22 SCI Input/Output Timing (Synchronous Mode) o tTRGS ADTRG Figure 24.23 A/D Converter External Trigger Input Timing 670 Table 24.8 Timing of On-Chip Supporting Modules (2) - Preliminary - Condition A:VCC = 5.0 V 10%, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B:VCC = 4.0 V to 5.5V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C:VCC = 2.7 V to 5.5V*, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 20 MHz Item HIF read cycle Symbol Min 10 10 120 -- 0 -- 10 10 60 30 Max -- -- -- 100 25 120 -- -- -- -- Condition B 16 MHz Min 10 10 120 -- 0 -- 10 10 60 30 Max -- -- -- 100 25 120 -- -- -- -- Condition C 10 MHz Min 10 10 220 -- 0 -- 10 10 100 50 Max -- -- -- 200 40 200 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 24.24 &6/HA0 setup item tHAR &6/HA0 hold time tHRA ,25 pulse width HDB delay time HDB hold time HIRQ delay time HIF write cycle tHRPW tHRD tHRF tHIRQ tHAW &6/HA0 setup item &6/HA0 hold time tHWA ,2: pulse width HDB setup time Fast A20 gate not used Fast A20 gate used HDB hold time GA20 delay time tHWD tHGA tHWPW tHDW 45 15 -- -- -- 90 55 15 -- -- -- 90 85 25 -- -- -- 180 ns ns ns Note: * For the low-voltage F-ZTAT version, VCC = 3.0 V to 5.5 V. 671 Host interface read timing CS/HA0 tHAR IOR tHRD HDB7 to HDB0 Valid data tHRF tHRPW tHRA tHIRQ HIRQi* (i = 1, 11, 12) Note: * The rising edge timing is the same as the port 4 output timing. See figure 24.13. Host interface write timing CS/HA0 tHAW IOW tHDW HDB7 to HDB0 tHWD tHWPW tHWA tHGA GA20 Figure 24.24 Host Interface Timing 672 - Preliminary - Table 24.10 I C Bus Timing Conditions:VCC = 2.7 V to 5.5 V, VSS = 0 V, o = 5 MHz to maximum operating frequency, Ta = -20 to +75C Ratings Item SCL clock cycle time SCL clock high pulse width SCL clock low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Symbol tSCL tSCLH tSCLL tSr tSf tSP Min 12 3 5 -- -- -- Typ -- -- -- -- -- -- Max -- -- -- 7.5* 300 1 Unit tcyc tcyc tcyc tcyc ns tcyc Test Conditions Notes Figure 24.25 2 tBUF tSTAH tSTAS 5 3 3 -- -- -- -- -- -- tcyc tcyc tcyc tSTOS 3 0.5 0 -- -- -- -- -- -- -- -- 400 tcyc tcyc ns pF 2 Data input setup tSDAS time Data input hold time SCL, SDA capacitive load tSDAH Cb Note: * 17.5tcyc can be set according to the clock selected for use by the I C module. For details, see section 16.4, Usage Notes. 673 SDA0, SDA1 tBUF VIH VIL tSTAH tSCLH tSP tSTOS tSTAS SCL0, SCL1 P* S* tSf tSCLL tSCL tSr tSDAH Sr* tSDAS P* Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition Figure 24.25 I C Bus Interface Input/Output Timing (Option) 2 674 24.4 A/D Conversion Characteristics Tables 24.10 and 24.11 list the A/D conversion characteristics. Table 24.10 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) - Preliminary - Condition A:VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B:VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) 5 5 Condition C:VCC = 2.7 V to 5.5 V* , AVCC = 2.7 V to 5.5 V* , VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 20 MHz Item Resolution Conversion time Analog input capacitance Permissible signalsource impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 -- -- -- Typ 10 -- -- -- Max 10 6.7 20 3 10* Condition B 16 MHz Min 10 -- -- -- Typ 10 -- -- -- Max 10 8.4 20 3 10* Condition C 10 MHz Min 10 -- -- -- Typ 10 -- -- -- Max 10 13.4 20 1 10* Unit Bits s pF k 4 5* 4 5* 2 5* -- -- -- -- -- -- -- -- -- -- 3.0 3.5 3.5 0.5 4.0 -- -- -- -- -- -- -- -- -- -- 3.0 3.5 3.5 0.5 4.0 -- -- -- -- -- -- -- -- -- -- 7.0 7.5 7.5 0.5 8.0 LSB LSB LSB LSB LSB Notes: 1. 2. 3. 4. 5. When 4.0 V AVCC 5.5 V When 2.7 V AVCC < 4.0 V When conversion time 11. 17 s (CKS = 1 and o 12 MHz, or CKS = 0) When conversion time < 11. 17 s (CKS = 1 and o > 12 MHz) For the low-voltage F-ZTAT version, VCC = 3.0 V to 5.5 V and AVCC = 3.0 V to 5.5 V. 675 Table 24.11 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) - Preliminary - Condition A:VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B:VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) 5 5 Condition C:VCC = 2.7 V to 5.5 V* , AVCC = 2.7 V to 5.5 V* , VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 20 MHz Item Resolution Conversion time Analog input capacitance Permissible signalsource impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 -- -- -- Typ 10 -- -- -- Max 10 6.7 20 3 10* Condition B 16 MHz Min 10 -- -- -- Typ 10 -- -- -- Max 10 8.4 20 3 10* Condition C 10 MHz Min 10 -- -- -- Typ 10 -- -- -- Max 10 13.4 20 1 10* Unit Bits s pF k 4 5* 4 5* 2 5* -- -- -- -- -- -- -- -- -- -- 5.0 5.5 5.5 0.5 6.0 -- -- -- -- -- -- -- -- -- -- 5.0 5.5 5.5 0.5 6.0 -- -- -- -- -- -- -- -- -- -- 11.0 11.5 11.5 0.5 12.0 LSB LSB LSB LSB LSB Notes: 1. 2. 3. 4. 5. When 4.0 V AVCC 5.5 V When 2.7 V AVCC < 4.0 V When conversion time 11. 17 s (CKS = 1 and o 12 MHz, or CKS = 0) When conversion time < 11. 17 s (CKS = 1 and o > 12 MHz) For the low-voltage F-ZTAT version, VCC = 3.0 V to 5.5 V and AVCC = 3.0 V to 5.5 V. 676 24.5 D/A Conversion Characteristics Table 24.12 lists the D/A conversion characteristics. Table 24.12 D/A Conversion Characteristics - Preliminary - Condition A:VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B:VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C:VCC = 2.7 V to 5.5 V*, AVCC = 2.7 V to 5.5 V*, VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to +75C Condition A 20 MHz Item Resolution Min 8 Typ 8 -- Max 8 10 Min 8 -- Condition B 16 MHz Typ 8 -- Max 8 10 Min 8 -- Condition C 10 MHz Typ 8 -- Max 8 10 Unit Bits s Conversion With 20 pF -- time load capacitance Absolute accuracy With 2 M load resistance With 4 M load resistance -- 1.0 1.5 -- 1.0 1.5 -- 2.0 3.0 LSB -- -- 1.0 -- - 1.0 -- -- 2.0 Note: * For the low-voltage F-ZTAT version, VCC = 3.0 V to 5.5 V and AVCC = 3.0 V to 5.5 V. 677 24.6 Flash Memory Characteristics Table 24.13 shows the flash memory characteristics. Table 24.13 Flash Memory Characteristics -- Preliminary -- Conditions (5-V version): VCC = 5.0 V 10%, VSS = 0 V, Ta = 0 to +75C (regular specifications), Ta = 0 to +85C (wide-range specifications) (Low-voltage version):VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = 0 to +75C (programming/erasing operating temperature) Item 1, 2, 4 Programming time* * * Symbol Min tP tE NWEC x y z N -- -- -- 10 50 150 10 10 4 2 4 -- Typ 10 100 -- -- -- -- -- -- -- -- -- -- Max 200 1200 100 -- -- 200 -- -- -- -- -- 1000 Unit ms/ 32 bytes ms/ block Times s s s s s s s s Times Test Condition 1, 3, 5 Erase time* * * Reprogramming count Programming Wait time after 1 SWE-bit setting* Wait time after 1 PSU-bit setting* Wait time after 1, 4 P-bit setting* * Wait time after 1 P-bit clear* Wait time after 1 PSU-bit clear* Wait time after 1 PV-bit setting* Wait time after 1 dummy write* Wait time after 1 PV-bit clear* Maximum programming 1, 4, 5 count* * * tP = 200 s 678 Table 24.13 Flash Memory Characteristics (cont) -- Preliminary -- Conditions (5-V version): VCC = 5.0 V 10%, VSS = 0 V, Ta = 0 to +75C (regular specifications), Ta = 0 to +85C (wide-range specifications) (Low-voltage version):VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = 0 to +75C (programming/erasing operating temperature) Item Erase Wait time after 1 SWE-bit setting* Wait time after 1 ESU-bit setting* Wait time after 1, 6 E-bit setting* * Wait time after 1 E-bit clear* Wait time after 1 ESU-bit clear* Wait time after 1 EV-bit setting* Wait time after 1 dummy write* Wait time after 1 EV-bit clear* Maximum erase 1, 6, 7 count* * * Symbol Min x y z N 10 200 5 10 10 20 2 5 -- Typ -- -- -- -- -- -- -- -- -- Max -- -- 10 -- -- -- -- -- 120 Unit s s ms s s s s s Times tE = 10 ms Test Condition Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 32 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max) = wait time after P-bit setting (z) x maximum programming count (N)) 5. Number of times when the wait time after P-bit setting (z) = 200 s. The number of writes should be set according to the actual set value of z to allow programming within the maximum programming time (tP). 6. Maximum erase time (tE (max) = Wait time after E-bit setting (z) x maximum erase count (N)) 7. Number of times when the wait time after E-bit setting (z) = 10 ms. The number of erases should be set according to the actual set value of z to allow erasing within the maximum erase time (tE). 679 24.7 Usage Note The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this manual. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, on-chip ROM, layout patterns, etc. When system evaluation testing is carried out using the F-ZTAT version, the same evaluation tests should also be conducted for the mask ROM version when changing over to that version. 680 Appendix A Instruction Set A.1 Instruction Operation Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / ()<> General register (destination )* General register (source)* General register* 1 1 1 General register (32-bit register) Multiply-and-accumulate register (32-bit register)* Destination operand Source operand Extend register Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Transfer from left-hand operand to right-hand operand, or transition from lefthand state to right-hand state NOT (logical complement) Operand contents 2 :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 2. MAC instructions cannot be used in the H8S/2138 Series and H8S/2134 Series. 681 Condition Code Notation Symbol Meaning Changes according operation result. * 0 1 -- Indeterminate (value not guaranteed). Always cleared to 0. Always set to 1. Not affected by operation result. 682 Table A.1 Instruction Set 1. Data Transfer Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 B B B B B B B B B B B B B B B B W W W W W W W W W W W W W W 2 2 2 4 8 2 2 4 6 2 4 8 2 2 4 6 4 2 2 4 8 2 4 6 2 4 8 2 4 6 #xx:8Rd8 Rs8Rd8 @ERsRd8 @(d:16,ERs)Rd8 @(d:32,ERs)Rd8 @ERsRd8,ERs32+1ERs32 @aa:8Rd8 @aa:16Rd8 @aa:32Rd8 Rs8@ERd Rs8@(d:16,ERd) Rs8@(d:32,ERd) ERd32-1ERd32,Rs8@ERd Rs8@aa:8 Rs8@aa:16 Rs8@aa:32 #xx:16Rd16 Rs16Rd16 @ERsRd16 @(d:16,ERs)Rd16 @(d:32,ERs)Rd16 @ERsRd16,ERs32+2ERs32 @aa:16Rd16 @aa:32Rd16 Rs16@ERd Rs16@(d:16,ERd) Rs16@(d:32,ERd) ERd32-2ERd32,Rs16@ERd Rs16@aa:16 Rs16@aa:32 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Normal @@aa I -- HNZ VC 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0 ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 3 5 3 3 4 2 3 5 3 3 4 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn 683 Table A.1 Instruction Set (cont) 1. Data Transfer Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) MOV MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 L L L L L L L L L L L L L L W L W L L 6 2 4 6 10 4 6 8 4 6 10 4 6 8 #xx:32Rd32 ERs32ERd32 @ERsERd32 @(d:16,ERs)ERd32 @(d:32,ERs)ERd32 @ERsERd32,ERs32+4ERs32 @aa:16ERd32 @aa:32ERd32 ERs32@ERd ERs32@(d:16,ERd) ERs32@(d:32,ERd) ERd32-4ERd32,ERs32@ERd ERs32@aa:16 ERs32@aa:32 2 @SPRn16,SP+2SP 4 @SPERn32,SP+4SP 2 SP-2SP,Rn16@SP 4 SP-4SP,ERn32@SP 4 (@SPERn32,SP+4SP) Repeated for each restored register. 4 (SP-4SP,ERn32@SP) Repeated for each saved register. ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- Normal @@aa I -- HNZ VC 3 1 4 5 7 5 5 6 4 5 7 5 5 6 3 5 3 5 POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn LDM LDM @SP+,(ERm-ERn) -- -- -- -- -- -- 7/9/11 [1] STM STM (ERm-ERn),@-SP L -- -- -- -- -- -- 7/9/11 [1] MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 Cannot be used with the H8S/2138 Series and H8S/2134 Series. [2] [2] 684 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 2. Arithmetic Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd B B W W L L B B L L L B W W L L B B W W L L B B L L L B W W L L 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 Rd8+#xx:8Rd8 Rd8+Rs8Rd8 Rd16+#xx:16Rd16 Rd16+Rs16Rd16 ERd32+#xx:32ERd32 ERd32+ERs32ERd32 Rd8+#xx:8+CRd8 Rd8+Rs8+CRd8 ERd32+1ERd32 ERd32+2ERd32 ERd32+4ERd32 Rd8+1Rd8 Rd16+1Rd16 Rd16+2Rd16 ERd32+1ERd32 ERd32+2ERd32 Rd8 decimal adjust Rd8 Rd8-Rs8Rd8 Rd16-#xx:16Rd16 Rd16-Rs16Rd16 ERd32-#xx:32ERd32 ERd32-ERs32ERd32 Rd8-#xx:8-CRd8 Rd8-Rs8-CRd8 ERd32-1ERd32 ERd32-2ERd32 ERd32-4ERd32 Rd8-1Rd8 Rd16-1Rd16 Rd16-2Rd16 ERd32-1ERd32 ERd32-2ERd32 -- -- -- [3] -- [3] -- [4] -- [4] -- -- [5] [5] Normal @@aa I -- HNZ VC 1 1 2 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 3 1 [5] [5] 1 1 1 1 1 1 1 1 1 1 ADDX ADDX #xx:8,Rd ADDX Rs,Rd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd ------------ ------------ ------------ ---- ---- ---- ---- ---- --* -- -- [3] -- [3] -- [4] -- [4] -- -- -- -- -- -- -- INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA SUB DAA Rd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd * SUBX SUBX #xx:8,Rd SUBX Rs,Rd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd ------------ ------------ ------------ ---- ---- ---- ---- ---- -- -- -- -- -- DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd 685 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 2. Arithmetic Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) DAS MULXU DAS Rd MULXU.B Rs,Rd MULXU.W Rs,ERd B B W B W B 2 2 2 4 4 2 Rd8 decimal adjust Rd8 Rd8xRs8Rd16 (unsigned multiplication) Rd16xRs16ERd32 (unsigned multiplication) Rd8xRs8Rd16 (signed multiplication) Rd16xRs16ERd32 (signed multiplication) Rd16/Rs8Rd16 (RdH: remainder, RdL: quotient) (unsigned division) ERd32/Rs16ERd32 (Ed: remainder, Rd: quotient) (unsigned division) Rd16/Rs8Rd16 (RdH: remainder, RdL: quotient) (signed division) ERd32/Rs16ERd32 (Ed: remainder, Rd: quotient) (signed division) Rd8-#xx:8 --* *-- Normal @@aa I -- HNZ VC 1 12 20 13 21 12 ------------ ------------ ---- ---- ---- ---- MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd -- -- [6] [7] -- -- DIVXU.W Rs,ERd W 2 -- -- [6] [7] -- -- 20 DIVXS DIVXS.B Rs,Rd B 4 -- -- [8] [7] -- -- 13 DIVXS.W Rs,ERd W 4 -- -- [8] [7] -- -- 21 CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd B B W W L L B W L W L W L B 2 2 4 2 6 2 2 2 2 2 2 2 2 4 -- -- -- [3] -- [3] -- [4] -- [4] -- -- -- ---- 0 ---- 0 ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 1 1 2 1 3 1 1 1 1 1 1 1 1 4 Rd8-Rs8 Rd16-#xx:16 Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 0-Rd8Rd8 0-Rd16Rd16 0-ERd32ERd32 0 ( NEG NEG.B Rd NEG.W Rd NEG.L ERd EXTU EXTU.W Rd EXTU.L ERd EXTS EXTS.W Rd EXTS.L ERd TAS TAS @ERd 686 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 2. Arithmetic Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) MAC MAC @ERn+,@ERm+ Cannot be used with the H8S/2138 Series and H8S/2134 Series. [2] CLRMAC CLRMAC LDMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC STMAC MACH,ERd STMAC MACL,ERd Normal @@aa I -- HNZ VC 687 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 3. Logic Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd B B W W L L B B W W L L B B W W L L B W L 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8Rd8 Rd16Rd16 ERd32ERd32 -- Normal @@aa I -- HNZ VC -- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd NOT.L ERd 688 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 4. Shift Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C MSB LSB 0 MSB LSB C MSB LSB MSB LSB C MSB LSB -- -- ---- Normal @@aa I -- HNZ VC 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ---- ---- ---- ---- ---- ---- ---- C ---- ---- ---- ---- ---- 0 ---- ---- ---- ---- ---- ---- ---- C ---- ---- ---- ---- ---- ---- ---- ---- ---- SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd 689 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 4. Shift Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 MSB LSB 2 2 C MSB LSB MSB LSB C -- -- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Normal @@aa I -- HNZ VC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd C ---- ---- ---- 690 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 5. Bit Manipulation Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) Normal @@aa I -- HNZ VC BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 (#xx:3 of Rd8)1 (#xx:3 of @ERd)1 (#xx:3 of @aa:8)1 (#xx:3 of @aa:16)1 (#xx:3 of @aa:32)1 (Rn8 of Rd8)1 (Rn8 of @ERd)1 (Rn8 of @aa:8)1 (Rn8 of @aa:16)1 (Rn8 of @aa:32)1 (#xx:3 of Rd8)0 (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (#xx:3 of @aa:16)0 (#xx:3 of @aa:32)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 (Rn8 of @aa:8)0 (Rn8 of @aa:16)0 (Rn8 of @aa:32)0 (#xx:3 of Rd8) [ (#xx:3 of Rd8)] (#xx:3 of @ERd) [ (#xx:3 of @ERd)] (#xx:3 of @aa:8) [ (#xx:3 of @aa:8)] (#xx:3 of @aa:16) [ (#xx:3 of @aa:16)] (#xx:3 of @aa:32) [ (#xx:3 of @aa:32)] (Rn8 of Rd8) [ (Rn8 of Rd8)] ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 (Rn8 of @ERd) [ (Rn8 of @ERd)] -- -- -- -- -- -- (Rn8 of @aa:8) [ (Rn8 of @aa:8)] -- -- -- -- -- -- (Rn8 of @aa:16) [ (Rn8 of @aa:16)] (Rn8 of @aa:32) [ (Rn8 of @aa:32)] ------------ ------------ 691 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 5. Bit Manipulation Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 (#xx:3 of Rd8)Z (#xx:3 of @ERd)Z (#xx:3 of @aa:8)Z (#xx:3 of @aa:16)Z (#xx:3 of @aa:32)Z (Rn8 of Rd8)Z (Rn8 of @ERd)Z (Rn8 of @aa:8)Z (Rn8 of @aa:16)Z (Rn8 of @aa:32)Z (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C C(#xx:3 of Rd8) C(#xx:3 of @ERd) C(#xx:3 of @aa:8) C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) C(#xx:3 of Rd8) C(#xx:3 of @ERd) C(#xx:3 of @aa:8) C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) ------ ------ ------ ------ ------ ------ ------ ------ ------ ------ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Normal @@aa I -- HNZ VC 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 4 4 5 6 1 4 4 5 6 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 692 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 5. Bit Manipulation Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 C (#xx:3 of Rd8)C C (#xx:3 of @ERd)C C (#xx:3 of @aa:8)C C (#xx:3 of @aa:16)C C (#xx:3 of @aa:32)C C [ (#xx:3 of Rd8)]C C [ (#xx:3 of @ERd)]C C [ (#xx:3 of @aa:8)]C C [ (#xx:3 of @aa:16)]C C [ (#xx:3 of @aa:32)]C C (#xx:3 of Rd8)C C (#xx:3 of @ERd)C C (#xx:3 of @aa:8)C C (#xx:3 of @aa:16)C C (#xx:3 of @aa:32)C C [ (#xx:3 of Rd8)]C C [ (#xx:3 of @ERd)]C C [ (#xx:3 of @aa:8)]C C [ (#xx:3 of @aa:16)]C C [ (#xx:3 of @aa:32)]C C (#xx:3 of Rd8)C C (#xx:3 of @ERd)C C (#xx:3 of @aa:8)C C (#xx:3 of @aa:16)C C (#xx:3 of @aa:32)C C [ (#xx:3 of Rd8)]C C [ (#xx:3 of @ERd)]C C [ (#xx:3 of @aa:8)]C C [ (#xx:3 of @aa:16)]C C [ (#xx:3 of @aa:32)]C ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- Normal @@aa I -- HNZ VC 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 693 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 6. Branch Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,ERn) @(d,PC) Bcc BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 if condition is true then PCPC+d else next; Always -- Normal @@aa @ERn Branch Condition I HNZ VC ---------- ------------ 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 Never ------------ ------------ CZ=0 ------------ ------------ CZ=1 ------------ ------------ C=0 ------------ ------------ C=1 ------------ ------------ Z=0 ------------ ------------ Z=1 ------------ ------------ V=0 ------------ ------------ V=1 ------------ ------------ N=0 ------------ ------------ N=1 ------------ ------------ NV=0 ------------ ------------ NV=1 ------------ ------------ Z(NV)=0 -- -- -- -- -- -- ------------ Z(NV)=1 -- -- -- -- -- -- ------------ 694 Advanced Mnemonic Operation @aa Size #xx Rn -- Table A.1 Instruction Set (cont) 6. Branch Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) JMP JMP @ERn JMP @aa:24 JMP @@aa:8 -- -- -- -- -- -- -- -- -- 2 4 2 2 4 2 4 2 PCERn PCaa:24 PC@aa:8 PC@-SP,PCPC+d:8 PC@-SP,PCPC+d:16 PC@-SP,PCERn PC@-SP,PCaa:24 PC@-SP,PC@aa:8 2 PC@SP+ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 4 3 4 3 4 4 4 Normal @@aa I -- HNZ VC 2 3 5 4 5 4 5 6 5 BSR BSR d:8 BSR d:16 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 RTS RTS 695 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 7. System Control Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) TRAPA TRAPA #xx:2 -- PC@-SP,CCR@-SP, EXR@-SP, 1 -- -- -- -- -- 7 [9] 8 [9] RTE RTE -- SLEEP LDC SLEEP LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR -- B B B B W W W W W W W W W W W W ------------ Normal @@aa I -- HNZ VC 5 [9] 2 1 ------------ 2 1 ------------ 1 3 ------------ 3 4 ------------ 4 6 ------------ 6 4 ------------ 4 4 ------------ 4 5 ------------ 5 696 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 7. System Control Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) STC STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 B B W W W W W W W W W W W W B B B B B B -- 2 4 2 4 2 4 2 2 4 4 6 6 10 10 4 4 6 6 8 8 CCRRd8 EXRRd8 CCR@ERd EXR@ERd CCR@(d:16,ERd) EXR@(d:16,ERd) CCR@(d:32,ERd) EXR@(d:32,ERd) ERd32-2ERd32,CCR@ERd ERd32-2ERd32,EXR@ERd CCR@aa:16 EXR@aa:16 CCR@aa:32 EXR@aa:32 CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR 2 PCPC+2 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ Normal @@aa I -- HNZ VC 1 1 3 3 4 4 6 6 4 4 4 4 5 5 1 ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR ------------ 2 1 ORC ORC #xx:8,CCR ORC #xx:8,EXR ------------ 2 1 XORC XORC #xx:8,CCR XORC #xx:8,EXR ------------ ------------ 2 1 NOP NOP 697 Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn Table A.1 Instruction Set (cont) 8. Block Transfer Instructions Addressing Mode and Instruction Length (Bytes) @-ERn/@ERn+ Condition Code No. of States*1 @(d,PC) EEPMOV EEPMOV.B -- 4 if R4L0 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4L-1R4L Until R4L=0 else next; -- ---------- 4+2n*2 EEPMOV.W -- 4 if R40 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4-1R4 Until R4=0 else next; ------------ 4+2n*2 Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value set in R4L or R4. [1] 7 states when the number of saved/restored registers is 2, 9 states when 3, and 11 states when 4. [2] Cannot be used with the H8S/2138 Series and H8S/2134 Series. [3] Set to 1 when there is a carry from or borrow to bit 11; otherwise cleared to 0. [4] Set to 1 when there is a carry from or borrow to bit 27; otherwise cleared to 0. [5] If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. [6] Set to 1 if the divisor is negative; otherwise cleared to 0. [7] Set to 1 if the divisor is zero; otherwise cleared to 0. [8] Set to 1 if the quotient is negative; otherwise cleared to 0. [9] When EXR is valid, the number of states is increased by 1. 698 Normal @@aa I -- HNZ VC Advanced @(d,ERn) Mnemonic @ERn Operation @aa Size #xx Rn A.2 Instruction Mnemonic Size 1st Byte 8 rd 8 rd rd rd 0 erd IMM IMM 9 9 A A B B B rd E rd IMM rs rd rd rd 0 erd IMM 6 6 0 ers 0 erd 0 IMM 4 1 0 6 IMM rd 0 7 6 6 abs abs 0 IMM 0 7 6 0 IMM 0 7 6 0 IMM 0 0 7 0 0 disp 0 0 disp 1 0 disp disp 0 IMM 0 IMM 0 erd abs 1 3 IMM 6 rs 6 F rd 6 9 6 A 1 6 1 6 C E A A 0 8 1 8 rs IMM 9 0 erd 8 0 erd 0 0 erd 1 ers 0 erd 1 rs 1 rs 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 IMM 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte 10th Byte B B W W L L L L L B B B B W W L L B B B B B B B -- -- -- -- ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) Instruction Format Table A.2 ADD ADDS Instruction Codes Instruction Codes ADDX AND ANDC BAND Bcc 699 700 Instruction Mnemonic Size 1st Byte 4 2 8 2 disp 3 disp 4 disp 5 disp 6 disp 7 disp 8 disp 9 disp A disp B disp C disp D disp E disp F 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 3 8 4 8 5 8 6 8 7 8 8 8 9 8 A 8 B 8 C 8 D 8 E 8 F 8 0 disp 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 disp 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Bcc Instruction Format Table A.2 10th Byte Instruction Codes (cont) Instruction Mnemonic Size 1st Byte 7 2 rd 0 7 2 0 0 7 2 0 7 2 0 IMM 0 abs 0 IMM 2 abs 0 IMM 7 8 8 rd 0 6 2 rn 0 0 6 2 rn 0 6 2 rn 0 abs rn abs 2 6 8 8 rd 0 7 6 0 0 7 6 abs 1 IMM 0 7 6 1 IMM 0 6 abs 1 IMM 7 0 0 rd 0 7 7 0 0 7 abs 7 1 IMM 0 7 7 1 IMM 0 7 abs 1 IMM 7 0 0 rd 0 7 4 4 7 0 0 1 IMM 1 IMM abs abs 0 0 7 4 1 IMM 0 7 4 1 IMM 0 1 IMM 1 IMM 0 IMM D F A 1 3 rn 0 erd abs 1 3 1 IMM 0 erd abs 1 3 1 IMM 0 erd abs 1 3 1 IMM 0 erd abs 1 3 A 2 D F A A 6 C E A A 7 C E A A 4 C E A A abs 0 erd 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 0 IMM 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte B B B B B B B B B B B B B B B B B B B B B B B B B BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIOR #xx:3,Rd BILD #xx:3,Rd BIAND #xx:3,Rd BCLR Instruction Format 10th Byte Table A.2 Instruction Codes (cont) 701 702 Instruction Mnemonic Size 1st Byte 6 7 rd 0 6 7 0 0 6 7 0 6 7 0 1 IMM abs 1 IMM 7 abs 1 IMM 6 8 8 rd 0 7 5 0 0 7 5 0 7 5 1 IMM 0 abs 1 IMM 5 abs 1 IMM 7 0 0 rd 0 7 7 0 0 7 7 abs 0 IMM 0 7 7 0 IMM 0 7 abs 0 IMM 7 0 0 rd 0 7 1 0 0 7 abs 1 0 IMM 0 7 1 0 IMM 0 1 abs 0 IMM 7 8 8 rd 0 6 1 1 abs abs 6 8 8 rn rn 0 0 6 1 rn 0 6 1 rn 0 0 IMM 0 IMM 1 IMM 1 IMM D F A 1 3 1 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd abs 1 3 A 5 C E A A 7 C E A A 1 D F A A 1 D F A A abs 0 erd 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 1 IMM 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte B B B B B B B B B B B B B B B B B B B B B B B B B BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BNOT #xx:3,Rd BLD #xx:3,Rd BIXOR #xx:3,Rd BIST Instruction Format Table A.2 10th Byte Instruction Codes (cont) Instruction Mnemonic Size 1st Byte 7 4 rd 0 7 4 0 0 7 4 0 7 4 0 IMM 0 abs 0 IMM 4 abs 0 IMM 7 0 0 rd 0 7 0 0 0 7 0 0 7 0 0 IMM 0 abs 0 IMM 0 abs 0 IMM 7 8 8 rd 0 6 0 rn 0 0 6 0 abs rn 0 6 0 rn 0 rn abs 0 6 8 8 disp 0 0 rd 0 6 7 7 abs abs 0 IMM 6 8 8 rd 0 7 7 0 0 rd 0 erd 0 6 3 rn 0 3 3 0 IMM 0 IMM abs abs 0 0 7 3 0 IMM 0 7 3 0 IMM 0 0 IMM 0 0 6 7 0 IMM 0 6 7 0 IMM 0 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn disp 0 IMM 0 IMM C E A 1 3 0 IMM 0 erd abs 1 3 rn 0 erd abs 1 3 A 0 D F A A 0 D F A A 5 C 7 D F A A 3 C E A A 3 C abs 0 erd 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 0 IMM 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte B B B B B B B B B B B B B B B -- -- B B B B B B B B B B B B BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:16 BST BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST #xx:3,Rd BST #xx:3,Rd BSR d:8 BSET #xx:3,Rd BOR Instruction Format 10th Byte Table A.2 Instruction Codes (cont) 703 704 Instruction Mnemonic Size 1st Byte 7 E 6 3 rn 0 6 3 rn 6 3 rn 0 0 abs abs 0 0 rd 0 7 5 0 0 7 5 0 7 5 0 IMM 0 abs 0 IMM 5 abs 0 IMM 7 0 0 0 IMM A 1 3 0 IMM 0 erd abs 1 3 A 5 C E A A 6 6 7 7 7 6 6 Cannot be used with the H8S/2138 Series and H8S/2134 Series. A rd C rs rd rd rd 0 erd IMM IMM 2 rs 2 1 ers 0 erd 0 rd rd rd rd rd 0 erd 0 erd 0 5 5 0 rd 0 erd C 4 5 5 9 9 8 8 F F 1 3 rs rs rd 0 erd 0 0 5 D 7 F D D rs rs 5 D 9 D A F F F A B B B B 1 1 1 3 B B 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 IMM abs 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte B B B B B B B B -- B B W W L L B B B W W L L B W B W -- -- BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC CMP CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS DIVXS.W Rs,ERd DIVXU DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W DIVXU.B Rs,Rd DIVXS.B Rs,Rd DEC.B Rd DAS Rd DAA Rd CMP.B #xx:8,Rd BXOR #xx:3,Rd BTST Instruction Format Table A.2 10th Byte Instruction Codes (cont) Instruction Mnemonic Size 1st Byte 1 7 D rd 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern 0 abs abs IMM 4 1 0 7 rs rs 0 6 9 9 F F 8 7 6 1 0 4 1 6 6 6 8 D D B B 0 ers 0 ers 0 ers 0 ers 7 0 ers 0 ers 0 0 ers 0 0 6 6 6 1 0 1 0 1 0 ers 0 0 0 0 0 0 0 0 0 0 abs 4 abs 6 6 B B disp disp 2 2 0 0 disp disp 0 1 4 4 4 4 4 4 4 4 IMM F 5 7 0 5 D 7 F 0 ern 7 7 7 A B B B B 9 A B D E F 7 1 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte W L W L B W W L L -- -- -- -- -- -- B B B B W W W W W W W W W W EXTS.W Rd EXTS.L ERd EXTU EXTU.L ERd INC INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP JMP @aa:24 JMP @@aa:8 JSR JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC #xx:8,CCR JSR @ERn JMP @ERn INC.B Rd EXTU.W Rd EXTS Instruction Format 10th Byte Table A.2 Instruction Codes (cont) 705 706 Instruction Mnemonic Size 1st Byte 0 1 4 0 6 B 2 2 7 7 7 0 ern+3 0 ern+2 0 ern+1 0 abs B D D D 6 6 6 6 1 0 0 0 abs 4 1 2 3 1 1 1 1 0 0 0 0 Cannot be used with the H8S/2138 Series and H8S/2134 Series. 0 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte W W L L L L L -- B rd C rs rd rd rd 0 6 A 2 rd rd disp disp 0 ers 0 ers 0 ers 0 ers abs 0 rd rd rs rs 0 6 A A rs rs disp disp abs 2 1 erd 1 erd 0 erd 1 erd abs 8 rs rs rd rd rd rd 0 6 B disp 2 rd disp IMM A 0 rs 0 ers 0 ers 0 ers abs abs abs 8 E 8 C rd A A 8 E 8 C rs A A 9 D 9 F 8 B B B B B B B B B B B B B B B W W W W W 7 6 6 0 7 6 6 3 6 7 6 6 6 6 2 6 7 6 6 0 F IMM LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACL MAC MOV MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.B #xx:8,Rd MAC @ERn+,@ERm+ LDMAC ERs,MACH LDM.L @SP+, (ERn-ERn+1) LDC Instruction Format Table A.2 10th Byte Instruction Codes (cont) Instruction Mnemonic Size 1st Byte 6 D rd rd rd rs rs 0 6 B A rs rs rs rs 0 erd IMM abs abs disp disp abs abs B 0 2 1 erd 1 erd 0 erd 1 erd 8 A 0 1 ers 0 erd 0 0 6 9 F 8 0 6 B D B 0 2 1 erd 0 ers 1 erd 0 ers 0 erd 0 6 B disp A 0 ers disp 0 erd B 9 F 8 D B B 0 erd 0 ers 0 erd abs abs 0 ers 2 0 ers 0 erd disp 0 erd disp 6 7 6 6 6 6 6 7 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ers 0 erd B 9 F 8 D B B A F 1 1 1 1 1 1 1 1 1 1 1 1 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ers 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte W W W W W W W W W L L L L L L L L L L MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)* L MOV.L ERs,@-ERd L L L B B B 1 C C rs rs 1 0 2 W B W 5 5 0 0 0 0 rd 0 erd 5 5 0 2 rs rs rd 0 erd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.W Rs,ERd MULXU MULXU.W Rs,ERd MULXU.B Rs,Rd MULXS.B Rs,Rd MOV Instruction Format 10th Byte Table A.2 Instruction Codes (cont) 1 erd 0 ers 8 A 0 ers 0 ers abs abs Cannot be used with the H8S/2138 Series and H8S/2134 Series. 707 708 Instruction Mnemonic Size 1st Byte 1 7 8 rd rd 0 erd 0 rd rd 0 erd IMM rs rd rd rd 0 erd IMM 6 4 0 ers 0 erd 0 IMM 4 1 rn 0 rn 0 rd rd rd rd 0 erd 0 erd 6 D F 0 ern 6 D 7 0 ern 7 0 F 0 8 C 9 D B F 0 4 IMM IMM 4 rs 4 F 9 B 0 0 1 3 7 7 0 7 7 7 rd 4 9 4 A 1 4 1 D 1 D 1 2 2 2 2 2 2 1 1 0 1 1 1 C 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte B W L -- B W L B B W W L L B B W L W L B B W W L L NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOT.W Rd NOT.L ERd OR OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,EXR POP POP.L ERn PUSH PUSH.L ERn ROTL ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd ROTL.B Rd PUSH.W Rn POP.W Rn ORC #xx:8,CCR OR.B #xx:8,Rd NOT.B Rd NOP NEG Instruction Format Table A.2 10th Byte Instruction Codes (cont) Instruction Mnemonic Size 1st Byte 1 3 8 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 C 9 D B F 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte B B W W L L B B W W L L B B W W L L -- -- B B W W L L ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTS SHAL SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd SHAL.B Rd RTS RTE ROTXR.B Rd ROTXL.B Rd ROTR Instruction Format 10th Byte Table A.2 Instruction Codes (cont) 709 710 Instruction Mnemonic Size 1st Byte 1 1 8 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 1 0 1 0 1 0 4 1 6 7 7 6 4 6 6 6 9 F F 8 8 D D 6 9 erd 1 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte B B W W L L B B W W L L B B W W L L -- B B W W SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP STC STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W STC.W CCR,@-ERd W W STC.W EXR,@-ERd STC.B CCR,Rd SLEEP SHLR.B Rd SHLL.B Rd SHAR Instruction Format Table A.2 10th Byte Instruction Codes (cont) Instruction Mnemonic Size 1st Byte 0 1 4 0 6 B 8 0 0 0 0 0 ern 0 ern 0 ern abs abs abs 8 A A F F F B B B D D D 6 6 6 6 6 6 1 0 1 0 0 0 4 4 4 1 2 3 1 1 1 1 1 1 0 0 0 0 0 0 Cannot be used with the H8S/2138 Series and H8S/2134 Series. abs 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 9th Byte W W W W L L L L L B 1 8 rs rd rd rd 0 erd IMM IMM 3 rs 3 1 ers 0 erd 0 8 9 IMM rs rd 0 7 B 0 0 erd C E 00 IMM IMM rs rd rd rd 0 erd 0 6 5 IMM 0 ers 0 erd IMM 5 rs 5 F 0 erd 0 erd 0 erd 9 9 A A B B B rd E 1 7 rd 5 9 5 A 1 7 1 7 1 1 1 1 B 1 0 5 D 1 7 6 7 0 W W L L L L L B B B -- B B W W L L STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACL,ERd SUB SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #2,ERd SUBS #4,ERd SUBX SUBX Rs,Rd TAS TRAPA XOR XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XOR.B #xx:8,Rd TRAPA #x:2 TAS @ERd SUBX #xx:8,Rd SUBS #1,ERd SUB.B Rs,Rd STMAC MACH,ERd STM.L (ERn-ERn+1), @-SP STC Instruction Format 10th Byte Table A.2 Instruction Codes (cont) 711 712 Instruction Mnemonic Size 1st byte 0 IMM 4 IMM 1 0 5 0 1 5 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B XORC #xx:8,CCR XORC #xx:8,EXR XORC Instruction Format Table A.2 10th byte Note: * Bit 7 of the 4th byte of the MOV.L ERs, @ (d:32, ERd) instruction can be either 0 or 1. Legend IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits, indicating an 8-bit or 16-bit register. rs, rd, and rn correspond to operand formats Rs, Rd, and Rn, respectively.) Register field (3 bits, indicating an address register or 32-bit register. ers, erd, ern, and erm correspond to operand formats ERs, ERd, ERn, and ERm, respectively.) Instruction Codes (cont) The correspondence between register fields and general registers is shown in the following table. Address Registers 32-Bit Registers 16-Bit Register Register Field 0000 0001 * * * 0111 1000 1001 * * * 1111 R0 R1 * * * R7 E0 E1 * * * E7 0000 0001 * * * 0111 1000 1001 * * * 1111 R0H R1H * * * R7H R0L R1L * * * R7L General Register Register Field General Register 8-Bit Register Register Field 000 001 * * * 111 ER0 ER1 * * * ER7 General Register Instruction when most significant bit of BH is 0. Instruction code: AH AL BH BL Instruction when most significant bit of BH is 1. 1st byte 2nd byte A.3 Table A.3 AL AH 0 NOP XORC ADD MOV CMP SUBX SUB ADDX XOR AND Table A.3 (2) MOV.B 3 4 BRA BRN BHI BLS BMI BGE BSR MOV Table A.3 (3) DIVXU OR MOV MOV Table A.3 (2) XOR AND BST Table A.3 (2) Table A.3 (2) EEPMOV BTST RTS BSR JMP RTE TRAPA Table A.3 (2) MULXU BCLR BPL DIVXU BNOT BCS BVS BNE BVC MULXU BSET 7 8 ADD ADDX CMP SUBX OR XOR AND MOV 9 A B C D E F Note: * Cannot be used with the H8S/2138 Series and H8S/2134 Series. BIST BXOR BAND BOR BLD BIXOR BIAND BIOR BILD BCC BEQ 5 6 BLT BGT JSR ANDC Table A.3 (2) OR ORC LDC 1 2 LDC Table STC * * A.3 (2) STMAC LDMAC Table Table Table A.3 (2) A.3 (2) A.3 (2) Table A.3 (2) Table A.3 (2) Table A.3 (2) Table A.3 (2) 0 1 2 3 B C D E A 5 9 6 8 4 7 F Table A.3 (2) Table A.3 (2) Operation Code Map Table A.3 shows the operation code map. Operation Code Map (1) BLE 713 714 1st byte AH AL BH BL 2nd byte BH 0 1 2 3 4 LDC STC ADD INC ADDS MOV SHLL SHLL SHLR ROTXL ROTXR NOT EXTU NEG EXTU ROTXR ROTR NEG SUB DEC DEC SUBS CMP BRN BHI BLS BCC * MOVFPE OR XOR XOR OR AND AND Table A.3 (4) SUB SUB MOV CMP CMP Table A.3 (4) ADD ADD BCS BNE BEQ BVC MOV BVS BPL MOV BMI BGE * MOVTPE BLT BGT DEC ROTXL ROTL SHLR SHAR SHLR ROTXL ROTXR NOT DEC SUBS DAS BRA MOV MOV MOV SHLL SHAL SHAL SHAR ROTL ROTR EXTS INC INC * MAC SLEEP * CLRMAC Table A.3 (3) Table A.3 (3) STM A LDM 6 9 C MOV INC ADDS DAA 5 8 B 7 D 01 0A 0B 0F 10 11 12 13 17 1A 1B 1F 58 6A 79 7A E TAS F Table A.3 Instruction code: AH AL Table A.3 (3) INC SHAL SHAR ROTL ROTR EXTS Operation Code Map (2) DEC BLE Note: * Cannot be used with the H8S/2138 Series and H8S/2134 Series. Instruction code: AH AL BH BL CH CL DH DL Table A.3 1st byte 2nd byte 3rd byte 4th byte Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. CL AH AL BH BL CH 0 1 2 3 4 5 6 7 8 9 A B C D MULXS DIVXS DIVXS OR XOR AND BTST BTST BSET BNOT BCLR BCLR BTST BTST BSET BNOT BCLR BCLR BNOT BSET BNOT BSET MULXS E F 01C05 01D05 01F06 7Cr06*1 7Cr07*1 7Dr06*1 7Dr07*1 7Eaa6*2 7Eaa7*2 7Faa6*2 7Faa7*2 Notes: 1. r is the register specification field. 2. aa is the absolute address specification. BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST Operation Code Map (3) 715 716 Instruction code: AH AL BH BL CH CL DH DL EH EL FH FL 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte EL AHALBHBLCHCLDHDLEH Table A.3 Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. 0 4 5 6 7 8 9 A B C BTST 6A10aaaa7* 6A18aaaa6* BSET 6A18aaaa7* BNOT BCLR BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 1 2 3 D E F Operation Code Map (4) 6A10aaaa6* Instruction code: AH AL BH BL CH CL DH DL EH EL FH 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte FL 7th byte GH GL 8th byte HH HL Indicates case where MSB of HH is 0. Indicates case where MSB of HH is 1. GL AHALBHBL ... FHFLGH 0 4 5 6 7 BTST 1 2 3 8 9 A B C D E F 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BSET 6A38aaaaaaaa7* Note: * aa is the absolute address specification. BNOT BCLR BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST A.4 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8S/2000 CPU. Table A.5 shows the number of instruction fetch, data read/write, and other cycles occurring in each instruction, and table A.4 shows the number of states required per cycle according to the bus size. The number of states required for execution of an instruction can be calculated from these two tables as follows: Number of states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples of Calculation of Number of States Required for Execution Examples: Advanced mode, stack located in external address space, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 8-bit bus width. 1. BSET #0,@FFFFC7:8 From table A.5, I = L = 2 and J = K = M = N = 0 From table A.4, SI = 8 and SL = 2 Number of states = 2 x 8 + 2 x 2 = 20 2. JSR @@30 From table A.5, I = J = K = 2 and L = M = N = 0 From table A.4, SI = SJ= SK = 8 Number of states = 2 x 8 + 2 x 8 + 2 x 8 = 48 717 Table A.4 Number of States per Cycle Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 2-State Access 4 3-State Access 6 + 2m 16-Bit Bus* 2-State Access 2 3-State Access 3+m Cycle Instruction fetch SI Branch address fetch SJ Stack operation SK Byte data access SL Word data access SM Internal operation SN On-Chip Memory 1 8-Bit Bus 4 16-Bit Bus 2 2 4 1 1 1 2 4 1 3+m 6 + 2m 1 1 1 Legend: m: Number of wait states inserted into external device access Note: Cannot be used in the H8S/2138 Series and H8S/2134 Series. 718 Table A.5 Number of Cycles per Instruction Instruction Fetch I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 (BHS d:8) (BLO d:8) 2 2 2 2 2 2 2 2 2 2 1 1 1 1 Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDX ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:8 BRN d:8 BHI d:8 BLS d:8 BCC d:8 BCS d:8 BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 (BT d:8) (BF d:8) 719 Table A.5 Number of Cycles per Instruction (cont) Instruction Fetch I 2 2 (BT d:16) (BF d:16) 2 2 2 2 (BHS d:16) (BLO d:16) 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic Bcc BGT d:8 BLE d:8 BRA d:16 BRN d:16 BHI d:16 BLS d:16 BCC d:16 BCS d:16 BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 720 Table A.5 Number of Cycles per Instruction (cont) Instruction Fetch I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 721 Table A.5 Number of Cycles per Instruction (cont) Instruction Fetch I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 1 1 1 1 1 2 2 2 2 1 2 1 2 1 1 2 2 2 2 2 2 2 2 1 1 1 1 Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 Normal Advanced BSR d:16 Normal Advanced BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 722 Table A.5 Number of Cycles per Instruction (cont) Instruction Fetch I 1 2 2 3 4 1 1 1 1 Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 Normal Advanced Cannot be used with the H8S/2138 Series and H8S/2134 Series. 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1 1 1 1 2 2 2 2 1 2 1 1 1 2n+2 * 2n+2 * 2 11 19 11 19 2 723 Table A.5 Number of Cycles per Instruction (cont) Instruction Fetch I Normal Advanced 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 4 6 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Branch Address Read J Stack Operation K 1 2 1 2 1 2 1 1 Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic JSR JSR @ERn JSR @aa:24 Normal Advanced JSR @@aa:8 Normal Advanced LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs, MACH LDMAC ERs, MACL Cannot be used with the H8S/2138 Series and H8S/2134 Series. MAC MOV MAC @ERn+, @ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd 1 1 1 2 4 1 1 2 1 1 1 1 1 1 1 724 Table A.5 Number of Cycles per Instruction (cont) Instruction Fetch I 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Branch Address Read J Stack Operation K Byte Data Access L 1 1 1 1 1 1 1 1 1 Word Data Access M Internal Operation N Instruction Mnemonic MOV MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 725 Table A.5 Number of Cycles per Instruction (cont) Instruction Fetch I Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd Cannot be used with the H8S/2138 Series and H8S/2134 Series. 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 2 1 2 11 19 11 19 1 1 1 1 726 Table A.5 Number of Cycles per Instruction (cont) Instruction Fetch I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Normal Advanced 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2/3 * 1 2 1 Instruction Mnemonic ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS RTE RTS Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 1 1 1 SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd 727 Table A.5 Number of Cycles per Instruction (cont) Instruction Fetch I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 1 2 1 3 1 4 6 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L (ERn-ERn+1),@-SP STM.L (ERn-ERn+2),@-SP STM.L (ERn-ERn+3),@-SP SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd 728 Table A.5 Number of Cycles per Instruction (cont) Instruction Fetch I 1 1 1 2 Normal Advanced 2 2 1 1 2 1 3 2 1 2 1 2 2/3 * 2/3 * 1 Instruction Mnemonic SUBS SUBX SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS TRAPA TAS @ERd TRAPA #x:2 Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 2 2 2 1 XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1. 2 when EXR is invalid, 3 when valid. 2. When n bytes of data are transferred. 729 A.5 Bus States During Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 Internal operation, 2 state 3 R:W EA 4 5 6 7 8 End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend: R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Start address of instruction following executing instruction Effective address Vector address 730 Figure A.1 shows timing waveforms for the address bus and the 5' and :5 signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. o Address bus RD WR High level R:W 2nd Internal operation R:W EA Fetching 3rd byte Fetching 4th byte of instruction of instruction Fetching 1st byte Fetching 2nd byte of branch of branch instruction instruction Figure A.1 Address Bus, 5' and :5 Timing (8-Bit Bus, Three-State Access, No Wait States) 731 Table A.6 Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd Instruction Execution Cycle 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 3rd R:W NEXT R:W NEXT 2 3 4 5 6 7 8 9 ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd R:W 2nd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT AND.L #xx:32,ERd R:W 2nd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT BAND #xx:3,@ERd R:W 2nd BAND #xx:3,@aa:8 R:W 2nd BAND #xx:3, @aa:16 BAND #xx:3, @aa:32 BRA d:8 BRN d:8 BHI d:8 BLS d:8 R:W 2nd R:W 2nd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT (BT d:8) R:W NEXT R:W EA (BF d:8) R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA BCC d:8 (BHS d:8) R:W NEXT R:W EA BCS d:8 (BLO d:8) R:W NEXT R:W EA BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA 732 Table A.6 Instruction BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 Instruction Execution Cycle (cont) 1 2 3 4 5 6 7 8 9 R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state BRA d:16 (BT d:16) R:W 2nd BRN d:16 (BF d:16) R:W 2nd BHI d:16 R:W 2nd BLS d:16 R:W 2nd BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 R:W 2nd R:W 2nd R:W 2nd BEQ d:16 R:W 2nd BVC d:16 R:W 2nd BVS d:16 R:W 2nd BPL d:16 R:W 2nd BMI d:16 R:W 2nd BGE d:16 R:W 2nd 733 Table A.6 Instruction BLT d:16 Instruction Execution Cycle (cont) 1 R:W 2nd 2 3 4 5 6 7 8 9 R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state R:W EA Internal operation, 1 state BGT d:16 R:W 2nd BLE d:16 R:W 2nd BCLR #xx:3,Rd R:W NEXT R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA BCLR #xx:3,@ERd R:W 2nd BCLR #xx:3,@aa:8 R:W 2nd BCLR #xx:3, @aa:16 BCLR #xx:3, @aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BIAND #xx:3, @aa:16 BIAND #xx:3, @aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W:M NEXT R:W:M NEXT R:B: EA R:W:M NEXT BILD #xx:3,@aa:16 R:W 2nd 734 Table A.6 Instruction Instruction Execution Cycle (cont) 1 2 R:W 3rd 3 R:W 4th 4 R:B EA 5 R:W:M NEXT 6 7 8 9 BILD #xx:3,@aa:32 R:W 2nd BIOR #xx:3,Rd BIOR #xx:3,@ERd R:W NEXT R:W 2nd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT BIOR #xx:3,@aa:8 R:W 2nd BIOR #xx:3,@aa:16 R:W 2nd BIOR #xx:3,@aa:32 R:W 2nd BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 R:W NEXT R:W 2nd R:W 2nd R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA BIST #xx:3,@aa:16 R:W 2nd BIST #xx:3,@aa:32 R:W 2nd BIXOR #xx:3,Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BIXOR #xx:3, @aa:16 BIXOR #xx:3, @aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT BLD #xx:3,@aa:16 R:W 2nd BLD #xx:3,@aa:32 R:W 2nd BNOT #xx:3,Rd R:W NEXT BNOT #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA 735 Table A.6 Instruction Instruction Execution Cycle (cont) 1 2 3 4 W:B EA W:B EA W:B EA 5 6 7 8 9 BNOT #xx:3,@aa:8 R:W 2nd BNOT #xx:3, @aa:16 BNOT #xx:3, @aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W NEXT BOR #xx:3,@aa:16 R:W 2nd BOR #xx:3,@aa:32 R:W 2nd BSET #xx:3,Rd R:W NEXT BSET #xx:3,@ERd R:W 2nd BSET #xx:3,@aa:8 R:W 2nd BSET #xx:3, @aa:16 BSET #xx:3, @aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT 736 Table A.6 Instruction BSR d:8 BSR d:16 Instruction Execution Cycle (cont) 1 2 3 W:W:M Stack (H) 4 W:W Stack (L) W:W:M Stack (H) W:W Stack (L) 5 6 7 8 9 Advanced R:W NEXT R:W EA Advanced R:W 2nd R:W EA Internal operation, 1 state BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 R:W NEXT R:W 2nd R:W 2nd R:B:M EA R:W:M NEXT R:B:M EA R:W:M NEXT R:W 3rd R:W 3rd W:B EA W:B EA W:B EA W:B EA BST #xx:3,@aa:16 R:W 2nd BST #xx:3,@aa:32 R:W 2nd BTST #xx:3,Rd R:W NEXT R:B:M EA R:W:M NEXT R:W 4th R:B:M EA R:W:M NEXT BTST #xx:3,@ERd R:W 2nd BTST #xx:3,@aa:8 R:W 2nd BTST #xx:3, @aa:16 BTST #xx:3, @aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT BXOR #xx:3,@ERd R:W 2nd BXOR #xx:3,@aa:8 R:W 2nd BXOR #xx:3, @aa:16 BXOR #xx:3, @aa:32 CLRMAC R:W 2nd R:W 2nd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W 4th R:W:M NEXT R:B EA R:W:M NEXT Cannot be used in the H8S/2138 Series and H8S/2134 Series 737 Table A.6 Instruction CMP.B #xx:8,Rd CMP.B Rs,Rd Instruction Execution Cycle (cont) 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 3rd R:W NEXT R:W NEXT 2 3 4 5 6 7 8 9 CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd R:W 2nd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W EA R:W 2nd R:W EA Internal operation, 1 state R:W aa:8 R:W EA Internal operation, 1 state W:W Stack (L) W:W:M Stack (H) W:W:M Stack (H) W:W Stack (L) W:W Stack (L) R:W EA R:B EAs* R:B EAs* 1 R:B EAd* R:B EAd* 1 R:B EAs* R:B EAs* 2 W:B EAd* R:W NEXT W:B EAd* R:W NEXT 2 2 1 1 2 2 Repeated n times * JMP Advanced R:W NEXT R:W:M @@aa:8 aa:8 JSR @ERn Advanced R:W NEXT R:W EA W:W:M Stack (H) JSR Advanced R:W 2nd @aa:24 R:W EA Internal operation, 1 state R:W aa:8 JSR Advanced R:W NEXT R:W:M @@aa:8 aa:8 738 Table A.6 Instruction LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR Instruction Execution Cycle (cont) 1 R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W EA R:W NEXT R:W EA R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W NEXT R:W EA R:W 4th R:W 4th R:W 5th R:W 5th R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT 2 3 4 5 6 7 8 9 LDC@(d:16,ERs), CCR LDC@(d:16,ERs), EXR LDC@(d:32,ERs), CCR LDC@(d:32,ERs), EXR LDC @ERs+,CCR R:W EA R:W NEXT Internal operation, 1 state R:W EA R:W NEXT Internal operation, 1 state R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:W:M NEXT R:W NEXT R:W EA R:W NEXT R:W EA R:W 4th R:W 4th R:W NEXT R:W EA R:W NEXT R:W EA R:W Stack (L) 3 * R:W Stack (L) 3 * R:W Stack (L) 3 * LDC @ERs+,EXR R:W 2nd LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W:M Internal operation, Stack (H) 3 1 state * R:W:M Internal operation, Stack (H) 3 1 state * R:W:M Internal operation, Stack (H) 3 1 state * R:W 2nd R:W 2nd LDMAC ERs,MACH Cannot be used in the H8S/2138 Series and H8S/2134 Series LDMAC ERs,MACL MAC @ERn+, @ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs), Rd R:W NEXT R:W NEXT R:W NEXT R:B EA R:W 2nd R:W NEXT R:B EA 739 Table A.6 Instruction MOV.B @(d:32,ERs),Rd Instruction Execution Cycle (cont) 1 R:W 2nd 2 R:W 3rd 3 R:W 4th 4 5 6 7 8 9 R:W NEXT R:B EA R:B EA MOV.B @ERs+,Rd R:W NEXT Internal operation, 1 state MOV.B @aa:8,Rd R:W NEXT R:B EA R:W NEXT R:B EA R:W 3rd R:W NEXT R:B EA MOV.B @aa:16,Rd R:W 2nd MOV.B @aa:32,Rd R:W 2nd MOV.B Rs,@ERd MOV.B Rs, @(d:16,ERd) MOV.B Rs, @(d:32,ERd) MOV.B Rs,@-ERd R:W NEXT W:B EA R:W 2nd R:W 2nd R:W NEXT W:B EA R:W 3rd R:W 4th R:W NEXT W:B EA W:B EA R:W NEXT Internal operation, 1 state R:W NEXT W:B EA R:W NEXT W:B EA R:W 3rd R:W NEXT R:W NEXT W:B EA MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 R:W 2nd MOV.B Rs,@aa:32 R:W 2nd MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd R:W 2nd R:W NEXT R:W NEXT R:W EA R:W 2nd R:W 2nd R:W NEXT R:W EA R:W 3rd R:W 4th R:W NEXT R:W EA R:W EA MOV.W @ERs+,Rd R:W NEXT Internal operation, 1 state MOV.W @aa:16,Rd R:W 2nd MOV.W @aa:32,Rd R:W 2nd MOV.W Rs,@ERd MOV.W Rs, @(d:16,ERd) MOV.W Rs, @(d:32,ERd) R:W NEXT R:W EA R:W 3rd R:W NEXT R:B EA R:W NEXT W:W EA R:W 2nd R:W 2nd R:W NEXT W:W EA R:W 3rd R:W 4th R:W NEXT W:W EA W:W EA MOV.W Rs,@-ERd R:W NEXT Internal operation, 1 state MOV.W Rs,@aa:16 R:W 2nd MOV.W Rs,@aa:32 R:W 2nd R:W NEXT W:W EA R:W 3rd R:W NEXT W:W EA 740 Table A.6 Instruction Instruction Execution Cycle (cont) 1 2 R:W 3rd 3 R:W NEXT 4 5 6 7 8 9 MOV.L #xx:32,ERd R:W 2nd MOV.L ERs,ERd R:W NEXT MOV.L @ERs,ERd R:W 2nd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:32, ERd R:W 2nd R:W 2nd R:W 2nd R:W:M NEXT R:W:M EA R:W EA+2 R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2 R:W:M 3rd R:W:M 4th R:W 5th R:W:M NEXT R:W NEXT R:W:M EA R:W EA+2 R:W:M EA R:W EA+2 Internal operation, 1 state R:W 2nd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2 R:W:M 3rd R:W 4th R:W:M NEXT R:W NEXT R:W:M EA R:W EA+2 MOV.L ERs,@ERd R:W 2nd MOV.L ERs, @(d:16,ERd) MOV.L ERs, @(d:32,ERd) R:W 2nd R:W 2nd W:W:M EA W:W EA+2 R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2 R:W:M 3rd R:W:M 4th R:W 5th R:W:M NEXT R:W NEXT W:W:M EA W:W EA+2 MOV.L ERs,@-ERd R:W 2nd W:W:M EA W:W EA+2 Internal operation, 1 state MOV.L ERs, @aa:16 MOV.L ERs, @aa:32 MOVFPE @aa:16, Rd MOVTPE Rs, @aa:16 MULXS.B Rs,Rd R:W 2nd R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2 R:W:M 3rd R:W 4th R:W NEXT W:W:M EA W:W EA+2 Cannot be used in the H8S/2138 Series and H8S/2134 Series R:W 2nd R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states MULXS.W Rs,ERd R:W 2nd MULXU.B Rs,Rd R:W NEXT Internal operation, 11 states MULXU.W Rs,ERd R:W NEXT Internal operation, 19 states NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 741 Table A.6 Instruction NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd Instruction Execution Cycle (cont) 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT 2 3 4 5 6 7 8 9 OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn R:W EA R:W NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT R:W:M EA R:W EA+2 Internal operation, 1 state POP.L ERn PUSH.W Rn W:W EA R:W NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT W:W:M EA W:W EA+2 Internal operation, 1 state PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 742 Table A.6 Instruction Instruction Execution Cycle (cont) 1 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W Stack (EXR) R:W Stack (H) R:W Stack (L) R:W Stack (L) R:W * Internal operation, 1 state 4 4 2 3 4 5 6 7 8 9 ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS Advanced R:W NEXT R:W:M Stack (H) R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W * Internal operation, 1 state SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd 743 Table A.6 Instruction SLEEP Instruction Execution Cycle (cont) 1 2 3 4 5 6 7 8 9 R:W NEXT Internal operation :M R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT W:W EA R:W NEXT W:W EA R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT W:W EA R:W NEXT W:W EA R:W 4th R:W 4th R:W 5th R:W 5th R:W NEXT W:W EA R:W NEXT W:W EA STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR, @(d:16,ERd) STC EXR, @(d:16,ERd) STC CCR, @(d:32,ERd) STC EXR, @(d:32,ERd) STC CCR,@-ERd W:W EA R:W NEXT Internal operation, 1 state W:W EA R:W NEXT Internal operation, 1 state R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:W:M NEXT R:W NEXT W:W EA R:W NEXT W:W EA R:W 4th R:W 4th R:W NEXT W:W EA R:W NEXT W:W EA W:W Stack (L) 3 * W:W Stack (L) 3 * W:W Stack (L) 3 * STC EXR,@-ERd R:W 2nd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 R:W 2nd R:W 2nd R:W 2nd R:W 2nd STM.L R:W 2nd (ERn-ERn+1),@-SP STM.L R:W 2nd (ERn-ERn+2),@-SP STM.L R:W 2nd (ERn-ERn+3),@-SP W:W:M Internal operation, Stack (H) 3 1 state * W:W:M Internal operation, Stack (H) 3 1 state * W:W:M Internal operation, Stack (H) 3 1 state * STMAC MACH,ERd Cannot be used in the H8S/2138 Series and H8S/2134 Series STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 3rd R:W NEXT R:W NEXT 744 Table A.6 Instruction Instruction Execution Cycle (cont) 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:B:M EA W:B EA W:W Stack (H) W:W Stack (EXR) R:W:M VEC R:W VEC+2 R:W * Internal operation, 1 state 7 2 3 4 5 6 7 8 9 SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd W:W TRAPA Advanced R:W NEXT Internal #x:2 operation, Stack (L) 1 state XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT XOR.L #xx:32,ERd R:W 2nd XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W VEC+2 R:W * Internal operation, 1 state 5 Advanced R:W:M Reset VEC exception handling Interrupt Advanced R:W * exception handling 6 W:W Internal operation, Stack (L) 1 state W:W Stack (H) W:W Stack (EXR) R:W:M VEC R:W VEC+2 R:W * Internal operation, 1 state 7 Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. Start address after return. 5. Start address of the program. 6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. Start address of the interrupt-handling routine. 745 746 Appendix B Internal I/O Registers B.1 Addresses Bit 7 SM1 Bit 6 SM0 Bit 5 DM1 Bit 4 DM0 Bit 3 MD1 Bit 2 MD0 Bit 1 DTS Bit 0 Sz Module Name DTC Bus Width 16/32* Register Address Name H'EC00 to H'EFFF MRA SAR MRB DAR CHNE DISEL -- -- -- -- -- -- CRA CRB H'FEE4 KBCOMP IrE IrCKS2 IrCKS1 IrCKS0 KBADE KBCH2 KBCH1 KBCH0 IrDA/ expasion A/D IIC0 Interrupt controller 8 H'FEE6 H'FEE8 H'FEE9 DDCSWR SWE ICRA ICRB ICR7 ICR7 ICR7 IRQ7F SW ICR6 ICR6 ICR6 IRQ6F IE ICR5 ICR5 ICR5 IRQ5F IF ICR4 ICR4 ICR4 IRQ4F CLR3 ICR3 ICR3 ICR3 IRQ3F CLR2 ICR2 ICR2 ICR2 IRQ2F CLR1 ICR1 ICR1 ICR1 IRQ1F CLR0 ICR0 ICR0 ICR0 IRQ0F 8 8 H'FEEA ICRC H'FEEB ISR H'FEEC ISCRH H'FEED ISCRL H'FEEE DTCERA H'FEEF DTCERB H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FF80 H'FF81 DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC FLMCR1 FLMCR2 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 SWDTE CMF A23 A15 A7 FWE FLER DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 -- A22 A14 A6 SWE -- -- A21 A13 A5 -- -- -- A20 A12 A4 -- -- -- A19 A11 A3 EV -- -- A18 A10 A2 PV -- -- A17 A9 A1 E ESU BIE A16 A8 -- P PSU FLASH 8 Interrupt controller 8 DTC 8 748 Register Address Name H'FF82 PCSR EBR1 H'FF83 SYSCR2 EBR2 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 SBYCR Bit 7 -- -- KWUL1 EB7 SSBY Bit 6 -- -- KWUL0 EB6 STS2 LSON Bit 5 -- -- P6PUE EB5 STS1 NESEL Bit 4 -- -- -- EB4 STS0 EXCLE Bit 3 -- -- SDE EB3 -- -- Bit 2 PWCKB -- CS4E EB2 SCK2 -- Bit 1 PWCKA EB9/-- CS3E EB1 SCK1 -- Bit 0 -- EB8/-- HI12E EB0 SCK0 -- MSTP8 MSTP0 CKS0 SCP Module Name PWM FLASH HIF FLASH SYSTEM Bus Width 8 8 8 8 8 LPWRCR DTON MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTPCRL MSTP7 SMR1 ICCR1 C/$ ICE MSTP6 CHR IEIC MSTP5 PE MST MSTP4 O/( TRS MSTP3 STOP ACKE MSTP2 MP BBSY MSTP1 CKS1 IRIC SCI1 IIC1 SCI1 8 H'FF89 BRR1 ICSR1 ESTP TIE STOP RIE IRTR TE AASX RE AL MPIE AAS TEIE ADZ CKE1 ACKB CKE0 8 IIC1 SCI1 8 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E SCR1 TDR1 SSR1 RDR1 SCMR1 ICDR1 SARX1 TDRE RDRF ORER FER PER TEND MPB MPBT -- ICDR7 SVAX6 MLS SVA6 ICIAE ICFA -- ICDR6 SVAX5 WAIT SVA5 ICIBE ICFB -- ICDR5 SVAX4 CKS2 SVA4 ICICE ICFC -- ICDR4 SVAX3 CKS1 SVA3 ICIDE ICFD SDIR ICDR3 SVAX2 CKS0 SVA2 OCIAE OCFA SINV ICDR2 SVAX1 BC2 SVA1 OCIBE OCFB -- ICDR1 SVAX0 BC1 SVA0 OVIE OVF SMIF ICDR0 FSX BC0 FS -- CCLRA FRT 16 IIC1 8 H'FF8F ICMR1 SAR1 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 TIER TCSR FRCH FRCL OCRAH OCRBH H'FF95 OCRAL OCRBL H'FF96 H'FF97 H'FF98 TCR TOCR ICRAH OCRARH IEDGA IEDGB IEDGC IEDGD OCRS BUFEA OEA BUFEB OEB CKS1 OLVLA CKS0 OLVLB ICRDMS OCRAMS ICRS H'FF99 ICRAL OCRARL H'FF9A ICRBH OCRAFH 749 Register Address Name H'FF9B ICRBL OCRAFL H'FF9C ICRCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name FRT Bus Width 16 OCRDMH 0 H'FF9D ICRCL OCRDML H'FF9E H'FF9F H'FFA0 ICRDH ICRDL SMR2 DADRAH DACR H'FFA1 BRR2 DADRAL H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 SCR2 TDR2 SSR2 RDR2 SCMR2 DADRBH DACNTH H'FFA7 DADRBL DACNTL H'FFA8 TCSR0 TCNT0 (write) H'FFA9 TCNT0 (read) OVF DA5 -- DA13 TDRE DA5 TIE C/$ DA13 TEST 0 0 0 0 0 0 0 CHR DA12 PWME PE DA11 -- O/( DA10 -- STOP DA9 OEB MP DA8 OEA CKS1 DA7 OS CKS0 DA6 CKS SCI2 PWMX 8 SCI2 DA4 RIE DA3 TE DA2 RE DA1 MPIE DA0 TEIE CFS CKE1 -- CKE0 PWMX SCI2 8 8 RDRF ORER FER PER TEND MPB MPBT -- DA12 -- DA11 -- DA10 SDIR DA9 SINV DA8 -- DA7 SMIF DA6 PWMX 8 DA4 DA3 DA2 DA1 DA0 CFS -- REGS REGS CKS0 WDT0 16 WT/,7 TME RSTS RST/10, CKS2 CKS1 H'FFAC P1PCR H'FFAD P2PCR H'FFAE P3PCR H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR P17DR P27DR P16DR P26DR P15DR P25DR P14DR P24DR P13DR P23DR P12DR P22DR P11DR P21DR P10DR P20DR Ports 8 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR P37DR P47DR P36DR P46DR P35DR P45DR P34DR P44DR P33DR P43DR P32DR P42DR P31DR P41DR P30DR P40DR 750 Register Address Name H'FFB8 H'FFB9 P5DDR P6DDR Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 Bit 1 Bit 0 Module Name Ports Bus Width 8 P52DDR P51DDR P50DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR -- P67DR -- P77PIN -- -- P66DR -- P65DR -- P64DR -- P63DR P52DR P62DR P51DR P61DR P50DR P60DR H'FFBA P5DR H'FFBB P6DR H'FFBD P8DDR H'FFBE P7PIN H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR0 TCR1 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR P76PIN P86DR P75PIN P85DR P74PIN P84DR P73PIN P83DR P72PIN P82DR P71PIN P81DR P70PIN P80DR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR P97DR IRQ7E IICS CS2E EXPE ICIS1 RAMS CMIEB CMIEB CMFB CMFB P96DR IRQ6E IICX1 IOSE -- ICIS0 RAM0 CMIEA CMIEA CMFA CMFA P95DR IRQ5E IICX0 INTM1 -- P94DR IRQ4E IICE INTM0 -- P93DR IRQ3E FLSHE XRST -- P92DR IRQ2E -- NMIEG -- P91DR IRQ1E ICKS1 HIE MDS1 IOS1 WC1 CKS1 CKS1 OS1 OS1 P90DR IRQ0E ICKS0 RAME MDS0 IOS0 WC0 CKS0 CKS0 OS0 OS0 Bus controller TMR0, TMR1 8 Interrupt controller System 8 8 BRSTRM BRSTS1 BRSTS0 -- ABW OVIE OVIE OVF OVF AST CCLR1 CCLR1 ADTE -- WMS1 CCLR0 CCLR0 OS3 OS3 WMS0 CKS2 CKS2 OS2 OS2 16 H'FFCA TCSR0 H'FFCB TCSR1 H'FFCC TCORA0 H'FFCD TCORA1 H'FFCE TCORB0 H'FFCF TCORB1 H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 TCNT0 TCNT1 PWOERB OE15 PWOERA OE7 PWDPRB OS15 PWDPRA OS7 PWSL PWDR0 to PWDR15 SMR0 ICCR0 C/$ ICE PWCKE OE14 OE6 OS14 OS6 PWCKS OE13 OE5 OS13 OS5 -- OE12 OE4 OS12 OS4 -- OE11 OE3 OS11 OS3 RS3 OE10 OE2 OS10 OS2 RS2 OE9 OE1 OS9 OS1 RS1 OE8 OE0 OS8 OS0 RS0 PWM 8 H'FFD8 CHR IEIC PE MST O/( TRS STOP ACKE MP BBSY CKS1 IRIC CKS0 SCP SCI0 IIC0 SCI0 8 H'FFD9 BRR0 ICSR0 ESTP STOP IRTR AASX AL AAS ADZ ACKB IIC0 751 Register Address Name H'FFDA SCR0 H'FFDB TDR0 H'FFDC SSR0 H'FFDD RDR0 H'FFDE SCMR0 ICDR0 SARX0 H'FFDF ICMR0 SAR0 H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCNT1 (write) H'FFEB TCNT1 (read) H'FFF0 HICR TCRX TCRY H'FFF1 KMIMR TCSRX TCSRY H'FFF2 KMPCR TICRR TCORAY H'FFF3 H'FFF4 TICRF TCORBY IDR1 TCNTX TCNTY Bit 7 TIE TDRE -- ICDR7 SVAX6 MLS SVA6 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGS1 OVF Bit 6 RIE RDRF -- ICDR6 SVAX5 WAIT SVA5 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/,7 Bit 5 TE ORER -- ICDR5 SVAX4 CKS2 SVA4 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- TME Bit 4 RE FER -- ICDR4 SVAX3 CKS1 SVA3 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- PSS Bit 3 MPIE PER SDIR ICDR3 SVAX2 CKS0 SVA2 AD5 -- AD5 -- AD5 -- AD5 -- CKS -- Bit 2 TEIE TEND SINV ICDR2 SVAX1 BC2 SVA1 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- Bit 1 CKE1 MPB -- ICDR1 SVAX0 BC1 SVA0 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- CKS1 Bit 0 CKE0 MPBT SMIF ICDR0 FSX BC0 FS AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- CKS0 Module Name SCI0 Bus Width 8 IIC0 A/D 8 H'FFEA TCSR1 RST/10, CKS2 WDT1 16 -- CMIEB CMIEB -- CMIEA CMIEA -- OVIE OVIE -- CCLR1 CCLR1 -- CCLR0 CCLR0 IBFIE2 CKS2 CKS2 IBFIE1 CKS1 CKS1 FGA20E CKS0 CKS0 HIF TMRX TMRY Interrupt controller TMRX TMRY Ports TMRX TMRY TMRX TMRY 8 KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 CMFB CMFB CMFA CMFA OVF OVF ICF ICIE OS3 OS3 OS2 OS2 OS1 OS1 OS0 OS0 KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 HIF TMRX TMRY 752 Register Address Name H'FFF5 ODR1 TCORC TISR H'FFF6 STR1 TCORAX H'FFF7 H'FFF8 H'FFF9 H'FFFA TCORBX DADR0 DADR1 DACR Bit 7 ODR7 Bit 6 ODR6 Bit 5 ODR5 Bit 4 ODR4 Bit 3 ODR3 Bit 2 ODR2 Bit 1 ODR1 Bit 0 ODR0 Module Name HIF TMRX Bus Width 8 -- DBU -- DBU -- DBU -- DBU -- C/' -- DBU -- IBF IS OBF TMRY HIF TMRX D/A DAOE1 IDR7 DAOE0 IDR6 DAE IDR5 -- IDR4 ICST ODR4 CBOE DBU -- IDR3 HFINV ODR3 HOINV C/' -- IDR2 VFINV ODR2 VOINV DBU -- IDR1 HIINV ODR1 CLOINV IBF -- IDR0 VIINV ODR0 CBOINV OBF HIF Timer connection HIF Timer connection HIF Timer connection H'FFFC IDR2 TCONRI H'FFFD ODR2 SIMOD1 SIMOD0 SCONE ODR7 ODR6 VOE DBU ODR5 CLOE DBU TCONRO HOE H'FFFE STR2 TCONRS H'FFFF SEDGR DBU TMRX/Y ISGENE HOMOD1 HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0 VEDG HEDG CEDG HFEDG VFEDG PREQF IHI IVI 753 B.2 Register Selection Conditions H8S/2138 Series Register Selection Conditions RAME = 1 in SYSCR H8S/2134 Series Register Selection Conditions -- Module Name DTC Lower Register Address Name H'EC00 to H'EFFF MRA SAR MRB DAR CRA CRB H'FEE4 KBCOMP No conditions No conditions IrDA/ expansion A/D IIC0 Interrupt controller H'FEE6 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FF80 H'FF81 H'FF82 DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC FLMCR1 FLMCR2 PCSR EBR1 MSTP4 = 0 No conditions -- No conditions No conditions -- DTC No conditions No conditions Interrupt controller FLSHE = 1 in STCR FLSHE = 1 in STCR Flash memory FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR PWM Flash memory HIF Flash memory System H'FF83 SYSCR2 EBR2 H'FF84 H'FF85 H'FF86 H'FF87 SBYCR LPWRCR MSTPCRH MSTPCRL 754 Lower Register Address Name H'FF88 SMR1 ICCR1 H'FF89 BRR1 ICSR1 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E SCR1 TDR1 SSR1 RDR1 SCMR1 ICDR1 SARX1 H'FF8F ICMR1 SAR1 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 TIER TCSR FRCH FRCL OCRAH OCRBH H'FF95 OCRAL OCRBL H'FF96 H'FF97 H'FF98 TCR TOCR ICRAH OCRARH H'FF99 ICRAL OCRARL H'FF9A ICRBH OCRAFH H'FF9B ICRBL OCRAFL H'FF9C ICRCH OCRDMH H'FF9D ICRCL OCRDML H8S/2138 Series Register Selection Conditions MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR MSTP6 = 0 H8S/2134 Series Register Selection Conditions MSTP6 = 0, IICE = 0 in STCR -- MSTP6 = 0, IICE = 0 in STCR -- MSTP6 = 0 Module Name SCI1 IIC1 SCI1 IIC1 SCI1 MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR ICE = 1 in ICCR1 ICE = 0 in ICCR1 ICE = 1 in ICCR1 ICE = 0 in ICCR1 MSTP13 = 0 MSTP6 = 0, IICE = 0 in STCR -- IIC1 MSTP13 = 0 FRT 755 Lower Register Address Name H'FF9E H'FF9F H'FFA0 ICRDH ICRDL SMR2 DADRAH H8S/2138 Series Register Selection Conditions MSTP13 = 0 H8S/2134 Series Register Selection Conditions MSTP13 = 0 Module Name FRT MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/ DADRB REGS = 1 in DACNT/ DADRB MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/ DADRB MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/ DADRB REGS = 1 in DACNT/ DADRB MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/ DADRB SCI2 PWMX DACR H'FFA1 BRR2 DADRAL SCI2 PWMX H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 SCR2 TDR2 SSR2 RDR2 SCMR2 DADRBH MSTP5 = 0 MSTP5 = 0 SCI2 MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/ DADRB REGS = 1 in DACNT/ DADRB REGS = 0 in DACNT/ DADRB REGS = 1 in DACNT/ DADRB No conditions MSTP5 = 0, IICE = 0 in STCR MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/ DADRB REGS = 1 in DACNT/ DADRB REGS = 0 in DACNT/ DADRB REGS = 1 in DACNT/ DADRB No conditions WDT0 PWMX DACNTH H'FFA7 DADRBL DACNTL H'FFA8 TCSR0 TCNT0 (write) H'FFA9 H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 TCNT0 (read) P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR No conditions No conditions Ports 756 Lower Register Address Name H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBD H'FFBE H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR P8DDR P7PIN P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR0 TCR1 TCSR0 TCSR1 TCORA0 TCORA1 TCORB0 TCORB1 TCNT0 TCNT1 PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR0 to PWDR15 H8S/2138 Series Register Selection Conditions No conditions H8S/2134 Series Register Selection Conditions No conditions Module Name Ports No conditions No conditions No conditions No conditions Interrupt controller System Bus controller MSTP12 = 0 MSTP12 = 0 TMR0, TMR1 No conditions -- PWM MSTP11 = 0 757 Lower Register Address Name H'FFD8 SMR0 ICCR0 H'FFD9 BRR0 ICSR0 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE SCR0 TDR0 SSR0 RDR0 SCMR0 ICDR0 SARX0 H'FFDF ICMR0 SAR0 H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR1 TCNT1 (write) H'FFEB H'FFF0 TCNT1 (read) HICR TCRX TCRY H8S/2138 Series Register Selection Conditions MSTP7 = 0, IICE = 0 in STCR MSTP4 = 0, IICE = 1 in STCR MSTP7 = 0, IICE = 0 in STCR MSTP4 = 0, IICE = 1 in STCR MSTP7 = 0 H8S/2134 Series Register Selection Conditions MSTP7 = 0, IICE = 0 in STCR -- MSTP7 = 0, IICE = 0 in STCR -- MSTP7 = 0 Module Name SCI0 IIC0 SCI0 IIC0 SCI0 MSTP7 = 0, IICE = 0 in STCR MSTP4 = 0, IICE = 1 in STCR ICE = 1 in ICCR0 ICE = 0 in ICCR0 ICE = 1 in ICCR0 ICE = 0 in ICCR0 MSTP9 = 0 MSTP7 = 0, IICE = 0 in STCR -- IIC0 MSTP9 = 0 A/D No conditions No conditions WDT1 MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR -- TMRX/Y = 0 in-- TCONRS TMRX/Y = 1 inMSTP8 = 0, HIE = 0 in SYSCR TCONRS HIF TMRX TMRY 758 Lower Register Address Name H'FFF1 KMIMR TCSRX TCSRY H'FFF2 KMPCR TICRR TCORAY H'FFF3 TICRF TCORBY H'FFF4 IDR1 TCNTX TCNTY H'FFF5 ODR1 TCORC TISR H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFC STR1 TCORAX TCORBX DADR0 DADR1 DACR IDR2 TCONRI H'FFFD ODR2 TCONRO H'FFFE STR2 TCONRS H'FFFF SEDGR H8S/2138 Series Register Selection Conditions MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR H8S/2134 Series Register Selection Conditions MSTP2 = 0, HIE = 1 in SYSCR Module Name Interrupt controller TMRX TMRY Ports TMRX TMRY TMRX TMRY HIF TMRX TMRY HIF TMRX TMRY HIF TMRX TMRX/Y = 0 in-- TCONRS TMRX/Y = 1 inMSTP8 = 0, HIE = 0 in SYSCR TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR TMRX/Y = 0 in-- TCONRS TMRX/Y = 1 inMSTP8 = 0, HIE = 0 in SYSCR TCONRS MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in-- TCONRS TMRX/Y = 1 inMSTP8 = 0, HIE = 0 in SYSCR TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR -- TMRX/Y = 0 in TCONRS TMRX/Y = 1 inMSTP8 = 0, HIE = 0 in SYSCR TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS -- TMRX/Y = 1 inMSTP8 = 0, HIE = 0 in SYSCR TCONRS MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS MSTP10 = 0 MSTP10 = 0 -- D/A MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR -- HIF Timer connection HIF Timer connection HIF Timer connection 759 B.3 Functions Register name Address to which the register is mapped Name of on-chip supporting module D/A Converter Register acronym DACR--D/A Control Register H'FFFA Bit numbers Bit 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial bit values Initial value Read/Write Names of the bits. Dashes (--) indicate reserved bits. D/A enabled DAOE1 DAOE0 DAE * 0 1 1 0 0 1 1 * Conversion result Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversion enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled Possible types of access R W Read only Write only 0 0 1 Full name of bit R/W Read and write Descriptions of bit settings D/A output enable 0 0 1 Analog output DA0 disabled Channel 0 D/A conversion enabled. Analog output DA0 enabled D/A output enable 1 0 1 Analog output DA1 disabled Channel 1 D/A conversion enabled. Analog output DA1 enabled 760 MRA--DTC Mode Register A Bit Initial value Read/Write 7 SM1 -- 6 SM0 -- 5 DM1 -- 4 DM0 -- H'EC00-H'EFFF 3 MD1 -- 2 MD0 -- 1 DTS -- 0 Sz -- DTC Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC data transfer size 0 Byte-size transfer 1 Word-size transfer DTC transfer mode select 0 Destination side is repeat area or block area 1 Source side is repeat area or block area DTC mode 0 1 0 Normal mode 1 Repeat mode 0 Block transfer mode 1-- Destination address mode 0 -- DAR is fixed 1 0 DAR is incremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) 1 DAR is decremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) Source address mode 0 -- SAR is fixed 1 0 SAR is incremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) 1 SAR is decremented after a transfer (by 1 when Sz = 0; by 2 when Sz = 1) 761 MRB--DTC Mode Register B Bit Initial value Read/Write 7 CHNE -- 6 DISEL -- 5 -- -- 4 -- -- H'EC00-H'EFFF 3 -- -- 2 -- -- 1 -- -- 0 -- -- DTC Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC interrupt select 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After a data transfer ends, the CPU interrupt is enabled DTC chain transfer enable 0 End of DTC data transfer 1 DTC chain transfer SAR--DTC Source Address Register Bit Initial value Read/Write 23 22 21 20 19 H'EC00-H'EFFF --------4 3 2 1 DTC 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined -- -- -- -- -- -- -- -- -- -- Specifies DTC transfer data source address DAR--DTC Destination Address Register Bit Initial value Read/Write 23 22 21 20 19 H'EC00-H'EFFF --------4 3 2 1 DTC 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined -- -- -- -- -- -- -- -- -- -- Specifies DTC transfer data destination address 762 CRA--DTC Transfer Count Register A Bit Initial value Read/Write 15 14 13 12 11 10 9 8 H'EC00-H'EFFF 7 6 5 4 3 2 1 DTC 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CRAH CRAL Specifies the number of DTC data transfers CRB--DTC Transfer Count Register B Bit Initial value Read/Write 15 14 13 12 11 10 9 8 H'EC00-H'EFFF 7 6 5 4 3 2 1 DTC 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Specifies the number of DTC block data transfers 763 KBCOMP--Keyboard Comparator Control Register Bit Initial value Read/Write 7 IrE 0 R/W 6 IrCKS2 0 R/W 5 IrCKS1 0 R/W 4 IrCKS0 0 R/W 3 H'FEE4 2 KBCH2 0 R/W 1 KBCH1 0 R/W IrDA/COMP 0 KBCH0 0 R/W KBADE 0 R/W Keyboard comparator control Bit 2 Bit 1 Bit 0 Bit 3 A/D converter A/D converter KBADE KBCH2 KBCH1 KBCH0 channel 6 input channel 7 input 0 1 -- 0 -- 0 1 1 0 1 -- 0 1 0 1 0 1 0 1 IrDA Clock select 2 to 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 IrDA enable 0 The TxD2/IrTxD and RxD2/IrRxD pins function as TxD2 and RxD2 1 The TxD2/IrTxD and RxD2/IrRxD pins function as IrTxD and IrRxD B x 3/16 (3/16 of the bit rate) o/2 o/4 o/8 o/16 o/32 o/64 o/128 AN6 CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 AN7 Undefined 764 DDCSWR--DDC Switch Register Bit Initial value Read/Write 7 SWE 0 R/W 6 SW 0 R/W 5 IE 0 R/W 4 IF 0 R/(W)*1 3 CLR3 1 W*2 H'FEE6 2 CLR2 1 W*2 1 CLR1 1 W*2 0 CLR0 1 W*2 IIC0 IIC clear bits Bit 3 Bit 2 Bit 1 Bit 0 CLR3 CLR2 CLR1 CLR0 0 0 1 -- 0 1 1 -- -- -- 0 1 0 1 -- Description Setting prohibited Setting prohibited IIC0 internal latch cleared IIC1 internal latch cleared IIC0 and IIC1 internal latches cleared Invalid setting DDC mode switch interrupt flag 0 No interrupt is requested when automatic format switching is executed [Clearing condition] When 0 is written in IF after reading IF = 1 An interrupt is requested when automatic format switching is executed [Setting condition] When a falling edge is detected on the SCL pin when SWE = 1 1 DDC mode switch interrupt enable bit 0 1 Interrupt when automatic format switching is executed is disabled Interrupt when automatic format switching is executed is enabled DDC mode switch 0 IIC channel 0 is used with the I2C bus format [Clearing conditions] * When 0 is written by software * When a falling edge is detected on the SCL pin when SWE = 1 IIC channel 0 is used in formatless mode [Setting condition] When 1 is written in SW after reading SW = 0 1 DDC mode switch enable 0 1 Automatic switching of IIC channel 0 from formatless mode to I2C bus format is disabled Automatic switching of IIC channel 0 from formatless mode to I2C bus format is enabled Notes: 1. Only 0 can be written, to clear the flag. 2. Always read as 1. 765 ICRA--Interrupt Control Register A ICRB--Interrupt Control Register B ICRC--Interrupt Control Register C Bit Initial value Read/Write 7 ICR7 0 R/W 6 ICR6 0 R/W 5 ICR5 0 R/W 4 H'FEE8 H'FEE9 H'FEEA 3 ICR3 0 R/W 2 ICR2 0 R/W Interrupt Controller Interrupt Controller Interrupt Controller 1 ICR1 0 R/W 0 ICR0 0 R/W ICR4 0 R/W Interrupt control level 0 1 Corresponding interrupt source is control level 0 (non-priority) Corresponding interrupt source is control level 1 (priority) Correspondence between Interrupt Sources and ICR Settings Register ICRA ICRB Bits 7 IRQ0 6 IRQ1 5 IRQ2 IRQ3 -- 4 IRQ4 IRQ5 -- 3 IRQ6 IRQ7 2 DTC 1 0 Watchdog Watchdog timer 0 timer 1 A/D Freeconverter running timer 8-bit timer 8-bit timer 8-bit timer HIF channel 0 channel 1 channels X, Y -- -- ICRC SCI SCI SCI IIC IIC -- channel 0 channel 1 channel 2 channel 0 channel 1 (option) (option) 766 ISR--IRQ Status Register Bit Initial value Read/Write 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 H'FEEB 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* Interrupt Controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ4F 0 R/(W)* IRQ7 to IRQ0 flags 0 [Clearing conditions] * Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF * When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high * When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) [Setting conditions] * When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) * When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) * When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) * When a falling or rising edge occurs in IRQn input while both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) Note: * Only 0 can be written, to clear the flag. 1 767 ISCRH--IRQ Sense Control Register H ISCRL--IRQ Sense Control Register L ISCRH H'FEEC H'FEED Interrupt Controller Interrupt Controller Bit Initial value Read/Write 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA IRQ7 to IRQ4 sense control A and B ISCRL Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA IRQ3 to IRQ0 sense control A and B ISCRH bits 7-0 ISCRL bits 7-0 IRQ7SCB- IRQ0SCB 0 IRQ7SCA- IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ7-IRQ0 input at low level Interrupt request generated at falling edge of IRQ7-IRQ0 input Interrupt request generated at rising edge of IRQ7-IRQ0 input Interrupt request generated at both falling and rising edges of IRQ7-IRQ0 input 768 DTCER--DTC Enable Register Bit Initial value Read/Write 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 H'FEEE to H'FEF2 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTC DTCE4 0 R/W DTCE0 0 R/W DTC activation enable 0 DTC activation by interrupt is disabled [Clearing conditions] * When data transfer ends with the DISEL bit set to 1 * When the specified number of transfers end DTC activation by interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 DTVECR--DTC Vector Register Bit Initial value Read/Write 7 0 R/(W)* 6 0 R/W 5 0 R/W 4 0 H'FEF3 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W DTC SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 R/W Sets vector number for DTC software activation DTC software activation enable 0 DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended DTC software activation is enabled [Holding conditions] * When data transfer ends with the DISEL bit set to 1 * When the specified number of transfers end * During software-activated deta transfer 1 Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. 769 ABRKCR--Address Break Control Register Bit Initial value Read/Write 7 CMF 0 R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FEF4 3 -- 0 -- 2 -- 0 -- Interrupt Controller 1 -- 0 -- 0 BIE 0 R/W Break interrupt enable 0 1 Condition match flag 0 1 [Clearing condition] When address break interrupt exception handling is executed [Setting condition] When address set by BARA-BARC is prefetched while BIE = 1 Address break disabled Address break enabled 770 BARA--Break Address Register A BARB--Break Address Register B BARC--Break Address Register C Bit BARA Initial value Read/Write 7 A23 0 R/W 6 A22 0 R/W 5 A21 0 R/W 4 A20 0 R/W H'FEF5 H'FEF6 H'FEF7 3 A19 0 R/W 2 A18 0 R/W Interrupt Controller Interrupt Controller Interrupt Controller 1 A17 0 R/W 0 A16 0 R/W Specifies address (bits 23-16) at which address break is to be generated Bit BARB Initial value Read/Write 7 A15 0 R/W 6 A14 0 R/W 5 A13 0 R/W 4 A12 0 R/W 3 A11 0 R/W 2 A10 0 R/W 1 A9 0 R/W 0 A8 0 R/W Specifies address (bits 15-8) at which address break is to be generated Bit BARC Initial value Read/Write 7 A7 0 R/W 6 A6 0 R/W 5 A5 0 R/W 4 A4 0 R/W 3 A3 0 R/W 2 A2 0 R/W 1 A1 0 R/W 0 -- 0 -- Specifies address (bits 7-1) at which address break is to be generated 771 FLMCR1--Flash Memory Control Register 1 Bit Initial value Read/Write 7 FWE 1 R 6 SWE 0 R/W 5 -- 0 -- 4 -- 0 -- H'FF80 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W Flash Memory 0 P 0 R/W Program 0 1 Program mode cleared Transition to program mode [Setting condition] When SWE = 1, and PSU = 1 Erase 0 1 Erase mode cleared Transition to erase mode [Setting condition] When SWE = 1, and ESU = 1 Program-verify 0 1 Program-verify mode cleared Transition to program-verify mode [Setting condition] When SWE = 1 Erase-verify 0 1 Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When SWE = 1 Software write enable 0 1 Writes disabled Writes enabled Reserved bit 772 FLMCR2--Flash Memory Control Register 2 Bit Initial value Read/Write 7 FLER 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FF81 3 -- 0 -- 2 -- 0 -- 1 ESU 0 R/W Flash Memory 0 PSU 0 R/W Program setup 0 1 Program setup cleared Program setup [Setting condition] When SWE = 1 Erase setup 0 1 Erase setup cleared Erase setup [Setting condition] When SWE = 1 Flash memory error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 21.8.3, Error Protection 1 773 PCSR--Peripheral Clock Select Register Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FF82 3 -- 0 -- 2 0 R/W 1 0 R/W 0 -- 0 -- PWM PWCKB PWCKA PWM clock select PWSL Bit 7 0 1 Bit 6 -- 0 1 PCSR Bit 2 -- -- 0 1 Bit 1 -- -- 0 1 0 1 Description Clock input is disabled o (system clock) is selected o/2 is selected o/4 is selected o/8 is selected o/16 is selected PWCKE PWCKS PWCKB PWCKA 774 SYSCR2--System Control Register 2 Bit Initial value Read/Write 7 KWUL1 0 R/W 6 KWUL0 0 R/W 5 P6PUE 0 R/W 4 -- 0 -- H'FF83 3 SDE 0 R/W 2 CS4E 0 R/W 1 CS3E 0 R/W 0 HI12E 0 R/W HIF Host interface enable 0 1 Host interface function disabled Host interface function enabled Reserved bits Shutdown enable 0 1 Host interface pin shutdown function disabled Host interface pin shutdown function enabled Port 6 input pull-up extra 0 1 Standard current specification is selected for port 6 MOS input pull-up function Current-limit specification is selected for port 6 MOS input pull-up function Key wakeup level 1 and 0 0 1 0 1 0 1 Standard input level is selected as port 6 input level Input level 1 is selected as port 6 input level Input level 2 is selected as port 6 input level Input level 3 is selected as port 6 input level 775 EBR1--Erase Block Register 1 EBR2--Erase Block Register 2 Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FF82 H'FF83 3 -- 0 -- 2 -- 0 -- 1 Flash Memory Flash Memory 0 EB8/--*2 0 R/W*1,*2 EB9/--*2 0 R/W*1,*2 Bit Initial value Read/Write Notes: 7 EB7 0 R/W*1 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W 1. In normal mode, these bits cannot be modified and are always read as 0. 2. Bits EB8 and EB9 are not present in the 64-kbyte versions; they cannot be modified and are always read as 0. Erase Blocks Block (Size) 128-kbyte versions EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) 64-kbyte versions EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) -- -- Addresses H'(00)0000-H'(00)03FF H'(00)0400-H'(00)07FF H'(00)0800-H'(00)0BFF H'(00)0C00-H'(00)0FFF H'(00)1000-H'(00)7FFF H'(00)8000-H'(00)BFFF H'(00)C000-H'(00)DFFF H'00E000-H'00FFFF H'010000-H'017FFF H'018000-H'01FFFF 776 SBYCR--Standby Control Register Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W H'FF84 3 -- 0 -- 2 SCK2 0 R/W 1 SCK1 0 R/W 0 System SCK0 0 R/W System clock select 2 to 0 0 0 0 Bus master is in high-speed mode 1 1 1 0 1 0 1 0 1 -- Medium-speed clock = o/2 Medium-speed clock = o/4 Medium-speed clock = o/8 Medium-speed clock = o/16 Medium-speed clock = o/32 -- Standby timer select 2 to 0 0 0 0 Standby time = 8192 states 1 1 1 0 1 0 1 0 1 0 1 Software standby 0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to subsleep mode on execution of SLEEP instruction in subactive mode Transition to software standby mode, subactive mode, or watch mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to watch mode or high-speed mode after execution of SLEEP instruction in subactive mode Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states* Note: * This setting must not be used in the flash memory version. 1 777 LPWRCR--Low-Power Control Register Bit Initial value Read/Write 7 DTON 0 R/W 6 LSON 0 R/W 5 NESEL 0 R/W 4 EXCLE 0 R/W H'FF85 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- System Subclock input enable 0 1 Subclock input from EXCL pin is disabled Subclock input from EXCL pin is enabled Noise elimination sampling frequency select 0 1 Low-speed on flag 0 * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode * After watch mode is cleared, a transition is made to high-speed mode * When a SLEEP instruction is executed in high-speed mode a transition is made to watch mode or subactive mode* * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode * After watch mode is cleared, a transition is made to subactive mode Sampling at o divided by 32 Sampling at o divided by 4 1 Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. Direct-transfer on flag 0 * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or software standby mode * When a SLEEP instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode 1 Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be set. 778 MSTPCRH--Module Stop Control Register H MSTPCRL--Module Stop Control Register L MSTPCRH Bit Initial value 7 0 6 0 5 1 4 1 3 1 2 1 1 1 0 1 H'FF86 H'FF87 MSTPCRL 7 1 6 1 5 1 4 1 3 1 2 1 1 1 System System 0 1 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Module stop 0 1 Module stop mode is cleared Module stop mode is set The correspondence between MSTPCR bits and on-chip supporting modules is shown below. Register MSTPCRH Bit MSTP15 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4* MSTP3* MSTP2* MSTP1* MSTP0* -- 16-bit free-running timer (FRT) 8-bit timers (TMR0, TMR1) 8-bit PWM timer (PWM), 14-bit PWM timer (PWMX) D/A converter A/D converter 8-bit timers (TMRX, TMRY), timer connection Serial communication interface 0 (SCI0) Serial communication interface 1 (SCI1) Serial communication interface 2 (SCI2) I2C bus interface (IIC) channel 0 (option) I2C bus interface (IIC) channel 1 (option) Host interface (HIF) -- -- Module MSTP14* Data transfer controller (DTC) Note: Bits 1 and 0 can be read and written but do not affect operation. * Must be set to 1 in the H8S/2134 Series. 779 SMR1--Serial Mode Register 1 SMR2--Serial Mode Register 2 SMR0--Serial Mode Register 0 Bit Initial value Read/Write 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF88 H'FFA0 H'FFD8 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI1 SCI2 SCI0 Clock select 1 and 0 0 1 0 1 0 1 Multiprocessor mode 0 1 Multiprocessor function disabled Multiprocessor format selected o clock o/4 clock o/16 clock o/64 clock Stop bit length 0 1 1 stop bit 2 stop bits Parity mode 0 1 Parity enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity Character length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Also, LSB-first/ MSB-first selection is not available. Communication mode 0 1 Asynchronous mode Synchronous mode 780 ICCR1--I C Bus Control Register 1 2 ICCR0--I C Bus Control Register 0 Bit Initial value Read/Write 7 ICE 0 R/W 6 IEIC 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 2 H'FF88 H'FFD8 3 ACKE 0 R/W 2 BBSY 0 R/W 1 IRIC 0 R/(W)* 0 SCP 1 W IIC1 IIC0 Start condition/stop condition prohibit 0 Writing 0 issues a start or stop condition, in combination with the BBSY flag Reading always returns a value of 1; writing is ignored 1 I2C bus interface interrupt request flag 0 1 Waiting for transfer, or transfer in progress Interrupt requested Note: For the clearing and setting conditions, see section 16.2.5, I2C Bus Control Register (ICCR). Bus busy 0 Bus is free [Clearing condition] When a stop condition is detected Bus is busy [Setting condition] When a start condition is detected I2C bus interface interrupt enable 0 1 I2C bus interface enable 0 I2C bus interface module disabled, with SCL and SDA signal pins set to port function SAR and SARX can be accessed I2C bus interface module enabled for transfer operations (pins SCL and SCA are driving the bus) ICMR and ICDR can be accessed Interrupts disabled Interrupts enabled 0 1 1 Acknowledge bit judgement selection The value of the acknowledge bit is ignored, and continuous transfer is performed If the acknowledge bit is 1, continuous transfer is interrupted Master/slave select (MST), transmit/receive select (TRS) 0 1 0 1 0 1 Slave receive mode Slave transmit mode Master receive mode Master transmit mode 1 Note: For details, see section 16.2.5, I2C Bus Control Register (ICCR). Note: * Only 0 can be written, to clear the flag. 781 BRR1--Bit Rate Register 1 BRR2--Bit Rate Register 2 BRR0--Bit Rate Register 0 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF89 H'FFA1 H'FFD9 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W SCI1 SCI2 SCI0 Sets the serial transmit/receive bit rate 782 ICSR1--I C Bus Status Register 1 2 ICSR0--I C Bus Status Register 0 Bit Initial value Read/Write 7 ESTP 0 R/(W)*1 6 STOP 0 R/(W)*1 5 IRTR 0 R/(W)*1 4 AASX 0 R/(W)*1 2 H'FF89 H'FFD9 3 AL 0 R/(W)*1 2 AAS 0 R/(W)*1 1 ADZ 0 R/(W)*1 0 ACKB 0 R/W IIC1 IIC0 Acknowledge bit 0 Receive mode: 0 is output at acknowledge output timing Transmit mode: indicates that the receiving device has acknowledged the data (signal is 0) Receive mode: 1 is output at acknowledge output timing Transmit mode: indicates that the receiving device has not acknowledged the data (signal is 1) 1 General call address recognition flag*2 0 1 General call address not recognized General call address recognized Slave address recognition flag*2 0 1 Slave address or general call address not recognized Slave address or general call address recognized Arbitration lost*2 0 1 Bus arbitration won Arbitration lost Second slave address recognition flag*2 0 1 I2C 0 1 Second slave address not recognized Second slave address recognized bus interface continuous transmission/reception interrupt request flag*2 Waiting for transfer, or transfer in progress Continuous transfer state Normal stop condition detection flag*2 0 1 No normal stop condition In I2C bus format slave mode: Normal stop condition detected In other modes: No meaning Error stop condition detection flag*2 0 1 No error stop condition In I2C bus format slave mode: Error stop condition detected In other modes: No meaning Notes: 1. Only 0 can be written, to clear the flag. 2. For the clearing and setting conditions, see section 16.2.6, I2C Bus Status Register (ICSR). 783 SCR1--Serial Control Register 1 SCR2--Serial Control Register 2 SCR0--Serial Control Register 0 Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF8A H'FFA2 H'FFDA 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W SCI1 SCI2 SCI0 Clock enable 1 and 0 0 0 Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode Transmit end interrupt enable 0 1 Transmit-end interrupt (TEI) request disabled Transmit-end interrupt (TEI) request enabled Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input External clock/SCK pin functions as serial clock input Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled (normal reception mode) [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Transmit interrupt enable 0 1 Transmit-data-empty interrupt (TXI) request disabled Transmit-data-empty interrupt (TXI) request enabled 1 Receive interrupt enable 0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Receive enable 0 1 Reception disabled Reception enabled Transmit enable 0 1 Transmission disabled Transmission enabled 1 784 RDR1--Receive Data Register 1 RDR2--Receive Data Register 2 RDR0--Receive Data Register 0 Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R H'FF8D H'FFA5 H'FFDD 3 0 R 2 0 R 1 0 R 0 0 R SCI1 SCI2 SCI0 Stores serial receive data TDR1--Transmit Data Register 1 TDR2--Transmit Data Register 2 TDR0--Transmit Data Register 0 Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF8B H'FFA3 H'FFDB 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W SCI1 SCI2 SCI0 Stores serial transmit data 785 SSR1--Serial Status Register 1 SSR2--Serial Status Register 2 SSR0--Serial Status Register 0 Bit Initial value Read/Write H'FF8C H'FFA4 H'FFDC 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 0 1 SCI1 SCI2 SCI0 1 MPB 0 R 0 MPBT 0 R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* Multiprocessor bit transfer Data with a 0 multi-processor bit is transmitted Data with a 1 multi-processor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Transmit end 0 [Clearing conditions] * When 0 is written in TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character 1 Parity error 0 1 [Clearing condition] When 0 is written in PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing error 0 1 [Clearing condition] When 0 is written in FER after reading FER = 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Overrun error 0 1 [Clearing condition] When 0 is written in ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] * When 0 is written in RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit data register empty 0 [Clearing conditions] * When 0 is written in TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written in TDR 1 Note: * Only 0 can be written, to clear the flag. 786 SCMR1--Serial Interface Mode Register 1 SCMR2--Serial Interface Mode Register 2 SCMR0--Serial Interface Mode Register 0 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'FF8E H'FFA6 H'FFDE 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W SCI1 SCI2 SCI0 Serial communication interface mode select 0 1 Data invert 0 1 TDR contents are transmitted without modification Receive data is stored in RDR without modification TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Normal SCI mode Setting prohibited Data transfer direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first 787 ICDR1--I C Bus Data Register 1 2 ICDR0--I C Bus Data Register 0 Bit Initial value Read/Write 7 ICDR7 -- R/W 6 ICDR6 -- R/W 5 ICDR5 -- R/W 4 ICDR4 -- R/W 2 H'FF8E H'FFDE 3 ICDR3 -- R/W 2 ICDR2 -- R/W 1 ICDR1 -- R/W 0 IIC1 IIC0 ICDR0 -- R/W ICDRR Bit Initial value Read/Write 7 -- R 6 -- R 5 -- R 4 -- R 3 -- R 2 -- R 1 -- R 0 -- R ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 ICDRS Bit Initial value Read/Write 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 -- -- 0 -- -- ICDRS7 ICDRS6 ICDRS5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0 ICDRT Bit Initial value Read/Write 7 -- W 6 -- W 5 -- W 4 -- W 3 -- W 2 -- W 1 -- W 0 -- W ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 TDRE, RDRF (internal flags) Bit Initial value Read/Write Note: For details, see section 16.2.1, I2C Bus Data Register (ICDR). -- TDRE 0 -- -- RDRF 0 -- 788 SARX1--Second Slave Address Register 1 SAR1--Slave Address Register 1 SARX0--Second Slave Address Register 0 SAR0--Slave Address Register 0 SAR Bit Initial value Read/Write 7 SVA6 0 R/W 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W H'FF8E H'FF8F H'FFDE H'FFDF IIC1 IIC1 IIC0 IIC0 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W Slave address SARX Bit Initial value Read/Write 7 SVAX6 0 R/W 6 SVAX5 0 R/W 5 SVAX4 0 R/W 4 SVAX3 0 R/W 3 SVAX2 0 R/W 2 SVAX1 0 R/W 1 Format select 0 FSX 1 R/W SVAX0 0 R/W Second slave address Format select DDCSWR Bit 6 SW 0 SAR Bit 0 FS 0 SARX Bit 0 FSX 0 1 I2C bus format * SAR and SARX slave addresses recognized I2C bus format * SAR slave address recognized * SARX slave address ignored I2C bus format * SAR slave address ignored * SARX slave address recognized Synchronous serial format * SAR and SARX slave addresses ignored Formatless mode (start/stop conditions not detected) * Acknowledge bit used Formatless mode* (start/stop conditions not detected) * No acknowledge bit Operating Mode 1 0 1 1 0 1 0 1 0 1 Note: * Do not set this mode when automatic switching to the I2C bus format is performed by means of the DDCSWR setting. 789 ICMR1--I C Bus Mode Register 1 2 ICMR0--I C Bus Mode Register 0 Bit Initial value Read/Write 7 MLS 0 R/W 6 WAIT 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W Bit counter BC2 0 2 H'FF8F H'FFDF 3 CKS0 0 R/W 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W IIC1 IIC0 BC1 0 1 BC0 0 1 0 1 0 1 0 1 1 0 1 Synchronous serial format 8 1 2 3 4 5 6 7 I2C bus format 9 2 3 4 5 6 7 8 Serial clock select IICX CKS2 0 0 CKS1 0 1 1 0 1 1 0 0 1 1 0 1 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock o/28 o/40 o/48 o/64 o/80 o/100 o/112 o/128 o/56 o/80 o/96 o/128 o/160 o/200 o/224 o/256 Wait insertion bit 0 1 Data and acknowledge bits transferred consecutively Wait inserted between data and acknowledge bits MSB-first/LSB-first select* 0 1 MSB-first LSB-first Note: * Do not set this bit to 1 when the I2C bus format is used. 790 TIER--Timer Interrupt Enable Register Bit Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W H'FF90 3 OCIAE 0 R/W 2 OCIBE 0 R/W 1 OVIE 0 R/W 0 -- 1 -- FRT Timer overflow interrupt enable 0 1 Timer overflow interrupt request (FOVI) is disabled Timer overflow interrupt request (FOVI) is enabled Output compare interrupt B enable 0 1 Output compare interrupt request B (OCIB) is disabled Output compare interrupt request B (OCIB) is enabled Output compare interrupt A enable 0 1 Output compare interrupt request A (OCIA) is disabled Output compare interrupt request A (OCIA) is enabled Input capture interrupt D enable 0 1 Input capture interrupt request D (ICID) is disabled Input capture interrupt request D (ICID) is enabled Input capture interrupt C enable 0 1 Input capture interrupt request C (ICIC) is disabled Input capture interrupt request C (ICIC) is enabled Input capture interrupt B enable 0 1 Input capture interrupt request B (ICIB) is disabled Input capture interrupt request B (ICIB) is enabled Input capture interrupt A enable 0 1 Input capture interrupt request A (ICIA) is disabled Input capture interrupt request A (ICIA) is enabled 791 TCSR--Timer Control/Status Register Bit Initial value Read/Write 7 ICFA 0 R/(W)* 6 ICFB 0 R/(W)* 5 ICFC 0 R/(W)* 4 ICFD 0 R/(W)* H'FF91 3 OCFA 0 R/(W)* 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* 0 CCLRA 0 R/W FRT Counter clear A 0 1 FRC clearing is disabled FRC is cleared at compare match A Timer overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] When FRC changes from H'FFFF to H'0000 1 Output compare flag B 0 1 [Clearing condition] Read OCFB when OCFB = 1, then write 0 in OCFB [Setting condition] When FRC = OCRB Output compare flag A 0 1 [Clearing condition] Read OCFA when OCFA = 1, then write 0 in OCFA [Setting condition] When FRC = OCRA Input capture flag D 0 1 [Clearing condition] Read ICFD when ICFD = 1, then write 0 in ICFD [Setting condition] When an input capture signal is received Input capture flag C 0 1 Input capture flag B 0 1 Input capture flag A 0 1 [Clearing condition] Read ICFA when ICFA = 1, then write 0 in ICFA [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRA [Clearing condition] Read ICFB when ICFB = 1, then write 0 in ICFB [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRB [Clearing condition] Read ICFC when ICFC = 1, then write 0 in ICFC [Setting condition] When an input capture signal is received Note: * Only 0 can be written in bits 7 to 1, to clear the flags. 792 FRC--Free-Running Counter Bit Initial value 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF92 7 0 6 0 5 0 4 0 3 0 2 0 1 0 FRT 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Count value OCRA/OCRB--Output Compare Register A/B Bit Initial value 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF94 7 1 6 1 5 1 4 1 3 1 2 1 1 1 FRT 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Constantly compared with FRC value; OCF is set when OCR = FRC 793 TCR--Timer Control Register Bit Initial value Read/Write 7 IEDGA 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W H'FF96 3 BUFEA 0 R/W 2 BUFEB 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W FRT Clock select 0 1 0 1 0 1 o/2 internal clock source o/8 internal clock source o/32 internal clock source External clock source (rising edge) Buffer enable B 0 1 ICRD is not used as a buffer register for input capture B ICRD is used as a buffer register for input capture B Buffer enable A 0 1 ICRC is not used as a buffer register for input capture A ICRC is used as a buffer register for input capture A Input edge select D 0 1 Capture on the falling edge of FTID Capture on the rising edge of FTID Input edge select C 0 1 Capture on the falling edge of FTIC Capture on the rising edge of FTIC Input edge select B 0 1 Capture on the falling edge of FTIB Capture on the rising edge of FTIB Input edge select A 0 1 Capture on the falling edge of FTIA Capture on the rising edge of FTIA 794 TOCR--Timer Output Compare Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 ICRS 0 R/W 4 OCRS 0 R/W H'FF97 3 OEA 0 R/W 2 OEB 0 R/W 1 OLVLA 0 R/W 0 OLVLB 0 R/W FRT ICRDMS OCRAMS Output level B 0 1 A 0 logic level is output for compare-match B A 1 logic level is output for compare-match B Output level A 0 1 A 0 logic level is output for compare-match A A 1 logic level is output for compare-match A Output enable B 0 1 Output compare B output disabled Output compare B output enabled Output enable A 0 1 Output compare A output disabled Output compare A output enabled Output compare register select 0 1 OCRA register selected OCRB register selected Input capture register select 0 1 ICRA, ICRB, and ICRC registers selected OCRAR, OCRAF, and OCRDM registers selected Output compare A mode select 0 1 OCRA set to normal operating mode OCRA set to operating mode using OCRAR and OCRAF Input capture D mode select 0 1 ICRD set to normal operating mode ICRD set to operating mode using OCRDM 795 OCRAR--Output Compare Register AR OCRAF--Output Compare Register AF Bit Initial value 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF98 H'FF9A 7 1 6 1 5 1 4 1 3 1 2 1 1 1 FRT FRT 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Used for OCRA operation when OCRAMS = 1 in TOCR (For details, see section 11.2.4, Output Compare Registers AR and AF (OCRAR, OCRAF).) OCRDM--Output Compare Register DM Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 H'FF9C 7 0 6 0 5 0 4 0 3 0 2 0 1 0 FRT 0 0 R R/W R/W R/W R/W R/W R/W R/W R/W Used for ICRD operation when ICRDMS = 1 in TOCR (For details, see section 11.2.5, Output Compare Register DM (OCRDM).) ICRA--Input Capture Register A ICRB--Input Capture Register B ICRC--Input Capture Register C ICRD--Input Capture Register D Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R H'FF98 H'FF9A H'FF9C H'FF9E 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R FRT FRT FRT FRT 0 0 R Stores FRC value when input capture signal is input (ICRC and ICRD can be used for buffer operation. For details, see section 11.2.3, Input Capture Registers A to D (ICRA to ICRD).) 796 DADRAH--PWM (D/A) Data Register AH DADRAL--PWM (D/A) Data Register AL DADRBH--PWM (D/A) Data Register BH DADRBL--PWM (D/A) Data Register BL DADRH Bit (CPU) Bit (data) DADRA Initial value 15 13 14 12 13 11 12 10 11 9 10 8 9 7 8 6 7 5 H'FFA0 H'FFA1 H'FFA6 H'FFA7 DADRL 6 4 5 3 4 2 3 1 2 0 1 -- PWMX PWMX PWMX PWMX 0 -- -- 1 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- DADRB Initial value DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register select (DADRB only) 0 1 DADRA and DADRB can be accessed DACR and DACNT can be accessed Carrier frequency select 0 1 Base cycle = resolution (T) x 64 DADR range is H'0401 to H'FFFD Base cycle = resolution (T) x 256 DADR range is H'0103 to H'FFFF D/A conversion data 797 DACR--PWM (D/A) Control Register Bit Initial value Read/Write 7 TEST 0 R/W 6 PWME 0 R/W 5 -- 1 -- 4 -- 1 -- H'FFA0 3 OEB 0 R/W 2 OEA 0 R/W 1 OS 0 R/W 0 PWMX CKS 0 R/W Clock select 0 1 Resolution (T) = system clock cycle time (tcyc) Resolution (T) = system clock cycle time (tcyc) x 2 Output select 0 1 Direct PWM output Inverted PWM output Output enable A 0 1 PWM channel A output (PWX0 output pin) disabled PWM channel A output (PWX0 output pin) enabled Output enable B 0 1 PWM enable 0 1 Test mode 0 1 User mode: the PWM D/A module operates normally Test mode: correct conversion results will not be obtained DACNT operates as a 14-bit up-counter DACNT halts at H'0003 PWM channel B output (PWX1 output pin) disabled PWM channel B output (PWX1 output pin) enabled 798 DACNTH--PWM (D/A) Counter H DACNTL--PWM (D/A) Counter L DACNTH Bit (CPU) Bit (counter) Initial value Read/Write 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 H'FFA6 H'FFA7 DACNTL 7 8 6 9 5 10 4 11 3 12 2 13 1 -- PWMX PWMX 0 -- -- REGS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- Register select 0 1 Up-counter DADRA and DADRB can be accessed DACR and DACNT can be accessed 799 TCSR0--Timer Control/Status Register 0 TCSR0 Bit Initial value Read/Write H'FFA8 WDT0 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 RSTS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select 2 to 0 CKS2 0 CKS1 0 1 1 0 1 CKS0 0 1 0 1 0 1 0 1 o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Clock Reset or NMI 0 1 Reserved bit Timer enable 0 1 TCNT is initialized to H'00 and halted TCNT counts NMI interrupt requested Internal reset requested Timer mode select 0 1 Overflow flag 0 [Clearing conditions] * Write 0 in the TME bit * Read TCSR when OVF = 1, then write 0 in OVFA [Setting condition] When TCNT overflows (changes from H'FF to H'00) (When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.) Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer: Generates a reset or NMI interrupt when TCNT overflows 1 Note: * Only 0 can be written, to clear the flag. 800 TCNT0--Timer Counter 0 TCNT1--Timer Counter 1 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W H'FFA8 (W), H'FFA9 (R) H'FFEA (W), H'FFEB (R) 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 WDT0 WDT1 R/W Up-counter P1PCR--Port 1 MOS Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFAC 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port 1 P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR R/W Control of port 1 built-in MOS input pull-ups P2PCR--Port 2 MOS Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFAD 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port 2 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR R/W Control of port 2 built-in MOS input pull-ups P3PCR--Port 3 MOS Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFAE 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port 3 P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR R/W Control of port 3 built-in MOS input pull-ups 801 P1DDR--Port 1 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FFB0 3 0 W 2 0 W 1 0 W 0 0 Port 1 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR W Specification of input or output for port 1 pins P2DDR--Port 2 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FFB1 3 0 W 2 0 W 1 0 W 0 0 W Port 2 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Specification of input or output for port 2 pins P1DR--Port 1 Data Register Bit Initial value Read/Write 7 P17DR 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W H'FFB2 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 Port 1 P10DR 0 R/W Output data for port 1 pins P2DR--Port 2 Data Register Bit Initial value Read/Write 7 P27DR 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 P24DR 0 R/W H'FFB3 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 Port 2 P20DR 0 R/W Output data for port 2 pins 802 P3DDR--Port 3 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FFB4 3 0 W 2 0 W 1 0 W 0 0 Port 3 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR W Specification of input or output for port 3 pins P4DDR--Port 4 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FFB5 3 0 W 2 0 W 1 0 W 0 0 Port 4 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR W Specification of input or output for port 4 pins P3DR--Port 3 Data Register Bit Initial value Read/Write 7 P37DR 0 R/W 6 P36DR 0 R/W 5 P35DR 0 R/W 4 P34DR 0 R/W H'FFB6 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 Port 3 P30DR 0 R/W Output data for port 3 pins P4DR--Port 4 Data Register Bit Initial value Read/Write 7 P47DR 0 R/W 6 P46DR 0 R/W 5 P45DR 0 R/W 4 P44DR 0 R/W H'FFB7 3 P43DR 0 R/W 2 P42DR 0 R/W 1 P41DR 0 R/W 0 Port 4 P40DR 0 R/W Output data for port 4 pins 803 P5DDR--Port 5 Data Direction Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'FFB8 3 -- 1 -- 2 0 W 1 0 W 0 0 W Port 5 P52DDR P51DDR P50DDR Specification of input or output for port 5 pins P6DDR--Port 6 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'FFB9 3 0 W 2 0 W 1 0 W 0 0 Port 6 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR W Specification of input or output for port 6 pins P5DR--Port 5 Data Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'FFBA 3 -- 1 -- 2 P52DR 0 R/W 1 P51DR 0 R/W 0 Port 5 P50DR 0 R/W Output data for port 5 pins P6DR--Port 6 Data Register Bit Initial value Read/Write 7 P67DR 0 R/W 6 P66DR 0 R/W 5 P65DR 0 R/W 4 P64DR 0 R/W H'FFBB 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0 Port 6 P60DR 0 R/W Output data for port 6 pins 804 P8DDR--Port 8 Data Direction Register Bit Initial value Read/Write 7 -- 1 -- 6 0 W 5 0 W 4 0 W H'FFBD 3 0 W 2 0 W 1 0 W 0 0 Port 8 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR W Specification of input or output for port 8 pins P7PIN--Port 7 Input Data Register Bit Initial value Read/Write 7 P77PIN --* R 6 --* R 5 --* R 4 --* R H'FFBE 3 --* R 2 --* R 1 --* R 0 Port 7 P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN --* R Port 7 pin states Note: * Determined by state of pins P77 to P70. P8DR--Port 8 Data Register Bit Initial value Read/Write 7 -- 1 -- 6 P86DR 0 R/W 5 P85DR 0 R/W 4 P84DR 0 R/W H'FFBF 3 P83DR 0 R/W 2 P82DR 0 R/W 1 P81DR 0 R/W 0 Port 8 P80DR 0 R/W Output data for port 8 pins 805 P9DDR--Port 9 Data Direction Register Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 1 W 0 W 0 W 7 6 5 4 H'FFC0 3 2 1 Port 9 0 P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Specification of input or output for port 9 pins P9DR--Port 9 Data Register Bit Initial value Read/Write 7 P97DR 0 R/W 6 P96DR --* R 5 P95DR 0 R/W 4 P94DR 0 R/W H'FFC1 3 P93DR 0 R/W 2 P92DR 0 R/W 1 P91DR 0 R/W 0 Port 9 P90DR 0 R/W Output data for port 9 pins Note: * Determined by state of pin P96. IER--IRQ Enable Register Bit Initial value Read/Write 7 IRQ7E 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W H'FFC2 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W Interrupt Controller 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ7 to IRQ0 enable 0 1 IRQn interrupt disabled IRQn interrupt enabled (n = 7 to 0) 806 STCR--Serial Timer Control Register Bit Initial value Read/Write 7 IICS 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W H'FFC3 3 FLSHE 0 R/W 2 -- 0 R/W 1 ICKS1 0 R/W 0 System ICKS0 0 R/W Internal Clock Source Select 1 and 0*1 Reserved Flash memory control register enable 0 1 Flash memory control register not selected Flash memory control register selected I2C master enable 0 1 CPU access to I2C bus interface data and control registers is disabled CPU access to I2C bus interface data and control registers is enabled I2C transfer select 1 and 0*2 Reserved Notes: 1. Used for 8-bit timer input clock selection. For details, see section 12.2.4, Timer Control Register (TCR). 2. Used for I2C bus interface transfer clock selection. For details, see section 16.2.4, I2C Bus Mode Register (ICMR). 807 SYSCR--System Control Register Bit Initial value Read/Write 7 CS2E 0 R/W 6 IOSE 0 R/W 5 INTM1 0 R 4 INTM0 0 R/W H'FFC4 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 System RAME 1 R/W RAM Enable 0 1 On-chip RAM is disabled On-chip RAM is enabled Host interface enable 0 Addresses H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF are used for access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers 1 Addresses H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF are used for access to host interface data registers and control registers, and keyboard controller and MOS input pull-up control registers NMI edge select 0 1 Falling edge Rising edge External reset 0 1 Reset generated by watchdog timer overflow Reset generated by an external reset Interrupt control mode select 0 0 1 IOS enable 0 1 The AS/IOS pin functions as the address strobe pin (Low output when accessing an external area) The AS/IOS pin functions as the I/O strobe pin (Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F) Interrupt control mode 0 Interrupt control mode 1 CS2 enable SYSCR HICR Bit 7 Bit 0 CS2E FGA20E 0 0 1 1 0 1 Description CS2 pin function halted (CS2 fixed high internally) CS2 pin function selected for P81/CS2 pin CS2 pin function selected for P90/ECS2 pin 808 MDCR--Mode Control Register Bit Initial value Read/Write 7 EXPE --* R/W* 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FFC5 3 -- 0 -- 2 -- 0 -- 1 MDS1 --* R System 0 MDS0 --* R Mode pin state Expanded mode enable 0 1 Single-chip mode selected Expanded mode selected Note: * Determined by the MD1 and MD0 pins. 809 BCR--Bus Control Register Bit Initial value Read/Write 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W H'FFC6 3 0 R/W 2 -- 1 R/W 1 IOS1 1 R/W Bus Controller 0 IOS0 1 R/W BRSTRM BRSTS1 BRSTS0 IOS select IOS1 IOS0 Addresses for which AS/IOS is low output when IOSE = 1 0 0 1 1 0 1 Low output when accessing addresses H'(FF)F000 to H'(FF)F03F Low output when accessing addresses H'(FF)F000 to H'(FF)F0FF Low output when accessing addresses H'(FF)F000 to H'(FF)F3FF Low output when accessing addresses H'(FF)F000 to H'(FF)FE4F Burst cycle select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access Burst cycle select 1 0 1 Burst cycle comprises 1 state Burst cycle comprises 2 states Burst ROM enable 0 Reserved 1 Basic bus interface Burst ROM interface Idle cycle insert 0 0 1 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles 810 WSCR--Wait State Control Register Bit Initial value Read/Write 7 RAMS 0 R/W 6 RAM0 0 R/W 5 ABW 1 R/W 4 AST 1 R/W H'FFC7 3 WMS1 0 R/W 2 WMS0 0 R/W 1 WC1 1 R/W Bus Controller 0 WC0 1 R/W Wait count 1 and 0 0 0 1 No program wait states are inserted 1 program wait state is inserted in external memory space accesses 2 program wait states are inserted in external memory space accesses 3 program wait states are inserted in external memory space accesses 1 0 1 Reserved Wait mode select 1 and 0 0 1 0 1 0 1 Access state control 0 External memory space is designated as 2-state access space Wait state insertion in external memory space accesses is disabled External memory space is designated as 3-state access space Wait state insertion in external memory space accesses is enabled Program wait mode Wait disabled mode Pin wait mode Pin auto-wait mode 1 Bus width control 0 1 External memory space designated as 16-bit access space (illegal setting in the H8S/2138 and H8S/2134) External memory space designated as 8-bit access space 811 TCR0--Timer Control Register 0 TCR1--Timer Control Register 1 TCRX--Timer Control Register X TCRY--Timer Control Register Y Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W H'FFC8 H'FFC9 H'FFF0 H'FFF0 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 TMR0 TMR1 TMRX TMRY CKS0 0 R/W Clock select 2 to 0 Channel Counter clear 1 and 0 0 0 1 0 1 Clear is disabled Cleared on compare match A Cleared on compare match B Cleared on rising edge of external reset input 1 1 Timer overflow interrupt enable 0 1 OVF interrupt request (OVI) is disabled OVF interrupt request (OVI) is enabled 1 0 0 0 0 Bit 2 Bit 1 Bit 0 Clock input disabled Internal clock: counting at falling edge of o/2 1 0*1 Internal clock: counting at falling edge of o/64 Internal clock: counting at falling edge of o/32 1*1 Internal clock: counting at falling edge of o/1024 Internal clock: counting at falling edge of o/256 0 0 Counting at TCNT1 overflow signal*2 Clock input disabled Internal clock: counting at falling edge of o/2 0*1 Internal clock: counting at falling edge of o/64 Internal clock: counting at falling edge of o/128 1*1 Internal clock: counting at falling edge of o/1024 Compare match interrupt enable A 0 1 CMFA interrupt request (CMIA) is disabled CMFA interrupt request (CMIA) is enabled X 1 0 0 0 1 1 Y 0 0 0 1 1 All 1 0 0 1 0 0 1 Compare Match Interrupt Enable B 0 1 CMFB interrupt request (CMIB) is disabled CMFB interrupt request (CMIB) is enabled 0 1 0 0 1 0 1 0 1 0 1 Internal clock: counting at falling edge of o/2048 Count at TCNT0 compare match A*2 Clock input disabled Internal clock: counting on o Internal clock: counting at falling edge of o/2 Internal clock: counting at falling edge of o/4 Clock input disabled Clock input disabled Internal clock: counting at falling edge of o/4 Internal clock: counting at falling edge of o/256 Internal clock: counting at falling edge of o/2048 Clock input disabled External clock: counting at rising edge External clock: counting at falling edge External clock: counting at both rising and falling edges Description CKS2 CKS1 CKS0 0 0 0 1*1 Internal clock: counting at falling edge of o/8 1 1*1 Internal clock: counting at falling edge of o/8 Notes: 1. Selected by ICKS1 and ICKS0 in STCR. For details, see section 12.2.4, Timer Control Register (TCR). 2. If the clock input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. 812 TCSR0--Timer Control/Status Register 0 TCSR0 Bit Initial value Read/Write H'FFCA TMR0 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Output select 1 and 0 0 1 0 1 0 1 Output select 3 and 2 0 1 0 1 0 1 A/D trigger enable 0 1 A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled No change at compare match B 0 output at compare match B 1 output at compare match B Output inverted at compare match B (toggle output) No change at compare match A 0 output at compare match A 1 output at compare match A Output inverted at compare match A (toggle output) Timer overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] When TCNT overflows from H'FF to H'00 Compare match flag A 0 [Clearing conditions] * Read CMFA when CMFA = 1, then write 0 in CMFA * When the DTC is activated by a CMIA interrupt [Setting condition] When TCNT = TCORA 1 Compare match flag B 0 [Clearing conditions] * Read CMFB when CMFB = 1, then write 0 in CMFB * When the DTC is activated by a CMIB interrupt [Setting condition] When TCNT = TCORB 1 Note: * Only 0 can be written in bits 7 to 5, to clear the flags. 813 TCSR1--Timer Control/Status Register 1 TCSR1 Bit Initial value Read/Write H'FFCB TMR1 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Output select 1 and 0 0 1 0 1 0 1 No change at compare match A 0 output at compare match A 1 output at compare match A Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 1 0 1 No change at compare match B 0 output at compare match B 1 output at compare match B Output inverted at compare match B (toggle output) Timer overflow flag 0 1 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] When TCNT overflows from H'FF to H'00 Compare match flag A 0 [Clearing conditions] * Read CMFA when CMFA = 1, then write 0 in CMFA * When the DTC is activated by a CMIA interrupt [Setting condition] When TCNT = TCORA 1 Compare match flag B 0 [Clearing conditions] * Read CMFB when CMFB = 1, then write 0 in CMFB * When the DTC is activated by a CMIB interrupt [Setting condition] When TCNT = TCORB 1 Note: * Only 0 can be written in bits 7 to 5, to clear the flags. 814 TCORA0--Time Constant Register A0 TCORA1--Time Constant Register A1 TCORB0--Time Constant Register B0 TCORB1--Time Constant Register B1 TCORAY--Time Constant Register AY TCORBY--Time Constant Register BY TCORC--Time Constant Register C TCORAX--Time Constant Register AX TCORBX--Time Constant Register BX TCORA0 TCORB0 Bit Initial value 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFCC H'FFCD H'FFCE H'FFCF H'FFF2 H'FFF3 H'FFF5 H'FFF6 H'FFF7 TCORA1 TCORB1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TMR0 TMR1 TMR0 TMR1 TMRY TMRY TMRX TMRX TMRX 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Compare match flag (CMF) is set when TCOR and TCNT values match TCORAX, TCORAY TCORBX, TCORBY Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Compare match flag (CMF) is set when TCOR and TCNT values match TCORC Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Compare match C signal is generated when sum of TCORC and TICR contents match TCNT value 815 TCNT0--Timer Counter 0 TCNT1--Timer Counter 1 TCNTX--Timer Counter X TCNTY--Timer Counter Y TCNT0 Bit Initial value 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFD0 H'FFD1 H'FFF4 H'FFF4 TCNT1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TMR0 TMR1 TMRX TMRY 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TCNTX, TCNTY Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Up-counter 816 PWOERA--PWM Output Enable Register A PWOERB--PWM Output Enable Register B Bit PWOERA Initial value Read/Write Bit PWOERB Initial value Read/Write 7 OE7 0 R/W 7 OE15 0 R/W 6 OE6 0 R/W 6 OE14 0 R/W 5 OE5 0 R/W 5 OE13 0 R/W 4 OE4 0 R/W 4 OE12 0 R/W H'FFD3 H'FFD2 3 OE3 0 R/W 3 OE11 0 R/W 2 OE2 0 R/W 2 OE10 0 R/W 1 OE1 0 R/W 1 OE9 0 R/W PWM PWM 0 OE0 0 R/W 0 OE8 0 R/W Switching between PWM output and port output DDR 0 1 OE 0 1 0 1 Port input Port input Port output or PWM 256/256 output PWM output (0 to 255/256 output) Description PWDPRA--PWM Data Polarity Register A PWDPRB--PWM Data Polarity Register B Bit PWDPRA Initial value Read/Write Bit PWDPRB Initial value Read/Write 7 OS7 0 R/W 7 OS15 0 R/W 6 OS6 0 R/W 6 OS14 0 R/W 5 OS5 0 R/W 5 OS13 0 R/W 4 OS4 0 R/W 4 OS12 0 R/W H'FFD5 H'FFD4 3 OS3 0 R/W 3 OS11 0 R/W 2 OS2 0 R/W 2 OS10 0 R/W 1 OS1 0 R/W 1 OS9 0 R/W PWM PWM 0 OS0 0 R/W 0 OS8 0 R/W PWM output polarity control 0 PWM direct output (PWDR value corresponds to high width of output) 1 PWM inverted output (PWDR value corresponds to low width of output) 817 PWSL--PWM Register Select Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 -- 1 -- 4 -- 0 -- H'FFD6 3 RS3 0 R/W 2 RS2 0 R/W 1 RS1 0 R/W 0 PWM PWCKE PWCKS RS0 0 R/W Register Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 PWM clock enable, PWM clock select PWSL Bit 7 0 1 Bit 6 -- 0 1 PCSR Bit 2 -- -- 0 1 Bit 1 -- -- 0 1 0 1 Description Clock input disabled o (system clock) selected o/2 selected o/4 selected o/8 selected o/16 selected 0 PWDR0 selected 1 PWDR1 selected 0 PWDR2 selected 1 PWDR3 selected 0 PWDR4 selected 1 PWDR5 selected 0 PWDR6 selected 1 PWDR7 selected 0 PWDR8 selected 1 PWDR9 selected 0 PWDR10 selected 1 PWDR11 selected 0 PWDR12 selected 1 PWDR13 selected 0 PWDR14 selected 1 PWDR15 selected PWCKE PWCKS PWCKB PWCKA 818 PWDR0 to PWDR15--PWM Data Registers Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFD7 3 0 R/W 2 0 R/W 1 0 R/W 0 0 PWM R/W Specifies duty factor of basic output pulse and number of additional pulses ADDRAH--A/D Data Register AH ADDRAL--A/D Data Register AL ADDRBH--A/D Data Register BH ADDRBL--A/D Data Register BL ADDRCH--A/D Data Register CH ADDRCL--A/D Data Register CL ADDRDH--A/D Data Register DH ADDRDL--A/D Data Register DL ADDRH Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 ADDRL 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Stores A/D data Correspondence between analog input channels and ADDR registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 or CIN0-CIN7 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD 819 ADCSR--A/D Control/Status Register Bit Initial value Read/Write 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W H'FFE8 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W A/D Converter 0 CH0 0 R/W Channel select Group selection CH2 0 Channel selection CH1 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 Single mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 or CIN0-7 AN7 AN0 AN0, AN1 AN0, AN1, AN2 AN0, AN1, AN2, AN3 AN4 AN4, AN5 AN4, AN5, AN6 or CIN0-7 AN4, AN5, AN6 or CIN0-7, AN7 Description Scan mode Clock select 0 1 Conversion time = 266 states (max.) Conversion time = 134 states (max.) Scan mode 0 1 A/D start 0 1 A/D conversion stopped * Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends * Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode Single mode Scan mode A/D interrupt enable 0 1 A/D end flag 0 [Clearing conditions] * When 0 is written in the to ADF flag after reading ADF = 1 * When the DTC is activated by an ADI interrupt, and ADDR is read [Setting conditions] * Single mode: When A/D conversion ends * Scan mode: When A/D conversion ends on all specified channels A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled 1 Note: * Only 0 can be written, to clear the flag. 820 ADCR--A/D Control Register Bit Initial value Read/Write 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- H'FFE9 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- A/D Converter 0 -- 1 -- Timer trigger select 0 1 0 1 0 1 Start of A/D conversion by external trigger is disabled Start of A/D conversion by external trigger is disabled Start of A/D conversion by external trigger (8-bit timer) is enabled Start of A/D conversion by external trigger pin is enabled 821 TCSR1--Timer Control/Status Register 1 TCSR1 Bit Initial value Read/Write H'FFEA WDT1 7 OVF 0 R/(W)*1 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select 2 to 0 PSS CKS2 CKS1 CKS0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Reset or NMI 0 1 Prescaler select*2 0 1 Timer enable 0 1 Timer mode select 0 1 Overflow flag 0 [Clearing conditions] * When 0 is written in the TME bit * When 0 is written in OVF after reading TCSR when OVF = 1 [Setting condition] When TCNT overflows from H'FF to H'00 When internal reset request is selected in watchdog timer mode, OVF is cleared automatically by an internal reset after being set Interval timer mode: Interval timer interrupt request (WOVI) sent to CPU when TCNT overflows Watchdog timer mode: Reset or NMI interrupt request sent to CPU when TCNT overflows TCNT is initialized to H'00 and halted TCNT counts TCNT counts on a o-based prescaler (PSM) scaled clock TCNT counts on a oSUB-based prescaler (PSS) scaled clock NMI interrupt requested Internal reset requested Clock o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 oSUB/2 oSUB/4 oSUB/8 oSUB/16 oSUB/32 oSUB/64 oSUB/128 oSUB/256 1 Notes: 1. Only 0 can be written, to clear the flag. 2. For operation control when a transition is made to power-down mode, see section 23.2.3, Timer Control/Status Register (TCSR). 822 HICR--Host Interface Control Register Bit Initial value Slave R/W Host R/W 7 -- 1 -- -- 6 -- 1 -- -- 5 -- 1 -- -- 4 -- 1 -- -- H'FFF0 3 -- 1 -- -- 2 IBFIE2 0 R/W -- 1 0 R/W -- 0 0 R/W -- HIF IBFIE1 FGA20E Fast gate A20 enable 0 1 Fast gate A20 function disabled Fast gate A20 function enabled Input data register interrupt enable 1 0 Input data register (IDR1) receive complete interrupt is disabled Input data register (IDR1) receive complete interrupt is enabled 1 Input data register full interrupt enable 2 0 1 Input data register (IDR2) receive complete interrupt is disabled Input data register (IDR2) receive complete interrupt is enabled 823 TCSRX--Timer Control/Status Register X TCSRX Bit Initial value Read/Write H'FFF1 TMRX 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICF 0 R/(W)* 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Output select 1 and 0 0 1 0 1 0 1 No change at compare match A 0 output at compare match A 1 output at compare match A Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 1 0 1 Input capture flag 0 1 [Clearing condition] Read ICF when ICF = 1, then write 1 in ICF [Setting condition] When a rising edge followed by a falling edge is detected in the external reset signal after the ICST bit in TCONRI has been set to 1 No change at compare match B 0 output at compare match B 1 output at compare match B Output inverted at compare match B (toggle output) Timer overflow flag 0 1 [Clearing condition] When 0 is written in OVF after reading OVF = 1 [Setting condition] When TCNT overflows from H'FF to H'00 Compare match flag A 0 [Clearing conditions] * When 0 is written in CMFA after reading CMFA = 1 * When the DTC is activated by a CMIA interrupt [Setting condition] When TCNT = TCORA 1 Compare match flag B 0 [Clearing conditions] * When 0 is written in CMFB after reading CMFB = 1 * When the DTC is activated by a CMIB interrupt [Setting condition] When TCNT = TCORB 1 Note: * Only 0 can be written in bits 7 to 4, to clear the flags. 824 TCSRY--Timer Control/Status Register Y TCSRY Bit Initial value Read/Write H'FFF1 TMRY 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICIE 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Output select 1 and 0 0 1 0 1 0 1 No change at compare match A 0 output at compare match A 1 output at compare match A Output inverted at compare match A (toggle output) Output select 3 and 2 0 1 0 1 0 1 No change at compare match B 0 output at compare match B 1 output at compare match B Output inverted at compare match B (toggle output) Input capture interrupt enable 0 1 Interrupt request by ICF (ICIX) is disabled Interrupt request by ICF (ICIX) is enabled Timer overflow flag 0 1 [Clearing condition] When 0 is written in OVF after reading OVF = 1 [Setting condition] When TCNT overflows from H'FF to H'00 Compare match flag A 0 [Clearing conditions] * When 0 is written in CMFA after reading CMFA = 1 * When the DTC is activated by a CMIA interrupt [Setting condition] When TCNT = TCORA 1 Compare match flag B 0 [Clearing conditions] * When 0 is written in CMFB after reading CMFB = 1 * When the DTC is activated by a CMIB interrupt [Setting condition] When TCNT = TCORB 1 Note: * Only 0 can be written in bits 7 to 5, to clear the flags. 825 KMIMR--Keyboard Matrix Interrupt Mask Register KMIMR Bit Initial value Read/Write 7 1 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'FFF1 Interrupt Controller 2 1 R/W 1 1 R/W 0 1 R/W KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Keyboard matrix interrupt mask 0 1 Key-sense input interrupt requests enabled Key-sense input interrupt requests disabled TICRR--Input Capture Register R TICRF--Input Capture Register F Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'FFF2 H'FFF3 2 0 R 1 0 R TMRX TMRX 0 0 R Stores TCNT value at fall of external trigger input KMPCR--Port 6 MOS Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFF2 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port 6 KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR R/W Control of port 6 built-in MOS input pull-ups Note: KMPCR has the same address as TICRR/TCORAY of TMRX/TMRY. When selecting KMPCR, set the HIE bit to 1 in SYSCR. 826 IDR1--Input Data Register 1 IDR2--Input Data Register 2 Bit Initial value Slave R/W Host R/W 7 IDR7 -- R W 6 IDR6 -- R W 5 IDR5 -- R W 4 IDR4 -- R W H'FFF4 H'FFFC 3 IDR3 -- R W 2 IDR2 -- R W 1 IDR1 -- R W 0 IDR0 -- R W HIF HIF Stores host data bus contents at rise of IOW when CS is low ODR1--Output Data Register 1 ODR2--Output Data Register 2 Bit Initial value Slave R/W Host R/W 7 ODR7 -- R/W R 6 ODR6 -- R/W R 5 ODR5 -- R/W R 4 ODR4 -- R/W R H'FFF5 H'FFFD 3 ODR3 -- R/W R 2 ODR2 -- R/W R 1 ODR1 -- R/W R 0 HIF HIF ODR0 -- R/W R ODR contents are output to the host data bus when HA0 is low, CS is low, and IOR is low TISR--Timer Input Select Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'FFF5 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 IS 0 TMRY R/W Input select 0 1 IVG signal is selected (H8S/2138 Series) External clock/reset input is disabled (H8S/2134 Series) VSYNCI/TMIY (TMCIY/TMRIY) is selected 827 STR1--Status Register 1 STR2--Status Register 2 Bit Initial value Slave R/W Host R/W 7 DBU 0 R/W R 6 DBU 0 R/W R 5 DBU 0 R/W R 4 DBU 0 R/W R H'FFF6 H'FFFE 3 C/D 0 R R 2 DBU 0 R/W R 1 IBF 0 R R 0 OBF 0 R/(W) R HIF HIF User-defined bits Output buffer full 0 [Clearing condition] When the host processor reads ODR or the slave writes 0 in the OBF bit [Setting condition] When the slave processor writes to ODR 1 Input buffer full 0 1 [Clearing condition] When the slave processor reads IDR [Setting condition] When the host processor writes to IDR Command/data 0 1 Contents of input data register (IDR) are data Contents of input data register (IDR) are a command DADR0--D/A Data Register 0 DADR1--D/A Data Register 1 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFF8 H'FFF9 3 0 R/W 2 0 R/W 1 0 D/A Converter D/A Converter 0 0 R/W R/W Stores data for D/A conversion 828 DACR--D/A Control Register Bit Initial value Read/Write 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 -- H'FFFA 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- D/A Converter 0 -- 1 -- D/A enabled DAOE1 DAOE0 0 0 1 DAE * 0 1 1 0 0 1 1 * Conversion result Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversion enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled *: Don't care D/A output enable 0 0 1 Analog output DA0 disabled D/A conversion is enabled on channel 0. Analog output DA0 is enabled D/A output enable 1 0 1 Analog output DA1 disabled D/A conversion is enabled on channel 1. Analog output DA1 is enabled 829 TCONRI--Timer Connection Register I Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 ICST 0 R/W H'FFFC 3 HFINV 0 R/W 2 VFINV 0 R/W Timer Connection 1 HIINV 0 R/W 0 VIINV 0 R/W SIMOD1 SIMOD0 SCONE Input synchronization signal inversion 0 The VSYNCI pin state is used directly as the VSYNCI input The VSYNCI pin state is inverted before use as the VSYNCI input 1 Input synchronization signal inversion 0 1 The HSYNCI and CSYNCI pin states are used directly as the HSYNCI and CSYNCI inputs The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and CSYNCI inputs Input synchronization signal inversion 0 1 The VFBACKI pin state is used directly as the VFBACKI input The VFBACKI pin state is inverted before use as the VFBACKI input Input synchronization signal inversion 0 1 The HFBACKI pin state is used directly as the HFBACKI input The HFBACKI pin state is inverted before use as the HFBACKI input Input capture start bit 0 The TICRR and TICRF input capture functions are stopped [Clearing condition] When a rising edge followed by a falling edge is detected on TMRIX The TICRR and TICRF input capture functions are operating (Waiting for detection of a rising edge followed by a falling edge on TMRIX) [Setting condition] When 1 is written in ICST after reading ICST = 0 1 Synchronization signal connection enable SCONE 0 Mode Normal connection FTIA FTIA input FTIB FTIB input TMO1 signal FTIC FTIC input VFBACKI input FTID FTID input IHI signal TMCI1 TMCI1 input IHI signal TMRI1 TMRI1 input IVI inverse signal 1 Synchronization IVI signal connecsignal tion mode Input synchronization mode select 1 and 0 SIMOD1 0 SIMOD0 0 1 1 0 1 Mode No signal S-on-G mode Composite mode Separate mode IHI signal HFBACKI input CSYNCI input HSYNCI input HSYNCI input IVI signal VFBACKI input PDC input PDC input VSYNCI input 830 TCONRO--Timer Connection Register O Bit Initial value Read/Write 7 HOE 0 R/W 6 VOE 0 R/W 5 CLOE 0 R/W 4 CBOE 0 R/W H'FFFD 3 HOINV 0 R/W 2 VOINV 0 R/W Timer Connection 1 0 R/W 0 0 R/W CLOINV CBOINV Output synchronization signal inversion 0 The CBLANK signal is used directly as the CBLANK output The CBLANK signal is inverted before use as the CBLANK output 1 Output synchronization signal inversion 0 The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the CLAMPO output The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as the CLAMPO output 1 Output synchronization signal inversion 0 1 The IVO signal is used directly as the VSYNCO output The IVO signal is inverted before use as the VSYNCO output Output synchronization signal inversion 0 1 Output enable 0 1 The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin In mode 1 (expanded mode with on-chip ROM disabled): The P27/A15/PW15/CBLANK pin functions as the A15 pin In modes 2 and 3 (expanded modes with on-chip ROM enabled): The P27/A15/PW15/CBLANK pin functions as the CBLANK pin The IHO signal is used directly as the HSYNCO output The IHO signal is inverted before use as the HSYNCO output Output enable 0 1 Output enable 0 1 Output enable 0 1 The P44/TMO1/HIRQ1/HSYNCO pin functions as the P44/TMO1/HIRQ1 pin The P44/TMO1/HIRQ1/HSYNCO pin functions as the HSYNCO pin The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the P61/FTOA/KIN1/CIN1 pin The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the VSYNCO pin The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the P64/FTIC/KIN4/CIN4 pin The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin 831 TCONRS--Timer Connection Register S Bit Initial value Read/Write 7 TMRX/Y 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFFE 3 0 R/W 2 0 R/W Timer Connection 1 0 R/W 0 0 R/W ISGENE HOMOD1 HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0 Clamp waveform mode select 1 and 0 ISGENE CLMOD1 CLMOD0 0 0 0 1 1 1 0 1 0 0 1 1 0 1 Vertical synchronization output mode select 1 and 0 ISGENE VOMOD1 VOMOD0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Horizontal synchronization output mode select 1 and 0 ISGENE HOMOD1 HOMOD0 0 0 0 1 1 1 0 1 0 0 1 1 0 1 Internal synchronization signal select TMRX/TMRY access select 0 1 The TMRX registers are accessed at addresses H'FFF0 to H'FFF5 The TMRY registers are accessed at addresses H'FFF0 to H'FFF5 The IHG signal is selected Description The IHI signal (without 2fH modification) is selected The IHI signal (with 2fH modification) is selected The CLI signal is selected Description The IVI signal (without fall modification or IHI synchronization) is selected The IVI signal (without fall modification, with IHI synchronization) is selected The IVI signal (with fall modification, without IHI synchronization) is selected The IVI signal (with fall modification and IHI synchronization) is selected The IVG signal is selected The CL4 signal is selected Description The CL1 signal is selected The CL2 signal is selected The CL3 signal is selected 832 SEDGR--Edge Sense Register Bit Initial value Read/Write 7 VEDG 0 R/(W) *1 H'FFFF 5 CEDG 0 R/(W) *1 Timer Connection 2 0 1 IHI --*2 *1 6 HEDG 0 R/(W) *1 4 0 R/(W) *1 3 0 R/(W) *1 0 IVI --*2 R HFEDG VFEDG PREQF R/(W) R IVI signal level 0 1 The IVI signal is low The IVI signal is high IHI signal level 0 1 The IHI signal is low The IHI signal is high Pre-equalization flag 0 [Clearing condition] When 0 is written in PREQF after reading PREQF = 1 [Setting condition] When an IHI signal 2fH modification condition is detected 1 VFBACKI edge 0 1 [Clearing condition] When 0 is written in VFEDG after reading VFEDG = 1 [Setting condition] When a rising edge is detected on the VFBACKI pin HFBACKI edge 0 1 CSYNCI edge 0 1 HSYNCI edge 0 1 VSYNCI edge 0 1 [Clearing condition] When 0 is written in VEDG after reading VEDG = 1 [Setting condition] When a rising edge is detected on the VSYNCI pin [Clearing condition] When 0 is written in HEDG after reading HEDG = 1 [Setting condition] When a rising edge is detected on the HSYNCI pin [Clearing condition] When 0 is written in CEDG after reading CEDG = 1 [Setting condition] When a rising edge is detected on the CSYNCI pin [Clearing condition] When 0 is written in HFEDG after reading HFEDG = 1 [Setting condition] When a rising edge is detected on the HFBACKI pin Notes: 1. Only 0 can be written, to clear the flags. 2. The initial value is undefined since it depends on the pin states. 833 834 Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Mode 2, 3 EXPE Mode 1 Reset R Q D P1nPCR C Hardware standby Mode 1 RP1P WP1P Reset R D Q P1nDDR C WP1D Internal address bus Internal data bus 8-bit PWM PWM output enable PWM output P1n Reset R Q D P1nDR C WP1 RP1 WP1P: Write to P1PCR WP1D: Write to P1DDR WP1: Write to port 1 RP1P: Read P1PCR RP1: Read port 1 n = 0 to 7 Figure C.1 Port 1 Block Diagram 835 C.2 Port 2 Block Diagrams Mode 2, 3 EXPE Mode 1 Reset R Q D P2nPCR C Hardware standby Mode 1 RP2P WP2P Reset R D Q P2nDDR C WP2D Internal address bus Internal data bus 8-bit PWM PWM output enable PWM output P2n Reset R Q D P2nDR C WP2 RP2 WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 n = 0 to 3 Figure C.2 Port 2 Block Diagram (Pins P20 to P23) 836 Mode 2, 3 EXPE IOSE Mode 1 Reset R Q D P2nPCR C Hardware standby Mode 1 RP2P WP2P Reset R D Q P2nDDR * C WP2D Internal data bus Internal address bus 8-bit PWM PWM output enable PWM output P2n Reset R Q D P2nDR C WP2 RP2 WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 n = 4 to 6 Figure C.3 Port 2 Block Diagram (Pins P24 to P26) 837 Mode 2, 3 EXPE IOSE Mode 1 Reset R Q D P27PCR C Hardware standby Mode 1 RP2P WP2P Reset R D Q P27DDR C WP2D Internal data bus Internal address bus 8-bit PWM PWM output enable PWM output P27 Reset R Q D P27DR C Mode 2, 3 WP2 Timer connection CBLANK CBLANK output enable RP2 WP2P: WP2D: WP2: RP2P: RP2: Write to P2PCR Write to P2DDR Write to port 2 Read P2PCR Read port 2 Figure C.4 Port 2 Block Diagram (Pin P27) 838 C.3 Port 3 Block Diagram Mode 2, 3 EXPE HI12E Mode 1 Reset R Q D P3nPCR C RP3P Hardware standby WP3P Reset R D Q P3nDDR C WP3D P3n Reset R Q D P3nDR C WP3 CS IOW RP3 External address read WP3P: Write to P3PCR WP3D: Write to P3DDR WP3: Write to port 3 RP3P: Read P3PCR RP3: Read port 3 n = 0 to 7 Figure C.5 Port 3 Block Diagram Host interface data bus Internal data bus 839 C.4 Port 4 Block Diagrams Reset R D Q P40DDR C WP4D Internal data bus SCI2 TxD2/IrTxD Transmit enable P40 Reset R Q D P40DR C WP4 RP4 8-bit timer 0 Counter clock input WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.6 Port 4 Block Diagram (Pin P40) 840 Reset R D Q P41DDR C WP4D Internal data bus 8-bit timer 0 8-bit timer output Output enable P41 Reset R Q D P41DR C WP4 RP4 SCI2 Receive enable RxD2/IrRxD WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.7 Port 4 Block Diagram (Pin P41) 841 Reset R D Q P42DDR C WP4D *1 Reset P42 *2 Internal data bus SCI2 Input enable Clock output Output enable Clock output Q D P42DR C WP4 R IIC1 SDA1 output Transmit enable RP4 SDA1 input WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Notes: 1. Output enable signal 2. Open drain control signal 8-bit timer 0 Reset input Figure C.8 Port 4 Block Diagram (Pin P42) 842 Reset R D Q P43DDR C WP4D Reset Internal data bus Host interface RESOBF2 (resets HIRQ11) P43 Q D P43DR C WP4 R RP4 8-bit timer 1 Counter clock input WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Timer connection HSYNCI input Figure C.9 Port 4 Block Diagram (Pin P43) 843 Reset R D Q P44DDR C WP4D Internal data bus Timer connection HSYNCO output Output enable Reset Host interface RESOBF1 (resets HIRQ1) P44 Q D P44DR C WP4 R 8-bit timer 1 TMO1 output Output enable RP4 WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Figure C.10 Port 4 Block Diagram (Pin P44) 844 Reset R D Q P45DDR C WP4D Reset Internal data bus Host interface RESOBF1 (resets HIRQ12) P45 Q D P45DR C WP4 R RP4 8-bit timer 1 Timer reset input WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Timer connection CSYNCI input Figure C.11 Port 4 Block Diagram (Pin P45) 845 Reset R D Q P4nDDR C WP4D Internal data bus 14-bit PWM PWX0, PWX1 output Output enable P4n Reset R Q D P4nDR C WP4 RP4 WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 n = 6 or 7 Figure C.12 Port 4 Block Diagram (Pins P46, P47) 846 C.5 Port 5 Block Diagrams Reset R D Q P50DDR C WP5D Internal data bus SCI0 Serial transmit data Output enable P50 Reset R Q D P50DR C WP5 RP5 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C.13 Port 5 Block Diagram (Pin P50) 847 Reset R D Q P51DDR C WP5D Internal data bus SCI0 Input enable Reset P51 R Q D P51DR C WP5 RP5 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Serial receive data Figure C.14 Port 5 Block Diagram (Pin P51) 848 Reset R D Q P52DDR C WP5D *1 Reset P52 *2 R Q D P52DR C WP5 Internal data bus SCI0 Input enable Clock output Output enable Clock input IIC0 SCL0 output Transmit enable RP5 SCL0 input WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Notes: 1. Output enable signal 2. Open drain control signal Figure C.15 Port 5 Block Diagram (Pin P52) 849 C.6 Port 6 Block Diagrams Reset R Q D KMPCR C RP6P Hardware standby WP6P Reset R D Q P6nDDR C WP6D Reset P6n R Q D P6nDR C WP6 Internal data bus 16-bit FRT FTCI input FTIA input FTIB input FTID input Timer connection 8-bit timers Y, X HFBACKI input, TMIX input, VSYNCI input, TMIY input, VFBACKI input Key-sense interrupt input KMIMR0, 2, 3, 5 A/D converter Analog input RP6 WP6P: Write to P6PCR WP6D: Write to P6DDR WP6: Write to port 6 RP6P: Read P6PCR RP6: Read port 6 n = 0, 2, 3, 5 Figure C.16 Port 6 Block Diagram (Pins P60, P62, P63, P65) 850 Reset R Q D KMPCR C RP6P Hardware standby WP6P Reset R D Q P61DDR C WP6D 16-bit FRT FTOA output Output enable Reset P61 R Q D P61DR C WP6 Internal data bus Timer connection VSYNCO output Output enable Key-sense interrupt input KMIMR1 A/D converter Analog input RP6 WP6P: WP6D: WP6: RP6P: RP6: Write to P6PCR Write to P6DDR Write to port 6 Read P6PCR Read port 6 Figure C.17 Port 6 Block Diagram (Pin P61) 851 Reset R Q D KMPCR C RP6P Hardware standby WP6P Reset R D Q P64DDR C WP6D Internal data bus Timer connection CLAMPO output Output enable Reset P64 R Q D P64DR C WP6 RP6 16-bit FRT FTIC input Key-sense interrupt input KMIMR4 A/D converter Analog input WP6P: WP6D: WP6: RP6P: RP6: Write to P6PCR Write to P6DDR Write to port 6 Read P6PCR Read port 6 Figure C.18 Port 6 Block Diagram (Pin P64) 852 Reset R Q D KMPCR C RP6P Hardware standby WP6P Reset R D Q P66DDR C WP6D Internal data bus 16-bit FRT FTOB output Output enable Reset P66 R Q D P66DR C WP6 RP6 KMIMR6 Other key-sense interrupt inputs IRQ6 input IRQ6 enable A/D converter Analog input WP6P: WP6D: WP6: RP6P: RP6: Write to P6PCR Write to P6DDR Write to port 6 Read P6PCR Read port 6 Figure C.19 Port 6 Block Diagram (Pin P66) 853 Reset R Q D KMPCR C RP6P Hardware standby WP6P Reset R D Q P67DDR C WP6D Internal data bus 8-bit timer X TMOX output Output enable Reset P67 R Q D P67DR C WP6 RP6 IRQ7 input IRQ7 enable A/D converter Analog input WP6P: WP6D: WP6: RP6P: RP6: Write to P6PCR Write to P6DDR Write to port 6 Read P6PCR Read port 6 Figure C.20 Port 6 Block Diagram (Pin P67) 854 C.7 Port 7 Block Diagrams RP7 P7n Internal data bus A/D converter Analog input RP7: Read port 7 n = 0 to 5 Figure C.21 Port 7 Block Diagram (Pins P70 to P75) RP7 P7n Internal data bus A/D converter Analog input D/A converter Output enable Analog output RP7: Read port 7 n = 6 or 7 Figure C.22 Port 7 Block Diagram (Pins P76, P77) 855 C.8 Port 8 Block Diagrams Reset R D Q P80DDR C WP8D Reset P80 R Q D P80DR C WP8 RP8 HIF HA0 input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.23 Port 8 Block Diagram (Pin P80) 856 Internal data bus HI12E EXPE Mode 2, 3 Reset R D Q P81DDR C WP8D Mode 2, 3 EXPE CS2E HI12E Internal data bus HIF GA20 output Output enable Reset P81 R Q D P81DR C WP8 RP8 HIF CS2 input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.24 Port 8 Block Diagram (Pin P81) 857 Reset R D Q P8nDDR C WP8D Reset P8n R Q D P8nDR C WP8 RP8 HIF HIFSD input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 n = 2, 3 (P82 only) Figure C.25 Port 8 Block Diagram (Pins P82, P83) 858 Internal data bus Reset R D Q P84DDR C WP8D Internal data bus SCI1 TxD1 Transmit enable IRQ3 input IRQ3 enable P84 Reset R Q D P84DR C WP8 RP8 WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.26 Port 8 Block Diagram (Pin P84) 859 Reset R D Q P85DDR C WP8D Internal data bus SCI1 Input enable Reset P85 R Q D P85DR C WP8 RP8 Serial receive data IRQ4 input IRQ4 enable WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.27 Port 8 Block Diagram (Pin P85) 860 Reset R D Q P86DDR C WP8D *1 Reset P86 *2 Internal data bus SCI1 Input enable Clock output Output enable Clock input Q D P86DR C WP8 R IIC1 SCL1 output Transmit enable RP8 SCL1 input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Notes: 1. Output enable signal 2. Open drain control signal IRQ5 input IRQ5 enable Figure C.28 Port 8 Block Diagram (Pin P86) 861 C.9 Port 9 Block Diagrams EXPE Mode 2, 3 GA20 HI12E CS2E Reset R D Q P90DDR C WP9D Reset P90 R Q D P90DR C WP9 RP9 HIF ECS2 input Internal data bus A/D converter External trigger input WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 IRQ2 input IRQ2 enable Figure C.29 Port 9 Block Diagram (Pin P90) 862 Reset R D Q P9nDDR C WP9D Reset P9n R Q D P9nDR C WP9 RP9 Internal data bus WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 n = 1 or 2 IRQ1 input IRQ0 input IRQ1 enable IRQ0 enable Figure C.30 Port 9 Block Diagram (Pins P91, P92) 863 Mode 2, 3 EXPE HI12E EXPE Reset R D Q P9nDDR C WP9D Internal data bus Bus controller RD output WR output AS/IOS output Reset P9n R Q D P9nDR C WP9 RP9 HIF IOR input IOW input CS1 input WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 n = 3 to 5 Figure C.31 Port 9 Block Diagram (Pins P93 to P95) 864 Reset Mode 1 Hardware standby SR D Q P96DDR C Subclock input enable P96 WP9D o output RP9 Internal data bus Subclock input WP9D: Write to P9DDR RP9: Read port 9 Figure C.32 Port 9 Block Diagram (Pin P96) 865 Reset R D Q P97DDR C WP9D *1 Internal data bus Bus controller Input enable EXPE Reset R Q D P97DR C WAIT input P97 *2 WP9 IIC0 SDA0 output Transmit enable RP9 SDA0 input WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Notes: 1. Output enable signal 2. Open drain control signal Figure C.33 Port 9 Block Diagram (Pin P97) 866 Appendix D Pin States D.1 Port States in Each Processing State I/O Port States in Each Processing State MCU Operating Mode Reset 1 2, 3 (EXPE = 1) L T Hardware Software Standby Standby Mode Mode T keep* Watch Mode keep* Sleep Mode keep* Subsleep Mode keep* Subactive Mode A7 to A0 Address output/ input port I/O port L T T keep* keep* keep* keep* A15 to A8 Address output/ input port I/O port T T T T T T D7 to D0 Program Execution State A7 to A0 Address output/ input port I/O port A15 to A8 Address output/ input port I/O port D7 to D0 Table D.1 Port Name Pin Name Port 1 A7 to A0 2, 3 (EXPE = 0) Port 2 A15 to A8 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 3 D7 to D0 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 4 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 5 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 6 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 7 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 8 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 97 T T keep keep keep keep T T T T T T T T keep keep keep keep T T keep keep keep keep T T keep keep keep keep keep keep keep keep I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port Input port Input port I/O port I/O port :$,7 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) T T T/keep T/keep T/keep T/keep :$,7/ I/O port I/O port :$,7/ I/O port I/O port keep keep keep keep 867 Table D.1 Port Name Pin Name Port 96 o EXCL I/O Port States in Each Processing State (cont) MCU Operating Mode Reset 1 Hardware Software Standby Standby Mode Mode Watch Mode Sleep Mode [DDR = 1] clock output [DDR = 0] T Subsleep Mode EXCL input Subactive Mode EXCL input Program Execution State Clock output/ EXCL input/ input port Clock T output T [DDR = 1] H EXCL input [DDR = 0] T 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 95 to 93 $6, :5, 5' 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) H T T H H H H $6, :5, 5' I/O port I/O port $6, :5, 5' I/O port I/O port keep T T keep keep keep keep keep keep keep Port 92 to 90 Legend: H: High L: Low T: High-impedance state keep: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, MOS input pullups remain on). Output ports maintain their previous state. Depending on the pins, the on-chip supporting modules may be initialized and the I/O port function determined by DDR and DR used. DDR: Data direction register Note: * In the case of address output, the last address accessed is retained. 868 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode E.1 Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the 5(6 signal low 10 system clock cycles before the 67%< signal goes low, as shown in figure E.1. 5(6 must remain low until 67%< signal goes low (minimum delay from 67%< low to 5(6 high: 0 ns). STBY t1 10tcyc RES t2 0 ns Figure E.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, 5(6 does not have to be driven low as in (1). E.2 Timing of Recovery from Hardware Standby Mode Drive the 5(6 signal low at least 100 ns before 67%< goes high to execute a reset. STBY t 100 ns RES tOSC Figure E.2 Timing of Recovery from Hardware Standby Mode 869 870 Appendix F Product Code Lineup Table F.1 H8S/2138 Series and H8S/2134 Series Product Code Lineup -- Preliminary -- Package (Hitachi Package Code) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) Product Type Product Code Mark Code HD6432138(***)FA HD6432138(***)TF Notes In planning stage H8S/2138 H8S/2138 Mask ROM Standard product HD6432138 Series version (5 V version, 4 V version, 3 V version) Version with on-chip HD6432138W HD6432138W(***)FA 80-pin QFP 2 I C bus interface (FP-80A) (5 V version, 4 V version, HD6432138W(***)TF 80-pin TQFP 3 V version) (TFP-80C) F-ZTAT version Version with on-chip 2 I C bus interface (5 V/4 V version) Low-voltage version (3 V version) HD64F2138 HD64F2138FA20 80-pin QFP (FP-80A) 80-pin QFP (FP-80A) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) Under development Under development In planning stage HD64F2138V HD64F2138VFA10 HD6432137(***)FA HD6432137(***)TF H8S/2137 Mask ROM Standard product HD6432137 version (5 V version, 4 V version, 3 V version) Version with on-chip HD6432137W HD6432137W(***)FA 80-pin QFP 2 I C bus interface (FP-80A) (5 V version, 4 V version, HD6432137W(***)TF 80-pin TQFP 3 V version) (TFP-80C) 871 Table F.1 H8S/2138 Series and H8S/2134 Series Product Code Lineup (cont) -- Preliminary -- Package (Hitachi Package Code) Product Type Product Code Mark Code Notes In planning stage H8S/2134 H8S/2134 Mask ROM Standard product HD6432134 Series version (5 V version, 4 V version, 3 V version) HD6432134(***)FA 80-pin QFP (FP-80A) HD6432134(***)TF 80-pin TQFP (TFP-80C) HD64F2134FA20 HD64F2134TF20 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) F-ZTAT version Standard product (5 V/4 V version) HD64F2134 Low-voltage version (3 V version) HD64F2134V HD64F2134VFA10 HD64F2134VTF10 H8S/2133 Mask ROM Standard product HD6432133 version (5 V version, 4 V version, 3 V version) HD6432133(***)FA 80-pin QFP (FP-80A) HD6432133(***)TF 80-pin TQFP (TFP-80C) HD6432132(***)FA 80-pin QFP (FP-80A) HD6432132(***)TF 80-pin TQFP (TFP-80C) HD64F2132RFA20 HD64F2132RTF20 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) In planning stage H8S/2132 Mask ROM Standard product HD6432132 version (5 V version, 4 V version, 3 V version) Under development F-ZTAT version Standard product (5 V/4 V version) HD64F2132R Under development Low-voltage version (3 V version) HD64F2132RV HD64F2132RVFA10 80-pin QFP (FP-80A) HD64F2132RVTF10 80-pin TQFP (TFP-80C) Under development H8S/2130 Mask ROM Standard product HD64F2130 version (5 V version, 4 V version, 3 V version) HD6432130(***)FA 80-pin QFP (FP-80A) HD6432130(***)TF 80-pin TQFP (TFP-80C) Under development Note: (***) is the ROM code. 2 The F-ZTAT version of the H8S/2138 has an on-chip I C bus interface as standard. The F-ZTAT 5 V/4 V version supports the operating ranges of the 5 V version and the 4 V version. The above table includes products in the planning stage or under development. Information on the status of individual products can be obtained from Hitachi's sales offices. 872 Appendix G Package Dimensions Figures G.1 and G.2 show the package dimensions of the H8S/2138 Series and H8S/2134 Series. 17.2 0.3 14 Unit: mm 41 40 60 61 17.2 0.3 80 1 *0.32 0.08 0.30 0.06 21 20 0.65 0.12 M 0.83 3.05 Max *0.17 0.05 0.15 0.04 2.70 1.6 0.10 +0.15 -0.10 0 - 8 0.8 0.3 0.10 *Dimension including the plating thickness Base material dimension Figure G.1 Package Dimensions (FP-80A) 873 14.0 0.2 12 60 61 41 40 Unit: mm 14.0 0.2 80 1 *0.22 0.05 0.20 0.04 20 0.10 M 1.25 21 0.5 *0.17 0.05 0.15 0.04 1.20 Max 1.00 1.0 0 - 8 0.5 0.1 0.10 *Dimension including the plating thickness Base material dimension Figure G.2 Package Dimensions (TFP-80C) 874 0.10 0.10 |
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